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target/mips32: optimize pracc access

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Update mips32 instructions, add barrier and sync related insts.
Add SYNC and barrier instruction blocks for memory access safety.

These instructions are not supported on Lexra and/or MIPSr1 CPUs,
detections were added and they will be executed conditionally.

Rework mips32_pracc_read/write_regs function.
Checkpatch-ignore: MACRO_ARG_REUSE

Change-Id: Ib14112f37ff1f060b1633df73d671a6b09bb2178
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7865
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Walter Ji
2023-08-29 13:27:49 +08:00
committed by Antonio Borneo
parent 019bf5f83c
commit b123128737
5 changed files with 208 additions and 39 deletions
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38
src/target/mips32.c
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@@ -796,6 +796,44 @@ static const struct cpu_entry *mips32_find_cpu_by_prid(uint32_t prid)
return &mips32_cpu_entry[MIPS32_NUM_CPU_ENTRIES - 1];
}
static bool mips32_cpu_is_lexra(struct mips_ejtag *ejtag_info)
{
return (ejtag_info->prid & PRID_COMP_MASK) == PRID_COMP_LEXRA;
}
static int mips32_cpu_get_release(struct mips_ejtag *ejtag_info)
{
return (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
}
/**
* mips32_cpu_support_sync - Checks CPU supports ordering
* @param[in] ejtag_info: MIPS EJTAG information structure.
*
* @brief MIPS ISA implemented on Lexra CPUs is MIPS-I, similar to R3000,
* which does not have the SYNC instruction alone with unaligned
* load/store instructions.
*
* @returns true if current CPU supports sync instruction(CPU is not Lexra)
*/
bool mips32_cpu_support_sync(struct mips_ejtag *ejtag_info)
{
return !mips32_cpu_is_lexra(ejtag_info);
}
/**
* mips32_cpu_support_hazard_barrier - Checks CPU supports hazard barrier
* @param[in] ejtag_info: MIPS EJTAG information structure.
*
* @brief hazard barrier instructions EHB and *.HB was introduced to MIPS from release 2.
*
* @returns true if current CPU supports hazard barrier(release > 1)
*/
bool mips32_cpu_support_hazard_barrier(struct mips_ejtag *ejtag_info)
{
return mips32_cpu_get_release(ejtag_info) > MIPS32_RELEASE_1;
}
/**
* mips32_cpu_probe - Detects processor type and applies necessary quirks.
* @param[in] target: The target CPU to probe.