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target/mips32: update coprocessor 0 command

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Update mips32 cp0 command, it accepts cp0 reg names now.
Updated mips32 cp0 description.

Change-Id: Ib23dd13519def77a657c9c5bb039276746207b9b
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7905
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
Tested-by: jenkins
This commit is contained in:
Walter Ji
2023-11-17 15:13:21 +08:00
committed by Antonio Borneo
parent 7de4b1202d
commit b2172ed7d7
3 changed files with 288 additions and 45 deletions
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10
src/target/mips32.h
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@@ -84,7 +84,7 @@
/* CP1 FIR register fields */
#define MIPS32_CP1_FIR_F64_SHIFT 22
static const struct {
static const struct mips32_cp0 {
unsigned int reg;
unsigned int sel;
const char *name;
@@ -202,7 +202,7 @@ static const struct {
{31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
};
#define MIPS32NUMCP0REGS ((int)ARRAY_SIZE(mips32_cp0_regs))
#define MIPS32NUMCP0REGS (ARRAY_SIZE(mips32_cp0_regs))
/* Insert extra NOPs after the DRET instruction on exit from debug. */
#define EJTAG_QUIRK_PAD_DRET BIT(0)
@@ -397,6 +397,12 @@ struct mips32_common {
int fdc;
int semihosting;
/* The cp0 registers implemented on different processor cores could be different, too.
* Here you can see most of the registers are implemented on interAptiv, which is
* a 2c4t SMP processor, it has more features than M-class processors, like vpe
* and other config registers for multhreading. */
uint32_t cp0_mask;
/* FPU enabled (cp0.status.cu1) */
bool fpu_enabled;
/* FPU mode (cp0.status.fr) */