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Introduce tcl config files for Synopsys HSDK board

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With this commit we add tcl configure files
for ARCv2 HS Development kit(HSDK). HSDK board
has Quad-core ARC HS38 CPU with L1 and L2
caches.

Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0
Signed-off-by: Evgeniy Didin <didin@synopsys.com>
Reviewed-on: http://openocd.zylin.com/5784
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Evgeniy Didin
2020-07-20 13:27:46 +03:00
committed by Antonio Borneo
parent 8fea8460db
commit b2821b6074
4 changed files with 180 additions and 0 deletions
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86
tcl/target/snps_hsdk.cfg Normal file
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# Copyright (C) 2019,2020 Synopsys, Inc.
# Anton Kolesov <anton.kolesov@synopsys.com>
# Didin Evgeniy <didin@synopsys.com>
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# HS Development Kit SoC.
#
# Contains quad-core ARC HS38.
#
source [find cpu/arc/hs.tcl]
set _coreid 0
set _dbgbase [expr ($_coreid << 13)]
# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
# OpenOCD is concerned EM and HS are identical.
set _CHIPNAME arc-em
# OpenOCD discovers JTAG TAPs in reverse order.
# ARC HS38 core 4
set _TARGETNAME $_CHIPNAME.cpu4
jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
$_TARGETNAME configure -coreid $_coreid
$_TARGETNAME configure -dbgbase $_dbgbase
# Flush L2$.
$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
set _coreid [expr $_coreid + 1]
set _dbgbase [expr ($_coreid << 13)]
arc_hs_init_regs
# Enable L2 cache support for core 4.
$_TARGETNAME arc cache l2 auto 1
# ARC HS38 core 3
set _TARGETNAME $_CHIPNAME.cpu3
jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
$_TARGETNAME configure -coreid $_coreid
$_TARGETNAME configure -dbgbase $_dbgbase
$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
set _coreid [expr $_coreid + 1]
set _dbgbase [expr ($_coreid << 13)]
arc_hs_init_regs
# Enable L2 cache support for core 3.
$_TARGETNAME arc cache l2 auto 1
# ARC HS38 core 2
set _TARGETNAME $_CHIPNAME.cpu2
jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
$_TARGETNAME configure -coreid $_coreid
$_TARGETNAME configure -dbgbase $_dbgbase
$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
set _coreid [expr $_coreid + 1]
set _dbgbase [expr ($_coreid << 13)]
arc_hs_init_regs
# Enable L2 cache support for core 2.
$_TARGETNAME arc cache l2 auto 1
# ARC HS38 core 1
set _TARGETNAME $_CHIPNAME.cpu1
jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
$_TARGETNAME configure -coreid $_coreid
$_TARGETNAME configure -dbgbase $_dbgbase
$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
set _coreid [expr $_coreid + 1]
set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
arc_hs_init_regs
# Enable L2 cache support for core 1.
$_TARGETNAME arc cache l2 auto 1