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Fix warnings exposed by GCC8

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gcc (GCC) 8.1.0 generates new warnings and thus fails the build.

The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and
SMUL instructions decoding.

Reported by Eimers on IRC.

Change-Id: I200c70f75a9e07a1f13a592addc1c5fb37714440
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4526
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Paul Fertser
2018-05-22 12:04:31 +03:00
committed by Matthias Welwarsky
parent dae1ec1278
commit b50fa9a19d
4 changed files with 12 additions and 10 deletions
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2
src/target/arm_adi_v5.c
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@@ -152,6 +152,8 @@ static uint32_t mem_ap_get_tar_increment(struct adiv5_ap *ap)
return 2;
case CSW_32BIT:
return 4;
default:
return 0;
}
case CSW_ADDRINC_PACKED:
return 4;

6
src/target/arm_disassembler.c
View File

@@ -1549,7 +1549,7 @@ static int evaluate_misc_instr(uint32_t opcode,
}
/* SMLAW < y> */
if (((opcode & 0x00600000) == 0x00100000) && (x == 0)) {
if (((opcode & 0x00600000) == 0x00200000) && (x == 0)) {
uint8_t Rd, Rm, Rs, Rn;
instruction->type = ARM_SMLAWy;
Rd = (opcode & 0xf0000) >> 16;
@@ -1571,7 +1571,7 @@ static int evaluate_misc_instr(uint32_t opcode,
}
/* SMUL < x><y> */
if ((opcode & 0x00600000) == 0x00300000) {
if ((opcode & 0x00600000) == 0x00600000) {
uint8_t Rd, Rm, Rs;
instruction->type = ARM_SMULxy;
Rd = (opcode & 0xf0000) >> 16;
@@ -1592,7 +1592,7 @@ static int evaluate_misc_instr(uint32_t opcode,
}
/* SMULW < y> */
if (((opcode & 0x00600000) == 0x00100000) && (x == 1)) {
if (((opcode & 0x00600000) == 0x00200000) && (x == 1)) {
uint8_t Rd, Rm, Rs;
instruction->type = ARM_SMULWy;
Rd = (opcode & 0xf0000) >> 16;