Upstream tons of RISC-V changes.
These are all the changes from https://github.com/riscv/riscv-openocd
(approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
new code is disabled because it requires some other target-independent
changes which I didn't want to include here.
Built like this, OpenOCD passes:
* All single-RV32 tests against spike.
* All single-RV64 tests against spike.
* Enough HiFive1 tests. (I suspect the failures are due to the test
suite rotting.)
* Many dual-RV32 (-rtos hwthread) against spike.
* Many dual-RV64 (-rtos hwthread) against spike.
I suspect this is an overall improvement compared to what's in mainline
right now, and it gets me a lot closer to getting all the riscv-openocd
work upstreamed.
Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/5821
Tested-by: jenkins
Reviewed-by: Jan Matyas <matyas@codasip.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Karl Palsson <karlp@tweak.net.au>
This commit is contained in:
Tim Newsome
@@ -1,3 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef RISCV_H
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#define RISCV_H
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@@ -6,9 +8,11 @@ struct riscv_program;
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#include <stdint.h>
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#include "opcodes.h"
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#include "gdb_regs.h"
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#include "jtag/jtag.h"
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#include "target/register.h"
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/* The register cache is statically allocated. */
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#define RISCV_MAX_HARTS 32
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#define RISCV_MAX_HARTS 1024
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#define RISCV_MAX_REGISTERS 5000
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#define RISCV_MAX_TRIGGERS 32
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#define RISCV_MAX_HWBPS 16
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@@ -16,6 +20,12 @@ struct riscv_program;
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#define DEFAULT_COMMAND_TIMEOUT_SEC 2
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#define DEFAULT_RESET_TIMEOUT_SEC 30
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#define RISCV_SATP_MODE(xlen) ((xlen) == 32 ? SATP32_MODE : SATP64_MODE)
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#define RISCV_SATP_PPN(xlen) ((xlen) == 32 ? SATP32_PPN : SATP64_PPN)
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#define RISCV_PGSHIFT 12
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# define PG_MAX_LEVEL 4
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extern struct target_type riscv011_target;
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extern struct target_type riscv013_target;
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@@ -32,6 +42,7 @@ enum riscv_halt_reason {
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RISCV_HALT_SINGLESTEP,
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RISCV_HALT_TRIGGER,
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RISCV_HALT_UNKNOWN,
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RISCV_HALT_GROUP,
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RISCV_HALT_ERROR
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};
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@@ -46,9 +57,6 @@ typedef struct {
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struct command_context *cmd_ctx;
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void *version_specific;
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/* The number of harts on this system. */
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int hart_count;
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/* The hart that the RTOS thinks is currently being debugged. */
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int rtos_hartid;
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@@ -58,11 +66,6 @@ typedef struct {
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* every function than an actual */
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int current_hartid;
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/* Enough space to store all the registers we might need to save. */
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/* FIXME: This should probably be a bunch of register caches. */
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uint64_t saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS];
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bool valid_saved_registers[RISCV_MAX_HARTS][RISCV_MAX_REGISTERS];
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/* OpenOCD's register cache points into here. This is not per-hart because
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* we just invalidate the entire cache when we change which hart is
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* selected. */
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@@ -75,6 +78,8 @@ typedef struct {
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/* It's possible that each core has a different supported ISA set. */
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int xlen[RISCV_MAX_HARTS];
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riscv_reg_t misa[RISCV_MAX_HARTS];
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/* Cached value of vlenb. 0 if vlenb is not readable for some reason. */
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unsigned vlenb[RISCV_MAX_HARTS];
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/* The number of triggers per hart. */
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unsigned trigger_count[RISCV_MAX_HARTS];
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@@ -100,19 +105,33 @@ typedef struct {
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* delays, causing them to be relearned. Used for testing. */
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int reset_delays_wait;
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/* This target has been prepped and is ready to step/resume. */
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bool prepped;
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/* This target was selected using hasel. */
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bool selected;
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/* Helper functions that target the various RISC-V debug spec
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* implementations. */
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int (*get_register)(struct target *target,
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riscv_reg_t *value, int hid, int rid);
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int (*set_register)(struct target *target, int hartid, int regid,
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uint64_t value);
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int (*get_register_buf)(struct target *target, uint8_t *buf, int regno);
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int (*set_register_buf)(struct target *target, int regno,
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const uint8_t *buf);
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int (*select_current_hart)(struct target *target);
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bool (*is_halted)(struct target *target);
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int (*halt_current_hart)(struct target *target);
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int (*resume_current_hart)(struct target *target);
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/* Resume this target, as well as every other prepped target that can be
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* resumed near-simultaneously. Clear the prepped flag on any target that
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* was resumed. */
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int (*resume_go)(struct target *target);
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int (*step_current_hart)(struct target *target);
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int (*on_halt)(struct target *target);
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int (*on_resume)(struct target *target);
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/* Get this target as ready as possible to resume, without actually
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* resuming. */
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int (*resume_prep)(struct target *target);
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int (*halt_prep)(struct target *target);
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int (*halt_go)(struct target *target);
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int (*on_step)(struct target *target);
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enum riscv_halt_reason (*halt_reason)(struct target *target);
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int (*write_debug_buffer)(struct target *target, unsigned index,
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@@ -134,8 +153,52 @@ typedef struct {
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uint32_t num_words, target_addr_t illegal_address, bool run_sbbusyerror_test);
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int (*test_compliance)(struct target *target);
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int (*read_memory)(struct target *target, target_addr_t address,
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uint32_t size, uint32_t count, uint8_t *buffer, uint32_t increment);
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/* How many harts are attached to the DM that this target is attached to? */
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int (*hart_count)(struct target *target);
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unsigned (*data_bits)(struct target *target);
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/* Storage for vector register types. */
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struct reg_data_type_vector vector_uint8;
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struct reg_data_type_vector vector_uint16;
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struct reg_data_type_vector vector_uint32;
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struct reg_data_type_vector vector_uint64;
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struct reg_data_type_vector vector_uint128;
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struct reg_data_type type_uint8_vector;
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struct reg_data_type type_uint16_vector;
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struct reg_data_type type_uint32_vector;
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struct reg_data_type type_uint64_vector;
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struct reg_data_type type_uint128_vector;
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struct reg_data_type_union_field vector_fields[5];
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struct reg_data_type_union vector_union;
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struct reg_data_type type_vector;
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/* Set when trigger registers are changed by the user. This indicates we eed
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* to beware that we may hit a trigger that we didn't realize had been set. */
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bool manual_hwbp_set;
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} riscv_info_t;
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typedef struct {
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uint8_t tunneled_dr_width;
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struct scan_field tunneled_dr[4];
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} riscv_bscan_tunneled_scan_context_t;
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typedef struct {
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const char *name;
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int level;
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unsigned va_bits;
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unsigned pte_shift;
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unsigned vpn_shift[PG_MAX_LEVEL];
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unsigned vpn_mask[PG_MAX_LEVEL];
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unsigned pte_ppn_shift[PG_MAX_LEVEL];
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unsigned pte_ppn_mask[PG_MAX_LEVEL];
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unsigned pa_ppn_shift[PG_MAX_LEVEL];
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unsigned pa_ppn_mask[PG_MAX_LEVEL];
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} virt2phys_info_t;
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/* Wall-clock timeout for a command/access. Settable via RISC-V Target commands.*/
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extern int riscv_command_timeout_sec;
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@@ -144,6 +207,11 @@ extern int riscv_reset_timeout_sec;
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extern bool riscv_prefer_sba;
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extern bool riscv_enable_virtual;
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extern bool riscv_ebreakm;
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extern bool riscv_ebreaks;
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extern bool riscv_ebreaku;
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/* Everything needs the RISC-V specific info structure, so here's a nice macro
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* that provides that. */
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static inline riscv_info_t *riscv_info(const struct target *target) __attribute__((unused));
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@@ -158,17 +226,28 @@ extern struct scan_field select_dbus;
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extern uint8_t ir_idcode[4];
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extern struct scan_field select_idcode;
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extern struct scan_field select_user4;
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extern struct scan_field *bscan_tunneled_select_dmi;
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extern uint32_t bscan_tunneled_select_dmi_num_fields;
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typedef enum { BSCAN_TUNNEL_NESTED_TAP, BSCAN_TUNNEL_DATA_REGISTER } bscan_tunnel_type_t;
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extern int bscan_tunnel_ir_width;
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extern bscan_tunnel_type_t bscan_tunnel_type;
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uint32_t dtmcontrol_scan_via_bscan(struct target *target, uint32_t out);
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void select_dmi_via_bscan(struct target *target);
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/*** OpenOCD Interface */
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int riscv_openocd_poll(struct target *target);
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int riscv_openocd_halt(struct target *target);
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int riscv_halt(struct target *target);
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int riscv_openocd_resume(
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int riscv_resume(
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struct target *target,
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int current,
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target_addr_t address,
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int handle_breakpoints,
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int debug_execution
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int debug_execution,
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bool single_hart
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);
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int riscv_openocd_step(
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@@ -186,14 +265,6 @@ int riscv_openocd_deassert_reset(struct target *target);
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/* Initializes the shared RISC-V structure. */
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void riscv_info_init(struct target *target, riscv_info_t *r);
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/* Run control, possibly for multiple harts. The _all_harts versions resume
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* all the enabled harts, which when running in RTOS mode is all the harts on
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* the system. */
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int riscv_halt_all_harts(struct target *target);
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int riscv_halt_one_hart(struct target *target, int hartid);
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int riscv_resume_all_harts(struct target *target);
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int riscv_resume_one_hart(struct target *target, int hartid);
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/* Steps the hart that's currently selected in the RTOS, or if there is no RTOS
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* then the only hart. */
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int riscv_step_rtos_hart(struct target *target);
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@@ -201,7 +272,7 @@ int riscv_step_rtos_hart(struct target *target);
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bool riscv_supports_extension(struct target *target, int hartid, char letter);
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/* Returns XLEN for the given (or current) hart. */
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int riscv_xlen(const struct target *target);
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unsigned riscv_xlen(const struct target *target);
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int riscv_xlen_of_hart(const struct target *target, int hartid);
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bool riscv_rtos_enabled(const struct target *target);
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@@ -226,12 +297,14 @@ int riscv_count_harts(struct target *target);
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/* Returns TRUE if the target has the given register on the given hart. */
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bool riscv_has_register(struct target *target, int hartid, int regid);
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/* Returns the value of the given register on the given hart. 32-bit registers
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* are zero extended to 64 bits. */
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/** Set register, updating the cache. */
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int riscv_set_register(struct target *target, enum gdb_regno i, riscv_reg_t v);
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/** Set register, updating the cache. */
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int riscv_set_register_on_hart(struct target *target, int hid, enum gdb_regno rid, uint64_t v);
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/** Get register, from the cache if it's in there. */
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int riscv_get_register(struct target *target, riscv_reg_t *value,
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enum gdb_regno r);
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/** Get register, from the cache if it's in there. */
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int riscv_get_register_on_hart(struct target *target, riscv_reg_t *value,
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int hartid, enum gdb_regno regid);
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@@ -272,6 +345,15 @@ int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_wp_addre
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int riscv_init_registers(struct target *target);
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void riscv_semihosting_init(struct target *target);
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int riscv_semihosting(struct target *target, int *retval);
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typedef enum {
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SEMI_NONE, /* Not halted for a semihosting call. */
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SEMI_HANDLED, /* Call handled, and target was resumed. */
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SEMI_WAITING, /* Call handled, target is halted waiting until we can resume. */
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SEMI_ERROR /* Something went wrong. */
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} semihosting_result_t;
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semihosting_result_t riscv_semihosting(struct target *target, int *retval);
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void riscv_add_bscan_tunneled_scan(struct target *target, struct scan_field *field,
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riscv_bscan_tunneled_scan_context_t *ctxt);
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#endif
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