aarch64: armv8 cache functions update
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky
@@ -37,6 +37,8 @@
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#include "target.h"
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#include "target_type.h"
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#define __unused __attribute__((unused))
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static const char * const armv8_state_strings[] = {
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"AArch32", "Thumb", "Jazelle", "ThumbEE", "AArch64",
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};
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@@ -208,6 +210,38 @@ static int armv8_write_core_reg(struct target *target, struct reg *r,
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return ERROR_OK;
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}
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#endif
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/* retrieve core id cluster id */
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int armv8_read_mpidr(struct armv8_common *armv8)
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{
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int retval = ERROR_FAIL;
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t mpidr;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
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if (retval != ERROR_OK)
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goto done;
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if (mpidr & 1<<31) {
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armv8->multi_processor_system = (mpidr >> 30) & 1;
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armv8->cluster_id = (mpidr >> 8) & 0xf;
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armv8->cpu_id = mpidr & 0x3;
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LOG_INFO("%s cluster %x core %x %s", target_name(armv8->arm.target),
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armv8->cluster_id,
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armv8->cpu_id,
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armv8->multi_processor_system == 0 ? "multi core" : "mono core");
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} else
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LOG_ERROR("mpdir not in multiprocessor format");
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done:
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dpm->finish(dpm);
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return retval;
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}
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/**
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* Configures host-side ARM records to reflect the specified CPSR.
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* Later, code can use arm_reg_current() to map register numbers
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@@ -368,7 +402,7 @@ static uint8_t armv8_pa_size(uint32_t ps)
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return ret;
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}
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static int armv8_read_ttbcr32(struct target *target)
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static __unused int armv8_read_ttbcr32(struct target *target)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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@@ -528,103 +562,10 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
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return ERROR_OK;
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}
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static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache)
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{
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if (armv8_cache->ctype == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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command_print(cmd_ctx,
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"D-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
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armv8_cache->d_u_size.linelen,
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armv8_cache->d_u_size.associativity,
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armv8_cache->d_u_size.nsets,
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armv8_cache->d_u_size.cachesize);
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command_print(cmd_ctx,
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"I-Cache: linelen %" PRIi32 ", associativity %" PRIi32 ", nsets %" PRIi32 ", cachesize %" PRId32 " KBytes",
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armv8_cache->i_size.linelen,
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armv8_cache->i_size.associativity,
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armv8_cache->i_size.nsets,
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armv8_cache->i_size.cachesize);
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return ERROR_OK;
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}
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static int _armv8_flush_all_data(struct target *target)
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{
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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struct armv8_cachesize *d_u_size =
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&(armv8->armv8_mmu.armv8_cache.d_u_size);
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int32_t c_way, c_index = d_u_size->index;
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int retval;
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/* check that cache data is on at target halt */
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if (!armv8->armv8_mmu.armv8_cache.d_u_cache_enabled) {
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LOG_INFO("flushed not performed :cache not on at target halt");
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return ERROR_OK;
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}
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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do {
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c_way = d_u_size->way;
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do {
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uint32_t value = (c_index << d_u_size->index_shift)
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| (c_way << d_u_size->way_shift);
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/* DCCISW */
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/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
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value);
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if (retval != ERROR_OK)
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goto done;
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c_way -= 1;
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} while (c_way >= 0);
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c_index -= 1;
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} while (c_index >= 0);
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return retval;
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done:
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LOG_ERROR("flushed failed");
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dpm->finish(dpm);
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return retval;
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}
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static int armv8_flush_all_data(struct target *target)
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{
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int retval = ERROR_FAIL;
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/* check that armv8_cache is correctly identify */
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struct armv8_common *armv8 = target_to_armv8(target);
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if (armv8->armv8_mmu.armv8_cache.ctype == -1) {
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LOG_ERROR("trying to flush un-identified cache");
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return retval;
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}
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if (target->smp) {
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/* look if all the other target have been flushed in order to flush level
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* 2 */
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struct target_list *head;
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struct target *curr;
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head = target->head;
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if (curr->state == TARGET_HALTED) {
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LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
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retval = _armv8_flush_all_data(curr);
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}
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head = head->next;
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}
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} else
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retval = _armv8_flush_all_data(target);
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return retval;
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}
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int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache)
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{
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if (armv8_cache->ctype == -1) {
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if (armv8_cache->info == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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@@ -634,174 +575,6 @@ int armv8_handle_cache_info_command(struct command_context *cmd_ctx,
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return ERROR_OK;
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}
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/* retrieve core id cluster id */
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static int armv8_read_mpidr(struct target *target)
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{
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int retval = ERROR_FAIL;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t mpidr;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* MRC p15,0,<Rd>,c0,c0,5; read Multiprocessor ID register*/
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_MPIDR), &mpidr);
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if (retval != ERROR_OK)
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goto done;
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if (mpidr & 1<<31) {
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armv8->multi_processor_system = (mpidr >> 30) & 1;
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armv8->cluster_id = (mpidr >> 8) & 0xf;
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armv8->cpu_id = mpidr & 0x3;
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LOG_INFO("%s cluster %x core %x %s", target_name(target),
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armv8->cluster_id,
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armv8->cpu_id,
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armv8->multi_processor_system == 0 ? "multi core" : "mono core");
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} else
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LOG_ERROR("mpdir not in multiprocessor format");
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done:
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dpm->finish(dpm);
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return retval;
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}
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int armv8_identify_cache(struct target *target)
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{
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/* read cache descriptor */
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int retval = ERROR_FAIL;
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struct armv8_common *armv8 = target_to_armv8(target);
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t cache_selected, clidr;
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uint32_t cache_i_reg, cache_d_reg;
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struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
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int is_aarch64 = armv8->arm.core_state == ARM_STATE_AARCH64;
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retval = is_aarch64 ? armv8_read_ttbcr(target) : armv8_read_ttbcr32(target);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* retrieve CLIDR */
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CLIDR), &clidr);
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if (retval != ERROR_OK)
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goto done;
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clidr = (clidr & 0x7000000) >> 23;
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LOG_INFO("number of cache level %" PRIx32, (uint32_t)(clidr / 2));
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if ((clidr / 2) > 1) {
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/* FIXME not supported present in cortex A8 and later */
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/* in cortex A7, A15 */
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LOG_ERROR("cache l2 present :not supported");
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}
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/* retrieve selected cache*/
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CSSELR), &cache_selected);
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if (retval != ERROR_OK)
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goto done;
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/* select instruction cache
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* [0] : 1 instruction cache selection , 0 data cache selection */
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retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 1);
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if (retval != ERROR_OK)
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goto done;
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/* read CCSIDR
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* MRC P15,1,<RT>,C0, C0,0 ;on cortex A9 read CCSIDR
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* [2:0] line size 001 eight word per line
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* [27:13] NumSet 0x7f 16KB, 0xff 32Kbytes, 0x1ff 64Kbytes */
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_i_reg);
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if (retval != ERROR_OK)
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goto done;
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/* select data cache*/
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retval = dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), 0);
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm, armv8_opcode(armv8, READ_REG_CCSIDR), &cache_d_reg);
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if (retval != ERROR_OK)
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goto done;
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/* restore selected cache */
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dpm->instr_write_data_r0(dpm, armv8_opcode(armv8, WRITE_REG_CSSELR), cache_selected);
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if (retval != ERROR_OK)
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goto done;
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dpm->finish(dpm);
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/* put fake type */
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cache->d_u_size.linelen = 16 << (cache_d_reg & 0x7);
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cache->d_u_size.cachesize = (((cache_d_reg >> 13) & 0x7fff)+1)/8;
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cache->d_u_size.nsets = (cache_d_reg >> 13) & 0x7fff;
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cache->d_u_size.associativity = ((cache_d_reg >> 3) & 0x3ff) + 1;
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/* compute info for set way operation on cache */
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cache->d_u_size.index_shift = (cache_d_reg & 0x7) + 4;
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cache->d_u_size.index = (cache_d_reg >> 13) & 0x7fff;
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cache->d_u_size.way = ((cache_d_reg >> 3) & 0x3ff);
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cache->d_u_size.way_shift = cache->d_u_size.way + 1;
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{
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int i = 0;
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while (((cache->d_u_size.way_shift >> i) & 1) != 1)
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i++;
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cache->d_u_size.way_shift = 32-i;
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}
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#if 0
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LOG_INFO("data cache index %d << %d, way %d << %d",
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cache->d_u_size.index, cache->d_u_size.index_shift,
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cache->d_u_size.way,
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cache->d_u_size.way_shift);
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LOG_INFO("data cache %d bytes %d KBytes asso %d ways",
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cache->d_u_size.linelen,
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cache->d_u_size.cachesize,
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cache->d_u_size.associativity);
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#endif
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cache->i_size.linelen = 16 << (cache_i_reg & 0x7);
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cache->i_size.associativity = ((cache_i_reg >> 3) & 0x3ff) + 1;
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cache->i_size.nsets = (cache_i_reg >> 13) & 0x7fff;
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cache->i_size.cachesize = (((cache_i_reg >> 13) & 0x7fff)+1)/8;
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/* compute info for set way operation on cache */
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cache->i_size.index_shift = (cache_i_reg & 0x7) + 4;
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cache->i_size.index = (cache_i_reg >> 13) & 0x7fff;
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cache->i_size.way = ((cache_i_reg >> 3) & 0x3ff);
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cache->i_size.way_shift = cache->i_size.way + 1;
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{
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int i = 0;
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while (((cache->i_size.way_shift >> i) & 1) != 1)
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i++;
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cache->i_size.way_shift = 32-i;
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}
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#if 0
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LOG_INFO("instruction cache index %d << %d, way %d << %d",
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cache->i_size.index, cache->i_size.index_shift,
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cache->i_size.way, cache->i_size.way_shift);
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LOG_INFO("instruction cache %d bytes %d KBytes asso %d ways",
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cache->i_size.linelen,
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cache->i_size.cachesize,
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cache->i_size.associativity);
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#endif
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/* if no l2 cache initialize l1 data cache flush function function */
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if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
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armv8->armv8_mmu.armv8_cache.display_cache_info =
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armv8_handle_inner_cache_info_command;
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armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
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armv8_flush_all_data;
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}
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armv8->armv8_mmu.armv8_cache.ctype = 0;
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done:
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dpm->finish(dpm);
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armv8_read_mpidr(target);
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return retval;
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}
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int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
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{
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struct arm *arm = &armv8->arm;
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@@ -818,7 +591,7 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
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#endif
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armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
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armv8->armv8_mmu.armv8_cache.ctype = -1;
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armv8->armv8_mmu.armv8_cache.info = -1;
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armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
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armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
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return ERROR_OK;
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