aarch64: armv8 cache functions update
Update cache identification to match functionality present in armv7a_cache.c Change-Id: I2dc4bee80f5a22b8728334d40331c183d1406f27 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky
@@ -24,6 +24,11 @@
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#include "armv8_dpm.h"
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#include "armv8_opcodes.h"
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/* CLIDR cache types */
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#define CACHE_LEVEL_HAS_UNIFIED_CACHE 0x4
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#define CACHE_LEVEL_HAS_D_CACHE 0x2
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#define CACHE_LEVEL_HAS_I_CACHE 0x1
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static int armv8_d_cache_sanity_check(struct armv8_common *armv8)
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{
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struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
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@@ -44,11 +49,72 @@ static int armv8_i_cache_sanity_check(struct armv8_common *armv8)
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return ERROR_TARGET_INVALID;
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}
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static int armv8_cache_d_inner_flush_level(struct arm_dpm *dpm, struct armv8_cachesize *size, int cl)
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{
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int retval = ERROR_OK;
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int32_t c_way, c_index = size->index;
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LOG_DEBUG("cl %" PRId32, cl);
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do {
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c_way = size->way;
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do {
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uint32_t value = (c_index << size->index_shift)
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| (c_way << size->way_shift) | (cl << 1);
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/*
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* DC CISW - Clean and invalidate data cache
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* line by Set/Way.
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*/
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_SYS(SYSTEM_DCCISW, 0), value);
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if (retval != ERROR_OK)
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goto done;
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c_way -= 1;
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} while (c_way >= 0);
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c_index -= 1;
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} while (c_index >= 0);
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done:
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return retval;
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}
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static int armv8_cache_d_inner_clean_inval_all(struct armv8_common *armv8)
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{
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struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
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struct arm_dpm *dpm = armv8->arm.dpm;
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int cl;
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int retval;
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retval = armv8_d_cache_sanity_check(armv8);
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if (retval != ERROR_OK)
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return retval;
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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for (cl = 0; cl < cache->loc; cl++) {
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/* skip i-only caches */
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if (cache->arch[cl].ctype < CACHE_LEVEL_HAS_D_CACHE)
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continue;
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armv8_cache_d_inner_flush_level(dpm, &cache->arch[cl].d_u_size, cl);
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}
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retval = dpm->finish(dpm);
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return retval;
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done:
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LOG_ERROR("clean invalidate failed");
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dpm->finish(dpm);
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return retval;
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}
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int armv8_cache_d_inner_flush_virt(struct armv8_common *armv8, target_addr_t va, size_t size)
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{
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struct arm_dpm *dpm = armv8->arm.dpm;
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struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
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uint64_t linelen = armv8_cache->d_u_size.linelen;
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uint64_t linelen = armv8_cache->dminline;
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target_addr_t va_line, va_end;
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int retval;
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@@ -87,7 +153,7 @@ int armv8_cache_i_inner_inval_virt(struct armv8_common *armv8, target_addr_t va,
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{
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struct arm_dpm *dpm = armv8->arm.dpm;
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struct armv8_cache_common *armv8_cache = &armv8->armv8_mmu.armv8_cache;
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uint64_t linelen = armv8_cache->i_size.linelen;
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uint64_t linelen = armv8_cache->iminline;
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target_addr_t va_line, va_end;
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int retval;
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@@ -120,3 +186,232 @@ done:
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return retval;
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}
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static int armv8_handle_inner_cache_info_command(struct command_context *cmd_ctx,
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struct armv8_cache_common *armv8_cache)
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{
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int cl;
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if (armv8_cache->info == -1) {
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command_print(cmd_ctx, "cache not yet identified");
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return ERROR_OK;
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}
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for (cl = 0; cl < armv8_cache->loc; cl++) {
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struct armv8_arch_cache *arch = &(armv8_cache->arch[cl]);
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if (arch->ctype & 1) {
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command_print(cmd_ctx,
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"L%d I-Cache: linelen %" PRIi32
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", associativity %" PRIi32
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", nsets %" PRIi32
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", cachesize %" PRId32 " KBytes",
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cl+1,
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arch->i_size.linelen,
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arch->i_size.associativity,
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arch->i_size.nsets,
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arch->i_size.cachesize);
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}
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if (arch->ctype >= 2) {
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command_print(cmd_ctx,
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"L%d D-Cache: linelen %" PRIi32
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", associativity %" PRIi32
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", nsets %" PRIi32
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", cachesize %" PRId32 " KBytes",
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cl+1,
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arch->d_u_size.linelen,
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arch->d_u_size.associativity,
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arch->d_u_size.nsets,
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arch->d_u_size.cachesize);
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}
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}
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return ERROR_OK;
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}
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static int _armv8_flush_all_data(struct target *target)
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{
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return armv8_cache_d_inner_clean_inval_all(target_to_armv8(target));
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}
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static int armv8_flush_all_data(struct target *target)
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{
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int retval = ERROR_FAIL;
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/* check that armv8_cache is correctly identify */
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struct armv8_common *armv8 = target_to_armv8(target);
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if (armv8->armv8_mmu.armv8_cache.info == -1) {
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LOG_ERROR("trying to flush un-identified cache");
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return retval;
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}
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if (target->smp) {
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/* look if all the other target have been flushed in order to flush level
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* 2 */
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struct target_list *head;
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struct target *curr;
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head = target->head;
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while (head != (struct target_list *)NULL) {
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curr = head->target;
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if (curr->state == TARGET_HALTED) {
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LOG_INFO("Wait flushing data l1 on core %" PRId32, curr->coreid);
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retval = _armv8_flush_all_data(curr);
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}
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head = head->next;
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}
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} else
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retval = _armv8_flush_all_data(target);
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return retval;
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}
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static int get_cache_info(struct arm_dpm *dpm, int cl, int ct, uint32_t *cache_reg)
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{
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int retval = ERROR_OK;
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/* select cache level */
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_MSR_GP(SYSTEM_CSSELR, 0),
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(cl << 1) | (ct == 1 ? 1 : 0));
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if (retval != ERROR_OK)
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goto done;
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retval = dpm->instr_read_data_r0(dpm,
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ARMV8_MRS(SYSTEM_CCSIDR, 0),
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cache_reg);
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done:
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return retval;
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}
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static struct armv8_cachesize decode_cache_reg(uint32_t cache_reg)
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{
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struct armv8_cachesize size;
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int i = 0;
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size.linelen = 16 << (cache_reg & 0x7);
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size.associativity = ((cache_reg >> 3) & 0x3ff) + 1;
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size.nsets = ((cache_reg >> 13) & 0x7fff) + 1;
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size.cachesize = size.linelen * size.associativity * size.nsets / 1024;
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/* compute info for set way operation on cache */
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size.index_shift = (cache_reg & 0x7) + 4;
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size.index = (cache_reg >> 13) & 0x7fff;
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size.way = ((cache_reg >> 3) & 0x3ff);
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while (((size.way << i) & 0x80000000) == 0)
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i++;
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size.way_shift = i;
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return size;
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}
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int armv8_identify_cache(struct armv8_common *armv8)
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{
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/* read cache descriptor */
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int retval = ERROR_FAIL;
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struct arm_dpm *dpm = armv8->arm.dpm;
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uint32_t csselr, clidr, ctr;
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uint32_t cache_reg;
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int cl, ctype;
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struct armv8_cache_common *cache = &(armv8->armv8_mmu.armv8_cache);
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retval = dpm->prepare(dpm);
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if (retval != ERROR_OK)
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goto done;
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/* retrieve CTR */
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retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CTR, 0), &ctr);
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if (retval != ERROR_OK)
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goto done;
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cache->iminline = 4UL << (ctr & 0xf);
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cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
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LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
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ctr, cache->iminline, cache->dminline);
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/* retrieve CLIDR */
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retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CLIDR, 0), &clidr);
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if (retval != ERROR_OK)
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goto done;
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cache->loc = (clidr & 0x7000000) >> 24;
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LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
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/* retrieve selected cache for later restore
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* MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
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retval = dpm->instr_read_data_r0(dpm, ARMV8_MRS(SYSTEM_CSSELR, 0), &csselr);
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if (retval != ERROR_OK)
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goto done;
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/* retrieve all available inner caches */
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for (cl = 0; cl < cache->loc; clidr >>= 3, cl++) {
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/* isolate cache type at current level */
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ctype = clidr & 7;
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/* skip reserved values */
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if (ctype > CACHE_LEVEL_HAS_UNIFIED_CACHE)
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continue;
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/* separate d or unified d/i cache at this level ? */
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if (ctype & (CACHE_LEVEL_HAS_UNIFIED_CACHE | CACHE_LEVEL_HAS_D_CACHE)) {
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/* retrieve d-cache info */
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retval = get_cache_info(dpm, cl, 0, &cache_reg);
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if (retval != ERROR_OK)
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goto done;
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cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
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LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
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cache->arch[cl].d_u_size.index,
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cache->arch[cl].d_u_size.index_shift,
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cache->arch[cl].d_u_size.way,
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cache->arch[cl].d_u_size.way_shift);
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LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
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cache->arch[cl].d_u_size.linelen,
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cache->arch[cl].d_u_size.cachesize,
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cache->arch[cl].d_u_size.associativity);
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}
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/* separate i-cache at this level ? */
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if (ctype & CACHE_LEVEL_HAS_I_CACHE) {
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/* retrieve i-cache info */
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retval = get_cache_info(dpm, cl, 1, &cache_reg);
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if (retval != ERROR_OK)
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goto done;
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cache->arch[cl].i_size = decode_cache_reg(cache_reg);
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LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
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cache->arch[cl].i_size.index,
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cache->arch[cl].i_size.index_shift,
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cache->arch[cl].i_size.way,
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cache->arch[cl].i_size.way_shift);
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LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
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cache->arch[cl].i_size.linelen,
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cache->arch[cl].i_size.cachesize,
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cache->arch[cl].i_size.associativity);
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}
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cache->arch[cl].ctype = ctype;
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}
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/* restore selected cache */
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dpm->instr_write_data_r0(dpm, ARMV8_MSR_GP(SYSTEM_CSSELR, 0), csselr);
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if (retval != ERROR_OK)
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goto done;
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armv8->armv8_mmu.armv8_cache.info = 1;
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/* if no l2 cache initialize l1 data cache flush function function */
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if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache == NULL) {
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armv8->armv8_mmu.armv8_cache.display_cache_info =
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armv8_handle_inner_cache_info_command;
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armv8->armv8_mmu.armv8_cache.flush_all_data_cache =
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armv8_flush_all_data;
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}
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done:
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dpm->finish(dpm);
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return retval;
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}
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