MIPS: add mips algorithm support
- add mips support for target algorithms. - added handlers for target_checksum_memory and target_blank_check_memory. - clean up long lines Signed-off-by: Spencer Oliver <ntfreak@users.sourceforge.net>
This commit is contained in:
Spencer Oliver
@@ -27,6 +27,8 @@
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#endif
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#include "mips32.h"
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#include "breakpoints.h"
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#include "algorithm.h"
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#include "register.h"
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char* mips32_core_reg_list[] =
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@@ -319,9 +321,168 @@ int mips32_init_arch_info(struct target *target, struct mips32_common *mips32, s
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return ERROR_OK;
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}
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int mips32_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info)
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/* run to exit point. return error if exit point was not reached. */
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static int mips32_run_and_wait(struct target *target, uint32_t entry_point,
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int timeout_ms, uint32_t exit_point, struct mips32_common *mips32)
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{
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/*TODO*/
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uint32_t pc;
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int retval;
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/* This code relies on the target specific resume() and poll()->debug_entry()
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* sequence to write register values to the processor and the read them back */
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if ((retval = target_resume(target, 0, entry_point, 0, 1)) != ERROR_OK)
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{
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return retval;
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}
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retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
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/* If the target fails to halt due to the breakpoint, force a halt */
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if (retval != ERROR_OK || target->state != TARGET_HALTED)
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{
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if ((retval = target_halt(target)) != ERROR_OK)
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return retval;
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if ((retval = target_wait_state(target, TARGET_HALTED, 500)) != ERROR_OK)
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{
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return retval;
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}
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return ERROR_TARGET_TIMEOUT;
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}
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pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
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if (pc != exit_point)
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{
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LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
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return ERROR_TARGET_TIMEOUT;
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}
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return ERROR_OK;
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}
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int mips32_run_algorithm(struct target *target, int num_mem_params,
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struct mem_param *mem_params, int num_reg_params,
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struct reg_param *reg_params, uint32_t entry_point,
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uint32_t exit_point, int timeout_ms, void *arch_info)
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{
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struct mips32_common *mips32 = target_to_mips32(target);
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struct mips32_algorithm *mips32_algorithm_info = arch_info;
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enum mips32_isa_mode isa_mode = mips32->isa_mode;
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uint32_t context[MIPS32NUMCOREREGS];
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int i;
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int retval = ERROR_OK;
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LOG_DEBUG("Running algorithm");
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/* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
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* at the exit point */
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if (mips32->common_magic != MIPS32_COMMON_MAGIC)
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{
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LOG_ERROR("current target isn't a MIPS32 target");
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return ERROR_TARGET_INVALID;
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}
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if (target->state != TARGET_HALTED)
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{
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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/* refresh core register cache */
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for (unsigned i = 0; i < MIPS32NUMCOREREGS; i++)
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{
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if (!mips32->core_cache->reg_list[i].valid)
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mips32->read_core_reg(target, i);
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context[i] = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
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}
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for (i = 0; i < num_mem_params; i++)
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{
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if ((retval = target_write_buffer(target, mem_params[i].address,
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mem_params[i].size, mem_params[i].value)) != ERROR_OK)
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{
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return retval;
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}
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}
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for (int i = 0; i < num_reg_params; i++)
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{
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struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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return ERROR_INVALID_ARGUMENTS;
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}
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if (reg->size != reg_params[i].size)
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{
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
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reg_params[i].reg_name);
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return ERROR_INVALID_ARGUMENTS;
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}
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mips32_set_core_reg(reg, reg_params[i].value);
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}
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mips32->isa_mode = mips32_algorithm_info->isa_mode;
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retval = mips32_run_and_wait(target, entry_point, timeout_ms, exit_point, mips32);
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if (retval != ERROR_OK)
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return retval;
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for (i = 0; i < num_mem_params; i++)
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{
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if (mem_params[i].direction != PARAM_OUT)
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{
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if ((retval = target_read_buffer(target, mem_params[i].address, mem_params[i].size,
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mem_params[i].value)) != ERROR_OK)
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{
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return retval;
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}
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}
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}
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for (i = 0; i < num_reg_params; i++)
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{
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if (reg_params[i].direction != PARAM_OUT)
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{
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struct reg *reg = register_get_by_name(mips32->core_cache, reg_params[i].reg_name, 0);
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if (!reg)
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{
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LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
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return ERROR_INVALID_ARGUMENTS;
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}
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if (reg->size != reg_params[i].size)
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{
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LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
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reg_params[i].reg_name);
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return ERROR_INVALID_ARGUMENTS;
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}
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buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
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}
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}
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/* restore everything we saved before */
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for (i = 0; i < MIPS32NUMCOREREGS; i++)
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{
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uint32_t regvalue;
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regvalue = buf_get_u32(mips32->core_cache->reg_list[i].value, 0, 32);
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if (regvalue != context[i])
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{
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LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
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mips32->core_cache->reg_list[i].name, context[i]);
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buf_set_u32(mips32->core_cache->reg_list[i].value,
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0, 32, context[i]);
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mips32->core_cache->reg_list[i].valid = 1;
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mips32->core_cache->reg_list[i].dirty = 1;
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}
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}
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mips32->isa_mode = isa_mode;
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return ERROR_OK;
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}
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@@ -397,7 +558,8 @@ int mips32_configure_break_unit(struct target *target)
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return retval;
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}
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LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
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LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints,
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mips32->num_data_bpoints);
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mips32->bp_scanned = 1;
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@@ -441,3 +603,150 @@ int mips32_enable_interrupts(struct target *target, int enable)
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return ERROR_OK;
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}
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int mips32_checksum_memory(struct target *target, uint32_t address,
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uint32_t count, uint32_t* checksum)
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{
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struct working_area *crc_algorithm;
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struct reg_param reg_params[2];
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struct mips32_algorithm mips32_info;
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int retval;
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uint32_t i;
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static const uint32_t mips_crc_code[] =
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{
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0x248C0000, /* addiu $t4, $a0, 0 */
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0x24AA0000, /* addiu $t2, $a1, 0 */
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0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */
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0x10000010, /* beq $zero, $zero, ncomp */
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0x240B0000, /* addiu $t3, $zero, 0 */
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/* nbyte: */
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0x81850000, /* lb $a1, ($t4) */
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0x218C0001, /* addi $t4, $t4, 1 */
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0x00052E00, /* sll $a1, $a1, 24 */
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0x3C0204C1, /* lui $v0, 0x04c1 */
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0x00852026, /* xor $a0, $a0, $a1 */
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0x34471DB7, /* ori $a3, $v0, 0x1db7 */
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0x00003021, /* addu $a2, $zero, $zero */
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/* loop: */
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0x00044040, /* sll $t0, $a0, 1 */
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0x24C60001, /* addiu $a2, $a2, 1 */
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0x28840000, /* slti $a0, $a0, 0 */
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0x01074826, /* xor $t1, $t0, $a3 */
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0x0124400B, /* movn $t0, $t1, $a0 */
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0x28C30008, /* slti $v1, $a2, 8 */
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0x1460FFF9, /* bne $v1, $zero, loop */
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0x01002021, /* addu $a0, $t0, $zero */
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/* ncomp: */
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0x154BFFF0, /* bne $t2, $t3, nbyte */
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0x256B0001, /* addiu $t3, $t3, 1 */
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0x7000003F, /* sdbbp */
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};
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/* make sure we have a working area */
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if (target_alloc_working_area(target, sizeof(mips_crc_code), &crc_algorithm) != ERROR_OK)
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{
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* convert flash writing code into a buffer in target endianness */
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for (i = 0; i < ARRAY_SIZE(mips_crc_code); i++)
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target_write_u32(target, crc_algorithm->address + i*sizeof(uint32_t), mips_crc_code[i]);
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mips32_info.common_magic = MIPS32_COMMON_MAGIC;
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mips32_info.isa_mode = MIPS32_ISA_MIPS32;
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init_reg_param(®_params[0], "a0", 32, PARAM_IN_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, address);
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init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
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buf_set_u32(reg_params[1].value, 0, 32, count);
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if ((retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
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crc_algorithm->address, crc_algorithm->address + (sizeof(mips_crc_code)-4), 10000,
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&mips32_info)) != ERROR_OK)
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{
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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target_free_working_area(target, crc_algorithm);
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return 0;
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}
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*checksum = buf_get_u32(reg_params[0].value, 0, 32);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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target_free_working_area(target, crc_algorithm);
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return ERROR_OK;
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}
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/** Checks whether a memory region is zeroed. */
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int mips32_blank_check_memory(struct target *target,
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uint32_t address, uint32_t count, uint32_t* blank)
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{
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struct working_area *erase_check_algorithm;
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struct reg_param reg_params[3];
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struct mips32_algorithm mips32_info;
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int retval;
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uint32_t i;
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static const uint32_t erase_check_code[] =
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{
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/* nbyte: */
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0x80880000, /* lb $t0, ($a0) */
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0x00C83024, /* and $a2, $a2, $t0 */
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0x24A5FFFF, /* addiu $a1, $a1, -1 */
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0x14A0FFFC, /* bne $a1, $zero, nbyte */
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0x24840001, /* addiu $a0, $a0, 1 */
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0x7000003F /* sdbbp */
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};
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/* make sure we have a working area */
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if (target_alloc_working_area(target, sizeof(erase_check_code), &erase_check_algorithm) != ERROR_OK)
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{
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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/* convert flash writing code into a buffer in target endianness */
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for (i = 0; i < ARRAY_SIZE(erase_check_code); i++)
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{
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target_write_u32(target, erase_check_algorithm->address + i*sizeof(uint32_t),
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erase_check_code[i]);
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}
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mips32_info.common_magic = MIPS32_COMMON_MAGIC;
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mips32_info.isa_mode = MIPS32_ISA_MIPS32;
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init_reg_param(®_params[0], "a0", 32, PARAM_OUT);
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buf_set_u32(reg_params[0].value, 0, 32, address);
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init_reg_param(®_params[1], "a1", 32, PARAM_OUT);
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buf_set_u32(reg_params[1].value, 0, 32, count);
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init_reg_param(®_params[2], "a2", 32, PARAM_IN_OUT);
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buf_set_u32(reg_params[2].value, 0, 32, 0xff);
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if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
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erase_check_algorithm->address,
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erase_check_algorithm->address + (sizeof(erase_check_code)-2),
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10000, &mips32_info)) != ERROR_OK)
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{
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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target_free_working_area(target, erase_check_algorithm);
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return 0;
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}
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*blank = buf_get_u32(reg_params[2].value, 0, 32);
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destroy_reg_param(®_params[0]);
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[2]);
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target_free_working_area(target, erase_check_algorithm);
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return ERROR_OK;
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}
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