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target/espressif: add semihosting support

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ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
2022-06-30 13:14:27 +03:00
committed by Antonio Borneo
parent 7dc4be3157
commit bea4d65903
16 changed files with 510 additions and 15 deletions
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14
src/target/espressif/esp32.c
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@@ -13,6 +13,7 @@
#include <target/target.h>
#include <target/target_type.h>
#include <target/smp.h>
#include <target/semihosting_common.h>
#include "assert.h"
#include "esp_xtensa_smp.h"
@@ -329,6 +330,10 @@ static const struct esp_xtensa_smp_chip_ops esp32_chip_ops = {
.on_halt = esp32_on_halt
};
static const struct esp_semihost_ops esp32_semihost_ops = {
.prepare = esp32_disable_wdts
};
static int esp32_target_create(struct target *target, Jim_Interp *interp)
{
struct xtensa_debug_module_config esp32_dm_cfg = {
@@ -346,7 +351,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
}
int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
&esp32_dm_cfg, &esp32_chip_ops);
&esp32_dm_cfg, &esp32_chip_ops, &esp32_semihost_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@@ -445,6 +450,13 @@ static const struct command_registration esp32_command_handlers[] = {
.usage = "",
.chain = esp32_any_command_handlers,
},
{
.name = "arm",
.mode = COMMAND_ANY,
.help = "ARM Command Group",
.usage = "",
.chain = semihosting_common_handlers
},
COMMAND_REGISTRATION_DONE
};