target/espressif: add semihosting support

ARM semihosting + some custom syscalls implemented for
Espressif chips (ESP32, ESP32-S2, ESP32-S3)

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: Ic8174cf1cd344fa16d619b7b8405c9650e869443
Reviewed-on: https://review.openocd.org/c/openocd/+/7074
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

tcl/target/esp32s2.cfg

@@ -7,6 +7,8 @@ set CPU_MAX_ADDRESS 0xFFFFFFFF
 source [find bitsbytes.tcl]
 source [find memory.tcl]
 source [find mmr_helpers.tcl]
+# Source the ESP common configuration file
+source [find target/esp_common.cfg]
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -60,6 +62,17 @@ $_TARGETNAME configure -event gdb-attach {
 
 xtensa maskisr on
 
+$_TARGETNAME configure -event examine-end {
+	# Need to enable to set 'semihosting_basedir'
+	arm semihosting enable
+	arm semihosting_resexit enable
+	if { [info exists _SEMIHOST_BASEDIR] } {
+		if { $_SEMIHOST_BASEDIR != "" } {
+			arm semihosting_basedir $_SEMIHOST_BASEDIR
+		}
+	}
+}
+
 $_TARGETNAME configure -event reset-assert-post { soft_reset_halt }
 
 gdb_breakpoint_override hard