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openocd: fix conversion string for stdint values

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Detected while converting 'unsigned' to 'unsigned int'.

Use the correct conversion string for stdint values.

Change-Id: I99f3dff4c64dfd7acf2bddb130b56e9ebe1e6c60
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8477
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2024-09-08 23:11:45 +02:00
parent 8750beeb44
commit bf1cf4afbb
24 changed files with 78 additions and 102 deletions
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15
src/target/arm11.c
View File

@@ -43,7 +43,7 @@ static int arm11_check_init(struct arm11_common *arm11)
CHECK_RETVAL(arm11_read_dscr(arm11));
if (!(arm11->dscr & DSCR_HALT_DBG_MODE)) {
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
LOG_DEBUG("DSCR %08" PRIx32, arm11->dscr);
LOG_DEBUG("Bringing target into debug mode");
arm11->dscr |= DSCR_HALT_DBG_MODE;
@@ -241,8 +241,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
registers hold data that was written by one side (CPU or JTAG) and not
read out by the other side.
*/
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)",
(unsigned) arm11->dscr);
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", arm11->dscr);
return ERROR_FAIL;
}
}
@@ -516,7 +515,7 @@ static int arm11_resume(struct target *target, int current,
while (1) {
CHECK_RETVAL(arm11_read_dscr(arm11));
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
LOG_DEBUG("DSCR %08" PRIx32, arm11->dscr);
if (arm11->dscr & DSCR_CORE_RESTARTED)
break;
@@ -662,7 +661,7 @@ static int arm11_step(struct target *target, int current,
| DSCR_CORE_HALTED;
CHECK_RETVAL(arm11_read_dscr(arm11));
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
LOG_DEBUG("DSCR %08" PRIx32 " e", arm11->dscr);
if ((arm11->dscr & mask) == mask)
break;
@@ -1012,10 +1011,8 @@ static int arm11_write_memory_inner(struct target *target,
return retval;
if (address + size * count != r0) {
LOG_ERROR("Data transfer failed. Expected end "
"address 0x%08x, got 0x%08x",
(unsigned) (address + size * count),
(unsigned) r0);
LOG_ERROR("Data transfer failed. Expected end address 0x%08" PRIx32 ", got 0x%08" PRIx32,
address + size * count, r0);
if (burst)
LOG_ERROR(

25
src/target/arm11_dbgtap.c
View File

@@ -242,7 +242,7 @@ int arm11_add_debug_scan_n(struct arm11_common *arm11,
static void arm11_add_debug_inst(struct arm11_common *arm11,
uint32_t inst, uint8_t *flag, tap_state_t state)
{
JTAG_DEBUG("INST <= 0x%08x", (unsigned) inst);
JTAG_DEBUG("INST <= 0x%08" PRIx32, inst);
struct scan_field itr[2];
@@ -282,9 +282,7 @@ int arm11_read_dscr(struct arm11_common *arm11)
CHECK_RETVAL(jtag_execute_queue());
if (arm11->dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)",
(unsigned) dscr,
(unsigned) arm11->dscr);
JTAG_DEBUG("DSCR = %08" PRIx32 " (OLD %08" PRIx32 ")", dscr, arm11->dscr);
arm11->dscr = dscr;
@@ -317,9 +315,7 @@ int arm11_write_dscr(struct arm11_common *arm11, uint32_t dscr)
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DSCR <= %08x (OLD %08x)",
(unsigned) dscr,
(unsigned) arm11->dscr);
JTAG_DEBUG("DSCR <= %08" PRIx32 " (OLD %08" PRIx32 ")", dscr, arm11->dscr);
arm11->dscr = dscr;
@@ -509,8 +505,8 @@ int arm11_run_instr_data_to_core(struct arm11_common *arm11,
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
(unsigned) _data, ready, n_retry);
JTAG_DEBUG("DTR _data %08" PRIx32 " ready %d n_retry %d",
_data, ready, n_retry);
int64_t then = 0;
@@ -754,8 +750,8 @@ int arm11_run_instr_data_from_core(struct arm11_common *arm11,
CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR _data %08x ready %d n_retry %d",
(unsigned) _data, ready, n_retry);
JTAG_DEBUG("DTR _data %08" PRIx32 " ready %d n_retry %d",
_data, ready, n_retry);
int64_t then = 0;
@@ -878,9 +874,8 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions,
/* Timeout here so we don't get stuck. */
int i_n = 0;
while (1) {
JTAG_DEBUG("SC7 <= c%-3d Data %08x %s",
(unsigned) address_out,
(unsigned) data_out,
JTAG_DEBUG("SC7 <= c%-3" PRIu8 " Data %08" PRIx32 " %s",
address_out, data_out,
n_rw ? "write" : "read");
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields),
@@ -908,7 +903,7 @@ int arm11_sc7_run(struct arm11_common *arm11, struct arm11_sc7_action *actions,
}
if (!n_rw)
JTAG_DEBUG("SC7 => Data %08x", (unsigned) data_in);
JTAG_DEBUG("SC7 => Data %08" PRIx32, data_in);
if (i > 0) {
if (actions[i - 1].address != address_in)

15
src/target/arm_disassembler.c
View File

@@ -266,18 +266,18 @@ static int evaluate_srs(uint32_t opcode,
case 0x08400000:
snprintf(instruction->text, 128, "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tSRS%s\tSP%s, #%d",
"\tSRS%s\tSP%s, #%" PRIu32,
address, opcode,
mode, wback,
(unsigned)(opcode & 0x1f));
opcode & 0x1f);
break;
case 0x08100000:
snprintf(instruction->text, 128, "0x%8.8" PRIx32
"\t0x%8.8" PRIx32
"\tRFE%s\tr%d%s",
"\tRFE%s\tr%" PRIu32 "%s",
address, opcode,
mode,
(unsigned)((opcode >> 16) & 0xf), wback);
(opcode >> 16) & 0xf, wback);
break;
default:
return evaluate_unknown(opcode, address, instruction);
@@ -842,7 +842,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
/* halfword pack */
if ((opcode & 0x01f00020) == 0x00800000) {
char *type, *shift;
unsigned imm = (unsigned) (opcode >> 7) & 0x1f;
unsigned int imm = (opcode >> 7) & 0x1f;
if (opcode & (1 << 6)) {
type = "TB";
@@ -865,7 +865,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
/* word saturate */
if ((opcode & 0x01a00020) == 0x00a00000) {
char *shift;
unsigned imm = (unsigned) (opcode >> 7) & 0x1f;
unsigned int imm = (opcode >> 7) & 0x1f;
if (opcode & (1 << 6)) {
shift = "ASR";
@@ -2046,8 +2046,7 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
return evaluate_cdp_mcr_mrc(opcode, address, instruction);
}
LOG_ERROR("ARM: should never reach this point (opcode=%08x)",
(unsigned) opcode);
LOG_ERROR("ARM: should never reach this point (opcode=%08" PRIx32 ")", opcode);
return -1;
}

10
src/target/arm_dpm.c
View File

@@ -198,8 +198,7 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
buf_set_u32(r->value + 4, 0, 32, value_r1);
r->valid = true;
r->dirty = false;
LOG_DEBUG("READ: %s, %8.8x, %8.8x", r->name,
(unsigned) value_r0, (unsigned) value_r1);
LOG_DEBUG("READ: %s, %8.8" PRIx32 ", %8.8" PRIx32, r->name, value_r0, value_r1);
}
return retval;
@@ -266,7 +265,7 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
buf_set_u32(r->value, 0, 32, value);
r->valid = true;
r->dirty = false;
LOG_DEBUG("READ: %s, %8.8x", r->name, (unsigned) value);
LOG_DEBUG("READ: %s, %8.8" PRIx32, r->name, value);
}
return retval;
@@ -302,8 +301,7 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum
if (retval == ERROR_OK) {
r->dirty = false;
LOG_DEBUG("WRITE: %s, %8.8x, %8.8x", r->name,
(unsigned) value_r0, (unsigned) value_r1);
LOG_DEBUG("WRITE: %s, %8.8" PRIx32 ", %8.8" PRIx32, r->name, value_r0, value_r1);
}
return retval;
@@ -351,7 +349,7 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
if (retval == ERROR_OK) {
r->dirty = false;
LOG_DEBUG("WRITE: %s, %8.8x", r->name, (unsigned) value);
LOG_DEBUG("WRITE: %s, %8.8" PRIx32, r->name, value);
}
return retval;

2
src/target/armv4_5.c
View File

@@ -482,7 +482,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
}
arm->core_state = state;
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
arm_mode_name(mode),
arm_state_strings[arm->core_state]);
}

2
src/target/armv8.c
View File

@@ -961,7 +961,7 @@ void armv8_set_cpsr(struct arm *arm, uint32_t cpsr)
arm->core_state = state;
arm->core_mode = mode;
LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
armv8_mode_name(arm->core_mode),
armv8_state_strings[arm->core_state]);
}

5
src/target/armv8_dpm.c
View File

@@ -441,8 +441,7 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
vr += 16 * index_t;
cr += 16 * index_t;
LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
LOG_DEBUG("A8: bpwp enable, vr %08" PRIx32 " cr %08" PRIx32, vr, cr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap, vr, addr);
if (retval != ERROR_OK)
@@ -469,7 +468,7 @@ static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
}
cr += 16 * index_t;
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
LOG_DEBUG("A: bpwp disable, cr %08" PRIx32, cr);
/* clear control register */
return mem_ap_write_atomic_u32(armv8->debug_ap, cr, 0);

5
src/target/cortex_a.c
View File

@@ -595,8 +595,7 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
vr += 4 * index_t;
cr += 4 * index_t;
LOG_DEBUG("A: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
LOG_DEBUG("A: bpwp enable, vr %08" PRIx32 " cr %08" PRIx32, vr, cr);
retval = mem_ap_write_atomic_u32(a->armv7a_common.debug_ap,
vr, addr);
@@ -625,7 +624,7 @@ static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
}
cr += 4 * index_t;
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
LOG_DEBUG("A: bpwp disable, cr %08" PRIx32, cr);
/* clear control register */
return mem_ap_write_atomic_u32(a->armv7a_common.debug_ap, cr, 0);

10
src/target/cortex_m.c
View File

@@ -2081,11 +2081,9 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat
target_write_u32(target, comparator->dwt_comparator_address + 8,
comparator->function);
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08" PRIx32 " 0x%" PRIx32 " 0x%05" PRIx32,
watchpoint->unique_id, dwt_num,
(unsigned) comparator->comp,
(unsigned) comparator->mask,
(unsigned) comparator->function);
comparator->comp, comparator->mask, comparator->function);
return ERROR_OK;
}
@@ -2102,9 +2100,9 @@ static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *w
unsigned int dwt_num = watchpoint->number;
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%u address: 0x%08x clear",
LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%u address: " TARGET_ADDR_FMT " clear",
watchpoint->unique_id, dwt_num,
(unsigned) watchpoint->address);
watchpoint->address);
if (dwt_num >= cortex_m->dwt_num_comp) {
LOG_TARGET_DEBUG(target, "Invalid DWT Comparator number in watchpoint");

10
src/target/dsp563xx.c
View File

@@ -1135,7 +1135,7 @@ static int dsp563xx_resume(struct target *target,
current = 0;
}
LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
LOG_DEBUG("%s %08X %08" TARGET_PRIXADDR, __func__, current, address);
err = dsp563xx_restore_context(target);
if (err != ERROR_OK)
@@ -1199,7 +1199,7 @@ static int dsp563xx_step_ex(struct target *target,
current = 0;
}
LOG_DEBUG("%s %08X %08X", __func__, current, (unsigned) address);
LOG_DEBUG("%s %08X %08" PRIX32, __func__, current, address);
err = dsp563xx_jtag_debug_request(target);
if (err != ERROR_OK)
@@ -1260,15 +1260,15 @@ static int dsp563xx_step_ex(struct target *target,
err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABFR, &dr_in);
if (err != ERROR_OK)
return err;
LOG_DEBUG("fetch: %08X", (unsigned) dr_in&0x00ffffff);
LOG_DEBUG("fetch: %08" PRIX32, dr_in & 0x00ffffff);
err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABDR, &dr_in);
if (err != ERROR_OK)
return err;
LOG_DEBUG("decode: %08X", (unsigned) dr_in&0x00ffffff);
LOG_DEBUG("decode: %08" PRIX32, dr_in & 0x00ffffff);
err = dsp563xx_once_reg_read(target->tap, 1, DSP563XX_ONCE_OPABEX, &dr_in);
if (err != ERROR_OK)
return err;
LOG_DEBUG("execute: %08X", (unsigned) dr_in&0x00ffffff);
LOG_DEBUG("execute: %08" PRIX32, dr_in & 0x00ffffff);
/* reset trace mode */
err = dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OSCR, 0x000000);

7
src/target/etm.c
View File

@@ -320,9 +320,8 @@ struct reg_cache *etm_build_reg_cache(struct target *target,
etm_reg_add(0x20, jtag_info, reg_cache, arch_info,
etm_core + 1, 1);
etm_get_reg(reg_list + 1);
etm_ctx->id = buf_get_u32(
arch_info[1].value, 0, 32);
LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx->id);
etm_ctx->id = buf_get_u32(arch_info[1].value, 0, 32);
LOG_DEBUG("ETM ID: %08" PRIx32, etm_ctx->id);
bcd_vers = 0x10 + (((etm_ctx->id) >> 4) & 0xff);
} else {
@@ -1495,7 +1494,7 @@ COMMAND_HANDLER(handle_etm_info_command)
etm_get_reg(etm_sys_config_reg);
config = buf_get_u32(etm_sys_config_reg->value, 0, 32);
LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config);
LOG_DEBUG("ETM SYS CONFIG %08" PRIx32, config);
max_port_size = config & 0x7;
if (etm->bcd_vers >= 0x30)

10
src/target/target.c
View File

@@ -3851,11 +3851,11 @@ static COMMAND_HELPER(handle_verify_image_command_internal, enum verify_mode ver
for (t = 0; t < buf_cnt; t++) {
if (data[t] != buffer[t]) {
command_print(CMD,
"diff %d address 0x%08x. Was 0x%02x instead of 0x%02x",
diffs,
(unsigned)(t + image.sections[i].base_address),
data[t],
buffer[t]);
"diff %d address " TARGET_ADDR_FMT ". Was 0x%02" PRIx8 " instead of 0x%02" PRIx8,
diffs,
t + image.sections[i].base_address,
data[t],
buffer[t]);
if (diffs++ >= 127) {
command_print(CMD, "More than 128 errors, the rest are not printed.");
free(data);

4
src/target/x86_32_common.c
View File

@@ -1360,8 +1360,8 @@ static void handle_iod_output(struct command_invocation *cmd,
if (i % line_modulo == 0) {
output_len += snprintf(output + output_len,
sizeof(output) - output_len,
"0x%8.8x: ",
(unsigned)(address + (i*size)));
"0x%8.8" PRIx32 ": ",
address + (i * size));
}
uint32_t value = 0;