auracaster/openocd
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- correct the register hi/lo read - wrong way round

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- all the register now can be written to, including the special CP0 regs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@1169 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
2008-11-13 21:40:26 +00:00
parent 368daf44ff
commit c0787b6994
4 changed files with 76 additions and 59 deletions
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28
src/target/mips_m4k.c
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@@ -139,6 +139,21 @@ int mips_m4k_poll(target_t *target)
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
/* clear this bit before handling polling
* as after reset registers will read zero */
if (ejtag_ctrl & EJTAG_CTRL_ROCC)
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
jtag_add_end_state(TAP_RTI);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
/* check for processor halted */
if (ejtag_ctrl & EJTAG_CTRL_BRKST)
{
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
@@ -168,18 +183,6 @@ int mips_m4k_poll(target_t *target)
target->state = TARGET_RUNNING;
}
if (ejtag_ctrl & EJTAG_CTRL_ROCC)
{
/* we have detected a reset, clear flag
* otherwise ejtag will not work */
jtag_add_end_state(TAP_RTI);
ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("Reset Detected");
}
// LOG_DEBUG("ctrl=0x%08X", ejtag_ctrl);
return ERROR_OK;
@@ -289,7 +292,6 @@ int mips_m4k_assert_reset(target_t *target)
return retval;
}
return ERROR_OK;
}