Reset wip. Just adding hooks. This is just to reduce the size of the actual change, no change in behaviour.
git-svn-id: svn://svn.berlios.de/openocd/trunk@565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@@ -755,14 +755,6 @@ int arm7_9_assert_reset(target_t *target)
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if ((target->reset_mode == RESET_HALT) || (target->reset_mode == RESET_INIT))
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{
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reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
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/* program EmbeddedICE Debug Control Register to deassert DBGRQ
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* i.e. resume.
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*/
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buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGRQ, 1, 0);
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embeddedice_store_reg(dbg_ctrl);
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/*
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* Some targets do not support communication while SRST is asserted. We need to
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* set up the reset vector catch here.
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@@ -867,7 +859,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
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int i;
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int retval;
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if ((retval=target->type->halt(target))!=ERROR_OK)
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if ((retval=target_halt(target))!=ERROR_OK)
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return retval;
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for (i=0; i<10; i++)
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@@ -2176,11 +2168,11 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
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}
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}
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target->type->halt(target);
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target_halt(target);
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for (i=0; i<100; i++)
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{
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target->type->poll(target);
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target_poll(target);
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if (target->state == TARGET_HALTED)
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break;
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usleep(1000); /* sleep 1ms */
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