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contrib/firmware: Add direction control for 'SCL' i2c signal

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We want to keep the tri-state buffers located between the FPGA
and the board, in 'Z' state until we launch an i2c connection.

We launch an i2c start condition, make the SCL
direction 'OUT' to start the i2c protocol and at the end
of the i2c connection at the stop condition, we re-make
the tri-state buffers at 'Z' state.

Change-Id: Ic597a70d0427832547f6b539864c24ce20a18c64
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7989
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ahmed BOUDJELIDA
2023-11-29 15:21:27 +01:00
committed by Antonio Borneo
parent 995a7af21d
commit c7073853eb
7 changed files with 22 additions and 13 deletions
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1
contrib/firmware/angie/hdl/src/angie_bitstream.ucf
View File

@@ -20,6 +20,7 @@ net SRST LOC = 'P61' ;
net SDA LOC = 'P50' ;
net SCL LOC = 'P51' ;
net SDA_DIR LOC = 'P56' ;
net SCL_DIR LOC = 'P57' ;
net SI_TDO LOC = 'P16' ;
net SO_TRST LOC = 'P32' ;

19
contrib/firmware/angie/hdl/src/angie_bitstream.vhd
View File

@@ -26,8 +26,9 @@ entity S609 is port(
SDA : inout std_logic;
SDA_DIR : in std_logic;
SCL : in std_logic;
SCL_DIR : in std_logic;
FTP : out std_logic_vector(7 downto 0):=(others => '1'); -- Test points
FTP : out std_logic_vector(7 downto 0); -- Test points
SI_TDO : in std_logic;
ST_0 : out std_logic;
ST_1 : out std_logic;
@@ -55,8 +56,6 @@ begin
ST_0 <= '0';
ST_1 <= '1';
ST_4 <= '0';
--TDO:
TDO <= not SI_TDO;
@@ -75,13 +74,21 @@ SO_SDA_OUT <= SDA;
process(SDA_DIR)
begin
if(SDA_DIR = '1') then
ST_5 <= '1';
else
if(SDA_DIR = '0') then
ST_5 <= '0';
else
ST_5 <= '1';
end if;
end process;
process(SCL_DIR)
begin
if(SCL_DIR = '0') then
ST_4 <= '0';
else
ST_4 <= '1';
end if;
end process;
--Points de test:
FTP(0) <= SDA;