David Kuehling <dvdkhlng@gmx.de> - added jim-eventloop.c

git-svn-id: svn://svn.berlios.de/openocd/trunk@898 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/target/Makefile.am

@@ -37,5 +37,5 @@ nobase_dist_pkglib_DATA = xscale/debug_handler.bin event/at91eb40a_reset.script
 	interface/signalyzer.cfg event/eir-sam7se512_reset.script target/eir-sam7se512.cfg \
 	event/hammer_reset.script interface/flyswatter.cfg target/hammer.cfg target/mx31.cfg  \
 	event/str730_program.script event/str750_program.script interface/olimex-jtag-tiny-a.cfg \
-	target/pic32mx.cfg
+	target/pic32mx.cfg target/aduc702x.cfg interface/dummy.cfg interface/olimex-arm-usb-ocd.cfg
 

src/target/interface/dummy.cfg

@@ -0,0 +1 @@
+interface dummy

src/target/interface/olimex-arm-usb-ocd.cfg

@@ -0,0 +1,4 @@
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG"
+ft2232_layout olimex-jtag
+ft2232_vid_pid 0x15ba 0x0003

src/target/target/aduc702x.cfg

@@ -0,0 +1,38 @@
+## -*- tcl -*-
+##
+
+# This is for the case that TRST/SRST is not wired on your JTAG adaptor.
+# Don't really need them anyways.  
+reset_config none
+
+## JTAG scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+##
+## Target configuration
+##
+target arm7tdmi little 0
+
+## software initiated reset (if your SRST isn't wired)
+#proc target_0_reset {} { mwb 0x0ffff0230 04 }
+
+# use top 1k of SRAM for as temporary JTAG memory 
+#working_area 0 0x11C00 0x400 backup
+
+## flash configuration
+## AdUC702x not yet spported  :(
+
+## If you use the watchdog, the following code makes sure that the board
+## doesn't reboot when halted via JTAG.  Yes, on the older generation
+## AdUC702x, timer3 continues running even when the CPU is halted.
+
+proc watchdog_service {} {
+    global watchdog_hdl
+    mww 0xffff036c 0
+#    puts "watchdog!!"
+    set watchdog_hdl [after 500 watchdog_service]
+}
+
+proc target_0_post_halt {} { watchdog_service }
+proc arget_0_pre_resume {} { global watchdog_hdl; after cancel $watchdog_hdl }