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tcl/target: add Bouffalo Lab BL602 and BL702L chip series support

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BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.

This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).

Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Marek Kraus
2024-11-23 15:54:26 +01:00
committed by Antonio Borneo
parent e1425845ea
commit c986b4dbf2
4 changed files with 234 additions and 49 deletions
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59
tcl/target/bl702.cfg
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@@ -12,62 +12,23 @@
# TDO - GPIO9
#
source [find mem_helper.tcl]
transport select jtag
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
set BL602_CHIPNAME $CHIPNAME
} else {
set _CHIPNAME bl702
set BL602_CHIPNAME bl702
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
set CPUTAPID 0x20000e05
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
set WORKAREAADDR 0x22014000
set WORKAREASIZE 0xC000
riscv set_mem_access sysbus
source [find target/bl602_common.cfg]
$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
# Internal RC ticks on 32 MHz, so this speed should be safe to use.
adapter speed 4000
# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
# CTRL_PWRON_RESET triggers full "power-on like" reset.
# This means that pinmux configuration to access JTAG is reset as well, and configured back early
# in BootROM.
$_TARGETNAME configure -event reset-assert-pre {
# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
$_TARGETNAME configure -event reset-assert {
halt
# Switch clock to internal RC32M
# In HBN_GLB, set ROOT_CLK_SEL = 0
mmw 0x4000f030 0x0 0x00000003
# Wait for clock switch
sleep 10
# GLB_REG_BCLK_DIS_FALSE
mww 0x40000ffc 0x0
# HCLK is RC32M, so BCLK/HCLK doesn't need divider
# In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
mmw 0x40000000 0x0 0x00FFFF00
# Wait for clock to stabilize
sleep 10
# Do reset
# In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
mmw 0x40000018 0x0 0x00000007
# Since this full software reset resets GPIO pinmux as well, we will lose access
# to JTAG right away after writing to register. This chip doesn't support abstract
# memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
# if write was successful or not, and will print error about that. Since receiving of
# this error is expected, we will turn off log printing for a moment,
set lvl [lindex [debug_level] 1]
debug_level -1
# In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
catch {mmw 0x40000018 0x7 0x0}
debug_level $lvl
bl602_sw_reset_hbn_wait
}