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target config files: Fix whitespace issues.

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Drop useless double-space occurences, drop trailing whitespace, and fix
some other minor whitespace-related issues.

Change-Id: I6b4c515492e2ee94dc25ef1fe4f51015a4bba8b5
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/137
Tested-by: jenkins
This commit is contained in:
Uwe Hermann
2011-10-29 23:32:17 +02:00
committed by Spencer Oliver
parent 17b546a900
commit ca45e700b1
86 changed files with 503 additions and 508 deletions
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14
tcl/target/ti_dm6446.cfg
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@@ -1,10 +1,10 @@
#
# Texas Instruments DaVinci family: TMS320DM6446
# Texas Instruments DaVinci family: TMS320DM6446
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME dm6446
set _CHIPNAME dm6446
}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
@@ -28,7 +28,7 @@ jtag configure $_CHIPNAME.dsp -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 2"
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID ] } {
if { [info exists ETB_TAPID] } {
set _ETB_TAPID $ETB_TAPID
} else {
set _ETB_TAPID 0x2b900f0f
@@ -38,7 +38,7 @@ jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID ] } {
if { [info exists CPU_TAPID] } {
set _CPU_TAPID $CPU_TAPID
} else {
set _CPU_TAPID 0x07926001
@@ -48,7 +48,7 @@ jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID ] } {
if { [info exists JRC_TAPID] } {
set _JRC_TAPID $JRC_TAPID
} else {
set _JRC_TAPID 0x0b70002f
@@ -59,7 +59,7 @@ jtag configure $_CHIPNAME.jrc -event setup \
"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
# Little-endian; use the OpenOCD default.
set _TARGETNAME $_CHIPNAME.arm