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error checking - no reported errors, but catched a couple of exit()'s and converted them to errors.

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git-svn-id: svn://svn.berlios.de/openocd/trunk@1175 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
oharboe
2008-11-19 07:32:30 +00:00
parent 6c15861bd8
commit cb434c21af
5 changed files with 186 additions and 178 deletions
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188
src/target/etb.c
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@@ -63,11 +63,11 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
int etb_set_instr(etb_t *etb, u32 new_instr)
{
jtag_device_t *device = jtag_get_device(etb->chain_pos);
if (buf_get_u32(device->cur_instr, 0, device->ir_length) != new_instr)
{
scan_field_t field;
field.device = etb->chain_pos;
field.num_bits = device->ir_length;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
@@ -78,12 +78,12 @@ int etb_set_instr(etb_t *etb, u32 new_instr)
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
jtag_add_ir_scan(1, &field, -1);
free(field.out_value);
}
return ERROR_OK;
}
@@ -92,7 +92,7 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
if(etb->cur_scan_chain != new_scan_chain)
{
scan_field_t field;
field.device = etb->chain_pos;
field.num_bits = 5;
field.out_value = calloc(CEIL(field.num_bits, 8), 1);
@@ -103,13 +103,13 @@ int etb_scann(etb_t *etb, u32 new_scan_chain)
field.in_check_mask = NULL;
field.in_handler = NULL;
field.in_handler_priv = NULL;
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
jtag_add_dr_scan(1, &field, -1);
etb->cur_scan_chain = new_scan_chain;
free(field.out_value);
}
@@ -123,21 +123,21 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
etb_reg_t *arch_info = NULL;
int num_regs = 9;
int i;
/* register a register arch-type for etm registers only once */
if (etb_reg_arch_type == -1)
etb_reg_arch_type = register_reg_arch_type(etb_get_reg, etb_set_reg_w_exec);
/* the actual registers are kept in two arrays */
reg_list = calloc(num_regs, sizeof(reg_t));
arch_info = calloc(num_regs, sizeof(etb_reg_t));
/* fill in values for the reg cache */
reg_cache->name = "etb registers";
reg_cache->next = NULL;
reg_cache->reg_list = reg_list;
reg_cache->num_regs = num_regs;
/* set up registers */
for (i = 0; i < num_regs; i++)
{
@@ -154,7 +154,7 @@ reg_cache_t* etb_build_reg_cache(etb_t *etb)
arch_info[i].addr = i;
arch_info[i].etb = etb;
}
return reg_cache;
}
@@ -166,13 +166,13 @@ int etb_get_reg(reg_t *reg)
LOG_ERROR("BUG: error scheduling etm register read");
return retval;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register read failed");
return retval;
}
return ERROR_OK;
}
@@ -180,11 +180,11 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
{
scan_field_t fields[3];
int i;
jtag_add_end_state(TAP_RTI);
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
fields[0].device = etb->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
@@ -194,7 +194,7 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = etb->chain_pos;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
@@ -216,31 +216,31 @@ int etb_read_ram(etb_t *etb, u32 *data, int num_frames)
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1);
fields[0].in_handler = buf_to_u32_handler;
for (i = 0; i < num_frames; i++)
{
/* ensure nR/W reamins set to read */
buf_set_u32(fields[2].out_value, 0, 1, 0);
/* address remains set to 0x4 (RAM data) until we read the last frame */
if (i < num_frames - 1)
buf_set_u32(fields[1].out_value, 0, 7, 4);
else
buf_set_u32(fields[1].out_value, 0, 7, 0);
fields[0].in_handler_priv = &data[i];
jtag_add_dr_scan(3, fields, -1);
}
jtag_execute_queue();
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
@@ -249,13 +249,13 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
etb_reg_t *etb_reg = reg->arch_info;
u8 reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
LOG_DEBUG("%i", etb_reg->addr);
jtag_add_end_state(TAP_RTI);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].device = etb_reg->etb->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
@@ -265,7 +265,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = etb_reg->etb->chain_pos;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
@@ -287,28 +287,28 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1);
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
*/
buf_set_u32(fields[1].out_value, 0, 7, 0x0);
fields[0].in_value = reg->value;
jtag_set_check_value(fields+0, check_value, check_mask, NULL);
jtag_add_dr_scan(3, fields, -1);
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
int etb_read_reg(reg_t *reg)
{
return etb_read_reg_w_check(reg, NULL, NULL);
return etb_read_reg_w_check(reg, NULL, NULL);
}
int etb_set_reg(reg_t *reg, u32 value)
@@ -319,11 +319,11 @@ int etb_set_reg(reg_t *reg, u32 value)
LOG_ERROR("BUG: error scheduling etm register write");
return retval;
}
buf_set_u32(reg->value, 0, reg->size, value);
reg->valid = 1;
reg->dirty = 0;
return ERROR_OK;
}
@@ -331,7 +331,7 @@ int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
{
int retval;
etb_set_reg(reg, buf_get_u32(buf, 0, reg->size));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
LOG_ERROR("register write failed");
@@ -345,13 +345,13 @@ int etb_write_reg(reg_t *reg, u32 value)
etb_reg_t *etb_reg = reg->arch_info;
u8 reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
jtag_add_end_state(TAP_RTI);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].device = etb_reg->etb->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
@@ -362,7 +362,7 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = etb_reg->etb->chain_pos;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
@@ -384,13 +384,13 @@ int etb_write_reg(reg_t *reg, u32 value)
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1);
free(fields[0].out_value);
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
@@ -402,9 +402,9 @@ int etb_store_reg(reg_t *reg)
int etb_register_commands(struct command_context_s *cmd_ctx)
{
command_t *etb_cmd;
etb_cmd = register_command(cmd_ctx, NULL, "etb", NULL, COMMAND_ANY, "Embedded Trace Buffer");
register_command(cmd_ctx, etb_cmd, "config", handle_etb_config_command, COMMAND_CONFIG, NULL);
return ERROR_OK;
@@ -416,41 +416,40 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
jtag_device_t *jtag_device;
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
if (argc != 2)
{
LOG_ERROR("incomplete 'etb config <target> <chain_pos>' command");
exit(-1);
return ERROR_COMMAND_SYNTAX_ERROR;
}
target = get_target_by_num(strtoul(args[0], NULL, 0));
if (!target)
{
LOG_ERROR("target number '%s' not defined", args[0]);
exit(-1);
return ERROR_FAIL;
}
if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
{
command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
return ERROR_OK;
return ERROR_FAIL;
}
jtag_device = jtag_get_device(strtoul(args[1], NULL, 0));
if (!jtag_device)
{
LOG_ERROR("jtag device number '%s' not defined", args[1]);
exit(-1);
return ERROR_FAIL;
}
if (arm7_9->etm_ctx)
{
etb_t *etb = malloc(sizeof(etb_t));
arm7_9->etm_ctx->capture_driver_priv = etb;
etb->chain_pos = strtoul(args[1], NULL, 0);
etb->cur_scan_chain = -1;
etb->reg_cache = NULL;
@@ -460,6 +459,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
else
{
LOG_ERROR("target has no ETM defined, ETB left unconfigured");
return ERROR_FAIL;
}
return ERROR_OK;
@@ -468,9 +468,9 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
int etb_init(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
etb->etm_ctx = etm_ctx;
/* identify ETB RAM depth and width */
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
@@ -478,16 +478,16 @@ int etb_init(etm_context_t *etm_ctx)
etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
return ERROR_OK;
}
trace_status_t etb_status(etm_context_t *etm_ctx)
{
etb_t *etb = etm_ctx->capture_driver_priv;
etb->etm_ctx = etm_ctx;
/* if tracing is currently idle, return this information */
if (etm_ctx->capture_status == TRACE_IDLE)
{
@@ -497,10 +497,10 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
{
reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
int etb_timeout = 100;
/* trace is running, check the ETB status flags */
etb_get_reg(etb_status_reg);
/* check Full bit to identify an overflow */
if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
etm_ctx->capture_status |= TRACE_OVERFLOWED;
@@ -517,23 +517,23 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
/* wait for data formatter idle */
etb_get_reg(etb_status_reg);
}
if (etb_timeout == 0)
{
LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
}
if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
{
LOG_ERROR("trace completed, but no trigger condition detected");
}
etm_ctx->capture_status &= ~TRACE_RUNNING;
etm_ctx->capture_status |= TRACE_COMPLETED;
}
}
return etm_ctx->capture_status;
}
@@ -544,11 +544,11 @@ int etb_read_trace(etm_context_t *etm_ctx)
int num_frames = etb->ram_depth;
u32 *trace_data = NULL;
int i, j;
etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
jtag_execute_queue();
/* check if we overflowed, and adjust first frame of the trace accordingly
* if we didn't overflow, read only up to the frame that would be written next,
* i.e. don't read invalid entries
@@ -561,10 +561,10 @@ int etb_read_trace(etm_context_t *etm_ctx)
{
num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
}
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_READ_POINTER], first_frame);
/* read data into temporary array for unpacking */
/* read data into temporary array for unpacking */
trace_data = malloc(sizeof(u32) * num_frames);
etb_read_ram(etb, trace_data, num_frames);
@@ -572,7 +572,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
{
free(etm_ctx->trace_data);
}
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
etm_ctx->trace_depth = num_frames * 3;
else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
@@ -581,7 +581,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_depth = num_frames;
etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
for (i = 0, j = 0; i < num_frames; i++)
{
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
@@ -599,7 +599,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
/* trace word j+1 */
etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
@@ -613,7 +613,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
}
/* trace word j+2 */
etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
@@ -627,7 +627,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 3;
}
else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
@@ -659,7 +659,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 2;
}
else
@@ -677,13 +677,13 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 1;
}
}
free(trace_data);
return ERROR_OK;
}
@@ -702,21 +702,21 @@ int etb_start_capture(etm_context_t *etm_ctx)
}
etb_ctrl_value |= 0x2;
}
if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
etb_write_reg(&etb->reg_cache->reg_list[ETB_CTRL], etb_ctrl_value);
jtag_execute_queue();
/* we're starting a new trace, initialize capture status */
etm_ctx->capture_status = TRACE_RUNNING;
return ERROR_OK;
return ERROR_OK;
}
int etb_stop_capture(etm_context_t *etm_ctx)
@@ -726,10 +726,10 @@ int etb_stop_capture(etm_context_t *etm_ctx)
etb_write_reg(etb_ctrl_reg, 0x0);
jtag_execute_queue();
/* trace stopped, just clear running flag, but preserve others */
/* trace stopped, just clear running flag, but preserve others */
etm_ctx->capture_status &= ~TRACE_RUNNING;
return ERROR_OK;
}