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target: add generic Xtensa LX support

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Generic Xtensa LX support extends the original Espressif/Xtensa
patch-set to support arbitrary Xtensa configurations, as defined in
a core-specific .cfg file.  Not yet fully-featured.  Additional
functionality to be added:
- Xtensa NX support
- DAP/SWD support
- File-IO support
- Generic Xtensa multi-core support

Valgrind-clean, no new Clang analyzer warnings

Signed-off-by: Ian Thompson <ianst@cadence.com>
Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52
Reviewed-on: https://review.openocd.org/c/openocd/+/7055
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ian Thompson
2022-06-24 22:27:32 -07:00
committed by Antonio Borneo
parent be2e5c6c35
commit ce5ca9f7ba
25 changed files with 3589 additions and 1800 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/target/espressif/Makefile.am
View File

@@ -7,8 +7,5 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
%D%/esp32.c \
%D%/esp32.h \
%D%/esp32s2.c \
%D%/esp32s2.h \
%D%/esp32s3.c \
%D%/esp32s3.h
%D%/esp32s3.c

205
src/target/espressif/esp32.c
View File

@@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
#include "esp32.h"
#include "esp_xtensa_smp.h"
/*
@@ -70,204 +69,6 @@ implementation.
#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
*xtensa-overlay */
static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = {
XT_REG_IDX_PC,
XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
ESP32_REG_IDX_EXPSTATE,
ESP32_REG_IDX_F64R_LO,
ESP32_REG_IDX_F64R_HI,
ESP32_REG_IDX_F64S,
XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
};
static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = {
{ "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type },
{ "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type },
{ "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type },
{ "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type },
};
static const struct xtensa_config esp32_xtensa_cfg = {
.density = true,
.aregs_num = XT_AREGS_NUM_MAX,
.windowed = true,
.coproc = true,
.fp_coproc = true,
.loop = true,
.miscregs_num = 4,
.threadptr = true,
.boolean = true,
.reloc_vec = true,
.proc_id = true,
.cond_store = true,
.mac16 = true,
.user_regs_num = ARRAY_SIZE(esp32_user_regs),
.user_regs = esp32_user_regs,
.fetch_user_regs = xtensa_fetch_user_regs_u32,
.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
.gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND,
.gdb_regs_mapping = esp32_gdb_regs_mapping,
.irom = {
.count = 2,
.regions = {
{
.base = ESP32_IROM_LOW,
.size = ESP32_IROM_HIGH - ESP32_IROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_IROM_MASK_LOW,
.size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.iram = {
.count = 2,
.regions = {
{
.base = ESP32_IRAM_LOW,
.size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_RTC_IRAM_LOW,
.size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.drom = {
.count = 1,
.regions = {
{
.base = ESP32_DROM_LOW,
.size = ESP32_DROM_HIGH - ESP32_DROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.dram = {
.count = 6,
.regions = {
{
.base = ESP32_DRAM_LOW,
.size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_RTC_DRAM_LOW,
.size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_RTC_DATA_LOW,
.size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_EXTRAM_DATA_LOW,
.size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_DR_REG_LOW,
.size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_SYS_RAM_LOW,
.size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.exc = {
.enabled = true,
},
.irq = {
.enabled = true,
.irq_num = 32,
},
.high_irq = {
.enabled = true,
.excm_level = 3,
.nmi_num = 1,
},
.tim_irq = {
.enabled = true,
.comp_num = 3,
},
.debug = {
.enabled = true,
.irq_level = 6,
.ibreaks_num = 2,
.dbreaks_num = 2,
.icount_sz = 32,
},
.trace = {
.enabled = true,
.mem_sz = ESP32_TRACEMEM_BLOCK_SZ,
.reversed_mem_access = true,
},
};
/* 0 - don't care, 1 - TMS low, 2 - TMS high */
enum esp32_flash_bootstrap {
FBS_DONTCARE = 0,
@@ -401,7 +202,8 @@ static int esp32_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
target->state);
get_timeout = true;
break;
}
@@ -481,7 +283,6 @@ static int esp32_virt2phys(struct target *target,
return ERROR_FAIL;
}
/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
* can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
* esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
@@ -544,7 +345,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg,
int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
&esp32_dm_cfg, &esp32_chip_ops);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");

31
src/target/espressif/esp32.h
View File

@@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* ESP32 target for OpenOCD *
* Copyright (C) 2017 Espressif Systems Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32_H
#define OPENOCD_TARGET_ESP32_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_DROM_LOW 0x3F400000
#define ESP32_DROM_HIGH 0x3F800000
#define ESP32_IROM_LOW 0x400D0000
#define ESP32_IROM_HIGH 0x40400000
/* Number of registers returned directly by the G command
* Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_NUM_REGS_G_COMMAND 105
enum esp32_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START,
ESP32_REG_IDX_F64R_LO,
ESP32_REG_IDX_F64R_HI,
ESP32_REG_IDX_F64S,
ESP32_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32_H */

196
src/target/espressif/esp32s2.c
View File

@@ -14,7 +14,6 @@
#include <target/target.h>
#include <target/target_type.h>
#include "esp_xtensa.h"
#include "esp32s2.h"
/* Overall memory map
* TODO: read memory configuration from target registers */
@@ -89,190 +88,6 @@
#define ESP32_S2_DR_REG_UART_BASE 0x3f400000
#define ESP32_S2_REG_UART_BASE(i) (ESP32_S2_DR_REG_UART_BASE + (i) * 0x10000)
#define ESP32_S2_UART_DATE_REG(i) (ESP32_S2_REG_UART_BASE(i) + 0x74)
/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
* xtensa-overlay */
static const unsigned int esp32s2_gdb_regs_mapping[ESP32_S2_NUM_REGS] = {
XT_REG_IDX_PC,
XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
XT_REG_IDX_SAR,
XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS, XT_REG_IDX_THREADPTR,
ESP32_S2_REG_IDX_GPIOOUT,
XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE, XT_REG_IDX_OCD_DDR,
XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
};
static const struct xtensa_user_reg_desc esp32s2_user_regs[ESP32_S2_NUM_REGS - XT_NUM_REGS] = {
{ "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
};
static const struct xtensa_config esp32s2_xtensa_cfg = {
.density = true,
.aregs_num = XT_AREGS_NUM_MAX,
.windowed = true,
.coproc = true,
.miscregs_num = 4,
.reloc_vec = true,
.proc_id = true,
.threadptr = true,
.user_regs_num = ARRAY_SIZE(esp32s2_user_regs),
.user_regs = esp32s2_user_regs,
.fetch_user_regs = xtensa_fetch_user_regs_u32,
.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
.gdb_general_regs_num = ESP32_S2_NUM_REGS_G_COMMAND,
.gdb_regs_mapping = esp32s2_gdb_regs_mapping,
.irom = {
.count = 2,
.regions = {
{
.base = ESP32_S2_IROM_LOW,
.size = ESP32_S2_IROM_HIGH - ESP32_S2_IROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_S2_IROM_MASK_LOW,
.size = ESP32_S2_IROM_MASK_HIGH - ESP32_S2_IROM_MASK_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.iram = {
.count = 2,
.regions = {
{
.base = ESP32_S2_IRAM_LOW,
.size = ESP32_S2_IRAM_HIGH - ESP32_S2_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_RTC_IRAM_LOW,
.size = ESP32_S2_RTC_IRAM_HIGH - ESP32_S2_RTC_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.drom = {
.count = 2,
.regions = {
{
.base = ESP32_S2_DROM0_LOW,
.size = ESP32_S2_DROM0_HIGH - ESP32_S2_DROM0_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_S2_DROM1_LOW,
.size = ESP32_S2_DROM1_HIGH - ESP32_S2_DROM1_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.dram = {
.count = 6,
.regions = {
{
.base = ESP32_S2_DRAM_LOW,
.size = ESP32_S2_DRAM_HIGH - ESP32_S2_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_RTC_DRAM_LOW,
.size = ESP32_S2_RTC_DRAM_HIGH - ESP32_S2_RTC_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_RTC_DATA_LOW,
.size = ESP32_S2_RTC_DATA_HIGH - ESP32_S2_RTC_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_EXTRAM_DATA_LOW,
.size = ESP32_S2_EXTRAM_DATA_HIGH - ESP32_S2_EXTRAM_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_DR_REG_LOW,
.size = ESP32_S2_DR_REG_HIGH - ESP32_S2_DR_REG_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S2_SYS_RAM_LOW,
.size = ESP32_S2_SYS_RAM_HIGH - ESP32_S2_SYS_RAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.exc = {
.enabled = true,
},
.irq = {
.enabled = true,
.irq_num = 32,
},
.high_irq = {
.enabled = true,
.excm_level = 3,
.nmi_num = 1,
},
.tim_irq = {
.enabled = true,
.comp_num = 3,
},
.debug = {
.enabled = true,
.irq_level = 6,
.ibreaks_num = 2,
.dbreaks_num = 2,
.icount_sz = 32,
},
.trace = {
.enabled = true,
.mem_sz = ESP32_S2_TRACEMEM_BLOCK_SZ,
},
};
struct esp32s2_common {
struct esp_xtensa_common esp_xtensa;
};
@@ -313,7 +128,7 @@ int esp32s2_soft_reset_halt(struct target *target)
int res = esp32s2_soc_reset(target);
if (res != ERROR_OK)
return res;
return xtensa_assert_reset(target);
return xtensa_soft_reset_halt(target);
}
static int esp32s2_set_peri_reg_mask(struct target *target,
@@ -476,7 +291,8 @@ static int esp32s2_soc_reset(struct target *target)
alive_sleep(10);
xtensa_poll(target);
if (timeval_ms() >= timeout) {
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
target->state);
return ERROR_TARGET_TIMEOUT;
}
}
@@ -638,7 +454,7 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
return ERROR_FAIL;
}
int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_xtensa_cfg, &esp32s2_dm_cfg);
int ret = esp_xtensa_init_arch_info(target, &esp32->esp_xtensa, &esp32s2_dm_cfg);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to init arch info!");
free(esp32);
@@ -653,10 +469,6 @@ static int esp32s2_target_create(struct target *target, Jim_Interp *interp)
static const struct command_registration esp32s2_command_handlers[] = {
{
.name = "xtensa",
.mode = COMMAND_ANY,
.help = "Xtensa commands group",
.usage = "",
.chain = xtensa_command_handlers,
},
COMMAND_REGISTRATION_DONE

28
src/target/espressif/esp32s2.h
View File

@@ -1,28 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* ESP32-S2 target for OpenOCD *
* Copyright (C) 2019 Espressif Systems Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32S2_H
#define OPENOCD_TARGET_ESP32S2_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_S2_DROM_LOW 0x3f000000
#define ESP32_S2_DROM_HIGH 0x3ff80000
#define ESP32_S2_IROM_LOW 0x40080000
#define ESP32_S2_IROM_HIGH 0x40800000
/* Number of registers returned directly by the G command
* Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_S2_NUM_REGS_G_COMMAND 72
enum esp32s2_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_S2_REG_IDX_GPIOOUT = XT_USR_REG_START,
ESP32_S2_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32S2_H */

239
src/target/espressif/esp32s3.c
View File

@@ -14,7 +14,6 @@
#include <target/target_type.h>
#include <target/smp.h>
#include "assert.h"
#include "esp32s3.h"
#include "esp_xtensa_smp.h"
/*
@@ -75,246 +74,10 @@ implementation.
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_REG (ESP32_S3_RTCCNTL_BASE + 0xBC)
#define ESP32_S3_RTC_CNTL_SW_CPU_STALL_DEF 0x0
/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
*xtensa-overlay */
static const unsigned int esp32s3_gdb_regs_mapping[ESP32_S3_NUM_REGS] = {
XT_REG_IDX_PC,
XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
ESP32_S3_REG_IDX_GPIOOUT,
XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
XT_REG_IDX_FCR, XT_REG_IDX_FSR,
ESP32_S3_REG_IDX_ACCX_0, ESP32_S3_REG_IDX_ACCX_1,
ESP32_S3_REG_IDX_QACC_H_0, ESP32_S3_REG_IDX_QACC_H_1, ESP32_S3_REG_IDX_QACC_H_2,
ESP32_S3_REG_IDX_QACC_H_3, ESP32_S3_REG_IDX_QACC_H_4,
ESP32_S3_REG_IDX_QACC_L_0, ESP32_S3_REG_IDX_QACC_L_1, ESP32_S3_REG_IDX_QACC_L_2,
ESP32_S3_REG_IDX_QACC_L_3, ESP32_S3_REG_IDX_QACC_L_4,
ESP32_S3_REG_IDX_SAR_BYTE, ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
ESP32_S3_REG_IDX_UA_STATE_0, ESP32_S3_REG_IDX_UA_STATE_1, ESP32_S3_REG_IDX_UA_STATE_2,
ESP32_S3_REG_IDX_UA_STATE_3,
ESP32_S3_REG_IDX_Q0, ESP32_S3_REG_IDX_Q1, ESP32_S3_REG_IDX_Q2, ESP32_S3_REG_IDX_Q3,
ESP32_S3_REG_IDX_Q4, ESP32_S3_REG_IDX_Q5, ESP32_S3_REG_IDX_Q6, ESP32_S3_REG_IDX_Q7,
XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
XT_REG_IDX_FAULT_INFO,
XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
XT_REG_IDX_TRAX_MEMEND,
XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
};
/* actually this table contains user + TIE registers
* TODO: for TIE registers we need to specify custom access functions instead of `xtensa_user_reg_xxx_type`*/
static const struct xtensa_user_reg_desc esp32s3_user_regs[ESP32_S3_NUM_REGS - XT_NUM_REGS] = {
{ "gpio_out", 0x00, 0, 32, &xtensa_user_reg_u32_type },
{ "accx_0", 0x01, 0, 32, &xtensa_user_reg_u32_type },
{ "accx_1", 0x02, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_0", 0x03, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_1", 0x04, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_2", 0x05, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_3", 0x06, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_h_4", 0x07, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_0", 0x08, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_1", 0x09, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_2", 0x0A, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_3", 0x0B, 0, 32, &xtensa_user_reg_u32_type },
{ "qacc_l_4", 0x0C, 0, 32, &xtensa_user_reg_u32_type },
{ "sar_byte", 0x0D, 0, 32, &xtensa_user_reg_u32_type },
{ "fft_bit_width", 0x0E, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_0", 0x0F, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_1", 0x10, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_2", 0x11, 0, 32, &xtensa_user_reg_u32_type },
{ "ua_state_3", 0x12, 0, 32, &xtensa_user_reg_u32_type },
{ "q0", 0x13, 0, 128, &xtensa_user_reg_u128_type },
{ "q1", 0x14, 0, 128, &xtensa_user_reg_u128_type },
{ "q2", 0x15, 0, 128, &xtensa_user_reg_u128_type },
{ "q3", 0x16, 0, 128, &xtensa_user_reg_u128_type },
{ "q4", 0x17, 0, 128, &xtensa_user_reg_u128_type },
{ "q5", 0x18, 0, 128, &xtensa_user_reg_u128_type },
{ "q6", 0x19, 0, 128, &xtensa_user_reg_u128_type },
{ "q7", 0x20, 0, 128, &xtensa_user_reg_u128_type },
};
struct esp32s3_common {
struct esp_xtensa_smp_common esp_xtensa_smp;
};
static int esp32s3_fetch_user_regs(struct target *target);
static int esp32s3_queue_write_dirty_user_regs(struct target *target);
static const struct xtensa_config esp32s3_xtensa_cfg = {
.density = true,
.aregs_num = XT_AREGS_NUM_MAX,
.windowed = true,
.coproc = true,
.fp_coproc = true,
.loop = true,
.miscregs_num = 4,
.threadptr = true,
.boolean = true,
.reloc_vec = true,
.proc_id = true,
.cond_store = true,
.mac16 = true,
.user_regs_num = ARRAY_SIZE(esp32s3_user_regs),
.user_regs = esp32s3_user_regs,
.fetch_user_regs = esp32s3_fetch_user_regs,
.queue_write_dirty_user_regs = esp32s3_queue_write_dirty_user_regs,
.gdb_general_regs_num = ESP32_S3_NUM_REGS_G_COMMAND,
.gdb_regs_mapping = esp32s3_gdb_regs_mapping,
.irom = {
.count = 2,
.regions = {
{
.base = ESP32_S3_IROM_LOW,
.size = ESP32_S3_IROM_HIGH - ESP32_S3_IROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
{
.base = ESP32_S3_IROM_MASK_LOW,
.size = ESP32_S3_IROM_MASK_HIGH - ESP32_S3_IROM_MASK_LOW,
.access = XT_MEM_ACCESS_READ,
}
}
},
.iram = {
.count = 2,
.regions = {
{
.base = ESP32_S3_IRAM_LOW,
.size = ESP32_S3_IRAM_HIGH - ESP32_S3_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_RTC_IRAM_LOW,
.size = ESP32_S3_RTC_IRAM_HIGH - ESP32_S3_RTC_IRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.drom = {
.count = 1,
.regions = {
{
.base = ESP32_S3_DROM_LOW,
.size = ESP32_S3_DROM_HIGH - ESP32_S3_DROM_LOW,
.access = XT_MEM_ACCESS_READ,
},
}
},
.dram = {
.count = 4,
.regions = {
{
.base = ESP32_S3_DRAM_LOW,
.size = ESP32_S3_DRAM_HIGH - ESP32_S3_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_RTC_DRAM_LOW,
.size = ESP32_S3_RTC_DRAM_HIGH - ESP32_S3_RTC_DRAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_RTC_DATA_LOW,
.size = ESP32_S3_RTC_DATA_HIGH - ESP32_S3_RTC_DATA_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
{
.base = ESP32_S3_SYS_RAM_LOW,
.size = ESP32_S3_SYS_RAM_HIGH - ESP32_S3_SYS_RAM_LOW,
.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
},
}
},
.exc = {
.enabled = true,
},
.irq = {
.enabled = true,
.irq_num = 32,
},
.high_irq = {
.enabled = true,
.excm_level = 3,
.nmi_num = 1,
},
.tim_irq = {
.enabled = true,
.comp_num = 3,
},
.debug = {
.enabled = true,
.irq_level = 6,
.ibreaks_num = 2,
.dbreaks_num = 2,
.icount_sz = 32,
},
.trace = {
.enabled = true,
.mem_sz = ESP32_S3_TRACEMEM_BLOCK_SZ,
},
};
static int esp32s3_fetch_user_regs(struct target *target)
{
LOG_DEBUG("%s: user regs fetching is not implemented!", target_name(target));
return ERROR_OK;
}
static int esp32s3_queue_write_dirty_user_regs(struct target *target)
{
LOG_DEBUG("%s: user regs writing is not implemented!", target_name(target));
return ERROR_OK;
}
/* Reset ESP32-S3's peripherals.
* 1. OpenOCD makes sure the target is halted; if not, tries to halt it.
* If that fails, tries to reset it (via OCD) and then halt.
@@ -537,7 +300,6 @@ static int esp32s3_virt2phys(struct target *target,
return ERROR_FAIL;
}
static int esp32s3_target_init(struct command_context *cmd_ctx, struct target *target)
{
return esp_xtensa_target_init(cmd_ctx, target);
@@ -577,7 +339,6 @@ static int esp32s3_target_create(struct target *target, Jim_Interp *interp)
int ret = esp_xtensa_smp_init_arch_info(target,
&esp32s3->esp_xtensa_smp,
&esp32s3_xtensa_cfg,
&esp32s3_dm_cfg,
&esp32s3_chip_ops);
if (ret != ERROR_OK) {

54
src/target/espressif/esp32s3.h
View File

@@ -1,54 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* ESP32-S3 target for OpenOCD *
* Copyright (C) 2020 Espressif Systems Ltd. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32S3_H
#define OPENOCD_TARGET_ESP32S3_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_S3_DROM_LOW 0x3C000000
#define ESP32_S3_DROM_HIGH 0x3D000000
#define ESP32_S3_IROM_LOW 0x42000000
#define ESP32_S3_IROM_HIGH 0x44000000
/*Number of registers returned directly by the G command
*Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_S3_NUM_REGS_G_COMMAND 128
enum esp32s3_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
ESP32_S3_REG_IDX_ACCX_0,
ESP32_S3_REG_IDX_ACCX_1,
ESP32_S3_REG_IDX_QACC_H_0,
ESP32_S3_REG_IDX_QACC_H_1,
ESP32_S3_REG_IDX_QACC_H_2,
ESP32_S3_REG_IDX_QACC_H_3,
ESP32_S3_REG_IDX_QACC_H_4,
ESP32_S3_REG_IDX_QACC_L_0,
ESP32_S3_REG_IDX_QACC_L_1,
ESP32_S3_REG_IDX_QACC_L_2,
ESP32_S3_REG_IDX_QACC_L_3,
ESP32_S3_REG_IDX_QACC_L_4,
ESP32_S3_REG_IDX_SAR_BYTE,
ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
ESP32_S3_REG_IDX_UA_STATE_0,
ESP32_S3_REG_IDX_UA_STATE_1,
ESP32_S3_REG_IDX_UA_STATE_2,
ESP32_S3_REG_IDX_UA_STATE_3,
ESP32_S3_REG_IDX_Q0,
ESP32_S3_REG_IDX_Q1,
ESP32_S3_REG_IDX_Q2,
ESP32_S3_REG_IDX_Q3,
ESP32_S3_REG_IDX_Q4,
ESP32_S3_REG_IDX_Q5,
ESP32_S3_REG_IDX_Q6,
ESP32_S3_REG_IDX_Q7,
ESP32_S3_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32S3_H */

3
src/target/espressif/esp_xtensa.c
View File

@@ -17,10 +17,9 @@
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg)
{
return xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg);
return xtensa_init_arch_info(target, &esp_xtensa->xtensa, dm_cfg);
}
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target)

1
src/target/espressif/esp_xtensa.h
View File

@@ -23,7 +23,6 @@ static inline struct esp_xtensa_common *target_to_esp_xtensa(struct target *targ
int esp_xtensa_init_arch_info(struct target *target,
struct esp_xtensa_common *esp_xtensa,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg);
int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
void esp_xtensa_target_deinit(struct target *target);

192
src/target/espressif/esp_xtensa_smp.c
View File

@@ -450,11 +450,10 @@ int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *w
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops)
{
int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg);
int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, dm_cfg);
if (ret != ERROR_OK)
return ret;
esp_xtensa_smp->chip_ops = chip_ops;
@@ -467,6 +466,139 @@ int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *t
return esp_xtensa_target_init(cmd_ctx, target);
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt)
{
struct target *target = get_current_target(CMD_CTX);
if (target->smp && CMD_ARGC > 0) {
struct target_list *head;
struct target *curr;
foreach_smp_target(head, target->smp_targets) {
curr = head->target;
int ret = CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
target_to_xtensa(curr));
if (ret != ERROR_OK)
return ret;
}
return ERROR_OK;
}
return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do,
target_to_xtensa(target));
}
COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode)
{
struct target *target = get_current_target(CMD_CTX);
@@ -632,6 +764,62 @@ COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump)
}
const struct command_registration esp_xtensa_smp_xtensa_command_handlers[] = {
{
.name = "xtdef",
.handler = esp_xtensa_smp_cmd_xtdef,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa core type",
.usage = "<type>",
},
{
.name = "xtopt",
.handler = esp_xtensa_smp_cmd_xtopt,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa core option",
.usage = "<name> <value>",
},
{
.name = "xtmem",
.handler = esp_xtensa_smp_cmd_xtmem,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa memory/cache option",
.usage = "<type> [parameters]",
},
{
.name = "xtmmu",
.handler = esp_xtensa_smp_cmd_xtmmu,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa MMU option",
.usage = "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>",
},
{
.name = "xtmpu",
.handler = esp_xtensa_smp_cmd_xtmpu,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa MPU option",
.usage = "<num FG seg> <min seg size> <lockable> <executeonly>",
},
{
.name = "xtreg",
.handler = esp_xtensa_smp_cmd_xtreg,
.mode = COMMAND_CONFIG,
.help = "Configure Xtensa register",
.usage = "<regname> <regnum>",
},
{
.name = "xtregs",
.handler = esp_xtensa_smp_cmd_xtreg,
.mode = COMMAND_CONFIG,
.help = "Configure number of Xtensa registers",
.usage = "<numregs>",
},
{
.name = "xtregfmt",
.handler = esp_xtensa_smp_cmd_xtregfmt,
.mode = COMMAND_CONFIG,
.help = "Configure format of Xtensa register map",
.usage = "<numgregs>",
},
{
.name = "set_permissive",
.handler = esp_xtensa_smp_cmd_permissive_mode,

1
src/target/espressif/esp_xtensa_smp.h
View File

@@ -43,7 +43,6 @@ int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target);
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops);