target: add generic Xtensa LX support
Generic Xtensa LX support extends the original Espressif/Xtensa patch-set to support arbitrary Xtensa configurations, as defined in a core-specific .cfg file. Not yet fully-featured. Additional functionality to be added: - Xtensa NX support - DAP/SWD support - File-IO support - Generic Xtensa multi-core support Valgrind-clean, no new Clang analyzer warnings Signed-off-by: Ian Thompson <ianst@cadence.com> Change-Id: I08e7bf8fa57c25b5d0cb75a1aa7a2ac13a380c52 Reviewed-on: https://review.openocd.org/c/openocd/+/7055 Tested-by: jenkins Reviewed-by: Erhan Kurubas <erhan.kurubas@espressif.com> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Ian Thompson
committed by
Antonio Borneo
Antonio Borneo
parent
be2e5c6c35
commit
ce5ca9f7ba
@@ -14,7 +14,6 @@
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#include <target/target_type.h>
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#include <target/smp.h>
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#include "assert.h"
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#include "esp32.h"
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#include "esp_xtensa_smp.h"
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/*
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@@ -70,204 +69,6 @@ implementation.
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#define ESP32_RTC_CNTL_SW_CPU_STALL_REG (ESP32_RTCCNTL_BASE + 0xac)
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#define ESP32_RTC_CNTL_SW_CPU_STALL_DEF 0x0
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/* this should map local reg IDs to GDB reg mapping as defined in xtensa-config.c 'rmap' in
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*xtensa-overlay */
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static const unsigned int esp32_gdb_regs_mapping[ESP32_NUM_REGS] = {
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XT_REG_IDX_PC,
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XT_REG_IDX_AR0, XT_REG_IDX_AR1, XT_REG_IDX_AR2, XT_REG_IDX_AR3,
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XT_REG_IDX_AR4, XT_REG_IDX_AR5, XT_REG_IDX_AR6, XT_REG_IDX_AR7,
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XT_REG_IDX_AR8, XT_REG_IDX_AR9, XT_REG_IDX_AR10, XT_REG_IDX_AR11,
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XT_REG_IDX_AR12, XT_REG_IDX_AR13, XT_REG_IDX_AR14, XT_REG_IDX_AR15,
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XT_REG_IDX_AR16, XT_REG_IDX_AR17, XT_REG_IDX_AR18, XT_REG_IDX_AR19,
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XT_REG_IDX_AR20, XT_REG_IDX_AR21, XT_REG_IDX_AR22, XT_REG_IDX_AR23,
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XT_REG_IDX_AR24, XT_REG_IDX_AR25, XT_REG_IDX_AR26, XT_REG_IDX_AR27,
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XT_REG_IDX_AR28, XT_REG_IDX_AR29, XT_REG_IDX_AR30, XT_REG_IDX_AR31,
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XT_REG_IDX_AR32, XT_REG_IDX_AR33, XT_REG_IDX_AR34, XT_REG_IDX_AR35,
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XT_REG_IDX_AR36, XT_REG_IDX_AR37, XT_REG_IDX_AR38, XT_REG_IDX_AR39,
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XT_REG_IDX_AR40, XT_REG_IDX_AR41, XT_REG_IDX_AR42, XT_REG_IDX_AR43,
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XT_REG_IDX_AR44, XT_REG_IDX_AR45, XT_REG_IDX_AR46, XT_REG_IDX_AR47,
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XT_REG_IDX_AR48, XT_REG_IDX_AR49, XT_REG_IDX_AR50, XT_REG_IDX_AR51,
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XT_REG_IDX_AR52, XT_REG_IDX_AR53, XT_REG_IDX_AR54, XT_REG_IDX_AR55,
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XT_REG_IDX_AR56, XT_REG_IDX_AR57, XT_REG_IDX_AR58, XT_REG_IDX_AR59,
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XT_REG_IDX_AR60, XT_REG_IDX_AR61, XT_REG_IDX_AR62, XT_REG_IDX_AR63,
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XT_REG_IDX_LBEG, XT_REG_IDX_LEND, XT_REG_IDX_LCOUNT, XT_REG_IDX_SAR,
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XT_REG_IDX_WINDOWBASE, XT_REG_IDX_WINDOWSTART, XT_REG_IDX_CONFIGID0, XT_REG_IDX_CONFIGID1,
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XT_REG_IDX_PS, XT_REG_IDX_THREADPTR, XT_REG_IDX_BR, XT_REG_IDX_SCOMPARE1,
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XT_REG_IDX_ACCLO, XT_REG_IDX_ACCHI,
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XT_REG_IDX_M0, XT_REG_IDX_M1, XT_REG_IDX_M2, XT_REG_IDX_M3,
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ESP32_REG_IDX_EXPSTATE,
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ESP32_REG_IDX_F64R_LO,
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ESP32_REG_IDX_F64R_HI,
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ESP32_REG_IDX_F64S,
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XT_REG_IDX_F0, XT_REG_IDX_F1, XT_REG_IDX_F2, XT_REG_IDX_F3,
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XT_REG_IDX_F4, XT_REG_IDX_F5, XT_REG_IDX_F6, XT_REG_IDX_F7,
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XT_REG_IDX_F8, XT_REG_IDX_F9, XT_REG_IDX_F10, XT_REG_IDX_F11,
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XT_REG_IDX_F12, XT_REG_IDX_F13, XT_REG_IDX_F14, XT_REG_IDX_F15,
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XT_REG_IDX_FCR, XT_REG_IDX_FSR, XT_REG_IDX_MMID, XT_REG_IDX_IBREAKENABLE,
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XT_REG_IDX_MEMCTL, XT_REG_IDX_ATOMCTL, XT_REG_IDX_OCD_DDR,
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XT_REG_IDX_IBREAKA0, XT_REG_IDX_IBREAKA1, XT_REG_IDX_DBREAKA0, XT_REG_IDX_DBREAKA1,
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XT_REG_IDX_DBREAKC0, XT_REG_IDX_DBREAKC1,
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XT_REG_IDX_EPC1, XT_REG_IDX_EPC2, XT_REG_IDX_EPC3, XT_REG_IDX_EPC4,
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XT_REG_IDX_EPC5, XT_REG_IDX_EPC6, XT_REG_IDX_EPC7, XT_REG_IDX_DEPC,
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XT_REG_IDX_EPS2, XT_REG_IDX_EPS3, XT_REG_IDX_EPS4, XT_REG_IDX_EPS5,
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XT_REG_IDX_EPS6, XT_REG_IDX_EPS7,
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XT_REG_IDX_EXCSAVE1, XT_REG_IDX_EXCSAVE2, XT_REG_IDX_EXCSAVE3, XT_REG_IDX_EXCSAVE4,
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XT_REG_IDX_EXCSAVE5, XT_REG_IDX_EXCSAVE6, XT_REG_IDX_EXCSAVE7, XT_REG_IDX_CPENABLE,
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XT_REG_IDX_INTERRUPT, XT_REG_IDX_INTSET, XT_REG_IDX_INTCLEAR, XT_REG_IDX_INTENABLE,
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XT_REG_IDX_VECBASE, XT_REG_IDX_EXCCAUSE, XT_REG_IDX_DEBUGCAUSE, XT_REG_IDX_CCOUNT,
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XT_REG_IDX_PRID, XT_REG_IDX_ICOUNT, XT_REG_IDX_ICOUNTLEVEL, XT_REG_IDX_EXCVADDR,
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XT_REG_IDX_CCOMPARE0, XT_REG_IDX_CCOMPARE1, XT_REG_IDX_CCOMPARE2,
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XT_REG_IDX_MISC0, XT_REG_IDX_MISC1, XT_REG_IDX_MISC2, XT_REG_IDX_MISC3,
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XT_REG_IDX_A0, XT_REG_IDX_A1, XT_REG_IDX_A2, XT_REG_IDX_A3,
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XT_REG_IDX_A4, XT_REG_IDX_A5, XT_REG_IDX_A6, XT_REG_IDX_A7,
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XT_REG_IDX_A8, XT_REG_IDX_A9, XT_REG_IDX_A10, XT_REG_IDX_A11,
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XT_REG_IDX_A12, XT_REG_IDX_A13, XT_REG_IDX_A14, XT_REG_IDX_A15,
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XT_REG_IDX_PWRCTL, XT_REG_IDX_PWRSTAT, XT_REG_IDX_ERISTAT,
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XT_REG_IDX_CS_ITCTRL, XT_REG_IDX_CS_CLAIMSET, XT_REG_IDX_CS_CLAIMCLR,
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XT_REG_IDX_CS_LOCKACCESS, XT_REG_IDX_CS_LOCKSTATUS, XT_REG_IDX_CS_AUTHSTATUS,
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XT_REG_IDX_FAULT_INFO,
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XT_REG_IDX_TRAX_ID, XT_REG_IDX_TRAX_CTRL, XT_REG_IDX_TRAX_STAT,
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XT_REG_IDX_TRAX_DATA, XT_REG_IDX_TRAX_ADDR, XT_REG_IDX_TRAX_PCTRIGGER,
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XT_REG_IDX_TRAX_PCMATCH, XT_REG_IDX_TRAX_DELAY, XT_REG_IDX_TRAX_MEMSTART,
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XT_REG_IDX_TRAX_MEMEND,
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XT_REG_IDX_PMG, XT_REG_IDX_PMPC, XT_REG_IDX_PM0, XT_REG_IDX_PM1,
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XT_REG_IDX_PMCTRL0, XT_REG_IDX_PMCTRL1, XT_REG_IDX_PMSTAT0, XT_REG_IDX_PMSTAT1,
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XT_REG_IDX_OCD_ID, XT_REG_IDX_OCD_DCRCLR, XT_REG_IDX_OCD_DCRSET, XT_REG_IDX_OCD_DSR,
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};
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static const struct xtensa_user_reg_desc esp32_user_regs[ESP32_NUM_REGS - XT_NUM_REGS] = {
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{ "expstate", 0xE6, 0, 32, &xtensa_user_reg_u32_type },
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{ "f64r_lo", 0xEA, 0, 32, &xtensa_user_reg_u32_type },
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{ "f64r_hi", 0xEB, 0, 32, &xtensa_user_reg_u32_type },
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{ "f64s", 0xEC, 0, 32, &xtensa_user_reg_u32_type },
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};
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static const struct xtensa_config esp32_xtensa_cfg = {
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.density = true,
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.aregs_num = XT_AREGS_NUM_MAX,
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.windowed = true,
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.coproc = true,
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.fp_coproc = true,
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.loop = true,
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.miscregs_num = 4,
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.threadptr = true,
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.boolean = true,
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.reloc_vec = true,
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.proc_id = true,
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.cond_store = true,
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.mac16 = true,
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.user_regs_num = ARRAY_SIZE(esp32_user_regs),
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.user_regs = esp32_user_regs,
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.fetch_user_regs = xtensa_fetch_user_regs_u32,
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.queue_write_dirty_user_regs = xtensa_queue_write_dirty_user_regs_u32,
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.gdb_general_regs_num = ESP32_NUM_REGS_G_COMMAND,
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.gdb_regs_mapping = esp32_gdb_regs_mapping,
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.irom = {
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.count = 2,
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.regions = {
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{
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.base = ESP32_IROM_LOW,
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.size = ESP32_IROM_HIGH - ESP32_IROM_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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{
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.base = ESP32_IROM_MASK_LOW,
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.size = ESP32_IROM_MASK_HIGH - ESP32_IROM_MASK_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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}
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},
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.iram = {
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.count = 2,
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.regions = {
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{
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.base = ESP32_IRAM_LOW,
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.size = ESP32_IRAM_HIGH - ESP32_IRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_RTC_IRAM_LOW,
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.size = ESP32_RTC_IRAM_HIGH - ESP32_RTC_IRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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}
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},
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.drom = {
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.count = 1,
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.regions = {
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{
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.base = ESP32_DROM_LOW,
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.size = ESP32_DROM_HIGH - ESP32_DROM_LOW,
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.access = XT_MEM_ACCESS_READ,
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},
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}
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},
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.dram = {
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.count = 6,
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.regions = {
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{
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.base = ESP32_DRAM_LOW,
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.size = ESP32_DRAM_HIGH - ESP32_DRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_RTC_DRAM_LOW,
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.size = ESP32_RTC_DRAM_HIGH - ESP32_RTC_DRAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_RTC_DATA_LOW,
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.size = ESP32_RTC_DATA_HIGH - ESP32_RTC_DATA_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_EXTRAM_DATA_LOW,
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.size = ESP32_EXTRAM_DATA_HIGH - ESP32_EXTRAM_DATA_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_DR_REG_LOW,
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.size = ESP32_DR_REG_HIGH - ESP32_DR_REG_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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{
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.base = ESP32_SYS_RAM_LOW,
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.size = ESP32_SYS_RAM_HIGH - ESP32_SYS_RAM_LOW,
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.access = XT_MEM_ACCESS_READ | XT_MEM_ACCESS_WRITE,
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},
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}
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},
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.exc = {
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.enabled = true,
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},
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.irq = {
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.enabled = true,
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.irq_num = 32,
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},
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.high_irq = {
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.enabled = true,
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.excm_level = 3,
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.nmi_num = 1,
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},
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.tim_irq = {
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.enabled = true,
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.comp_num = 3,
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},
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.debug = {
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.enabled = true,
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.irq_level = 6,
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.ibreaks_num = 2,
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.dbreaks_num = 2,
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.icount_sz = 32,
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},
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.trace = {
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.enabled = true,
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.mem_sz = ESP32_TRACEMEM_BLOCK_SZ,
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.reversed_mem_access = true,
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},
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};
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/* 0 - don't care, 1 - TMS low, 2 - TMS high */
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enum esp32_flash_bootstrap {
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FBS_DONTCARE = 0,
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@@ -401,7 +202,8 @@ static int esp32_soc_reset(struct target *target)
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alive_sleep(10);
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xtensa_poll(target);
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if (timeval_ms() >= timeout) {
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LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d", target->state);
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LOG_TARGET_ERROR(target, "Timed out waiting for CPU to be reset, target state=%d",
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target->state);
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get_timeout = true;
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break;
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}
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@@ -481,7 +283,6 @@ static int esp32_virt2phys(struct target *target,
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return ERROR_FAIL;
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}
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/* The TDI pin is also used as a flash Vcc bootstrap pin. If we reset the CPU externally, the last state of the TDI pin
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* can allow the power to an 1.8V flash chip to be raised to 3.3V, or the other way around. Users can use the
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* esp32 flashbootstrap command to set a level, and this routine will make sure the tdi line will return to
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@@ -544,7 +345,7 @@ static int esp32_target_create(struct target *target, Jim_Interp *interp)
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return ERROR_FAIL;
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}
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int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp, &esp32_xtensa_cfg,
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int ret = esp_xtensa_smp_init_arch_info(target, &esp32->esp_xtensa_smp,
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&esp32_dm_cfg, &esp32_chip_ops);
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if (ret != ERROR_OK) {
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LOG_ERROR("Failed to init arch info!");
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