contrib/firmware/angie: add new spartan6 VHDL code

This new code implement two FIFOs for handling TX and RX
JTAG data transfers, its simply receives data and send it
OUT to target chip in respect of JTAG protocol timing
constraints.
The IN FIFO receives data from target chip and send it
back to openocd.

Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e
Signed-off-by: Ahmed BOUDJELIDA <aboudjelida@nanoxplore.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8715
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

contrib/firmware/angie/hdl/src/dff.vhd

@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_arith.ALL;
+use ieee.std_logic_unsigned.ALL;
+
+entity DFF is
+port (  clk : in std_logic;
+        reset : in std_logic;
+        d : in std_logic;
+        q : out std_logic);
+end DFF;
+
+architecture Behavioral of DFF is
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            q <= '1'; -- Reset output to 0
+        elsif rising_edge(clk) then
+            q <= d; -- Capture D at the rising edge of the clock
+        end if;
+    end process;
+end Behavioral;