aice: add Andes AICE support
Andes AICE uses USB to transfer packets between OpenOCD and AICE. It uses high-level USB commands to control targets instead of using JTAG signals. I define an interface as aice_port_api_s. It contains all basic operations needed by target-dependent code. Change-Id: I117bc4f938fab2732e44c509ea68b30172d6fdb9 Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-on: http://openocd.zylin.com/1256 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Hsiangkai Wang
committed by
Spencer Oliver
Spencer Oliver
parent
8890ce3469
commit
ceb402dc9e
432
src/target/nds32.h
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432
src/target/nds32.h
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/***************************************************************************
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* Copyright (C) 2013 by Andes Technology *
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* Hsiangkai Wang <hkwang@andestech.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
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***************************************************************************/
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#ifndef __NDS32_H__
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#define __NDS32_H__
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#include <jtag/jtag.h>
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#include <jtag/aice/aice_port.h>
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#include "target.h"
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#include "target_type.h"
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#include "register.h"
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#include "breakpoints.h"
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#include "nds32_reg.h"
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#include "nds32_insn.h"
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#include "nds32_edm.h"
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#define CHECK_RETVAL(action) \
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do { \
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int __retval = (action); \
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if (__retval != ERROR_OK) { \
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LOG_DEBUG("error while calling \"%s\"", \
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# action); \
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return __retval; \
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} \
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} while (0)
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/**
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* @file
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* Holds the interface to Andes cores.
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*/
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extern const char *nds32_debug_type_name[11];
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enum nds32_debug_reason {
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NDS32_DEBUG_BREAK = 0,
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NDS32_DEBUG_BREAK_16,
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NDS32_DEBUG_INST_BREAK,
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NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE,
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NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE,
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NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE,
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NDS32_DEBUG_DEBUG_INTERRUPT,
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NDS32_DEBUG_HARDWARE_SINGLE_STEP,
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NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE,
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NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE,
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NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP,
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};
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enum nds32_tdesc_type {
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NDS32_CORE_TDESC = 0,
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NDS32_SYSTEM_TDESC,
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NDS32_AUDIO_TDESC,
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NDS32_FPU_TDESC,
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NDS32_NUM_TDESC,
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};
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#define NDS32_STRUCT_STAT_SIZE 60
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#define NDS32_STRUCT_TIMEVAL_SIZE 8
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enum nds32_syscall_id {
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NDS32_SYSCALL_EXIT = 1,
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NDS32_SYSCALL_OPEN = 2,
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NDS32_SYSCALL_CLOSE = 3,
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NDS32_SYSCALL_READ = 4,
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NDS32_SYSCALL_WRITE = 5,
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NDS32_SYSCALL_LSEEK = 6,
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NDS32_SYSCALL_UNLINK = 7,
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NDS32_SYSCALL_RENAME = 3001,
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NDS32_SYSCALL_FSTAT = 10,
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NDS32_SYSCALL_STAT = 15,
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NDS32_SYSCALL_GETTIMEOFDAY = 19,
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NDS32_SYSCALL_ISATTY = 3002,
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NDS32_SYSCALL_SYSTEM = 3003,
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NDS32_SYSCALL_ERRNO = 6001,
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};
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#define NDS32_COMMON_MAGIC (int)0xADE5ADE5
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struct nds32_edm {
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/** EDM_CFG.VER, indicate the EDM version */
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int version;
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/** The number of hardware breakpoints */
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int breakpoint_num;
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/** EDM_CFG.DALM, indicate if direct local memory access feature is supported or not */
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bool direct_access_local_memory;
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/** Support ACC_CTL register */
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bool access_control;
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/** */
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bool support_max_stop;
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};
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struct nds32_cache {
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/** enable cache or not */
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bool enable;
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/** cache sets per way */
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int set;
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/** cache ways */
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int way;
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/** cache line size */
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int line_size;
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/** cache locking support */
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bool lock_support;
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};
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struct nds32_memory {
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/** ICache */
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struct nds32_cache icache;
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/** DCache */
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struct nds32_cache dcache;
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/** On-chip instruction local memory base */
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int ilm_base;
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/** On-chip instruction local memory size */
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int ilm_size;
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/** ILM base register alignment version */
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int ilm_align_ver;
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/** DLM is enabled or not */
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bool ilm_enable;
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/** DLM start address */
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int ilm_start;
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/** DLM end address */
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int ilm_end;
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/** On-chip data local memory base */
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int dlm_base;
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/** On-chip data local memory size */
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int dlm_size;
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/** DLM base register alignment version */
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int dlm_align_ver;
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/** DLM is enabled or not */
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bool dlm_enable;
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/** DLM start address */
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int dlm_start;
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/** DLM end address */
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int dlm_end;
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/** Memory access method */
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enum aice_memory_access access_channel;
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/** Memory access mode */
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enum aice_memory_mode mode;
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/** Address translation */
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bool address_translation;
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};
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struct nds32_cpu_version {
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bool performance_extension;
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bool _16bit_extension;
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bool performance_extension_2;
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bool cop_fpu_extension;
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bool string_extension;
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int revision;
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int cpu_id_family;
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int cpu_id_version;
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};
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struct nds32_mmu_config {
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int memory_protection;
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int memory_protection_version;
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bool fully_associative_tlb;
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int tlb_size;
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int tlb_ways;
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int tlb_sets;
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bool _8k_page_support;
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int extra_page_size_support;
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bool tlb_lock;
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bool hardware_page_table_walker;
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bool default_endian;
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int partition_num;
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bool invisible_tlb;
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bool vlpt;
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bool ntme;
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bool drde;
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int default_min_page_size;
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bool multiple_page_size_in_use;
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};
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struct nds32_misc_config {
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bool edm;
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bool local_memory_dma;
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bool performance_monitor;
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bool high_speed_memory_port;
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bool debug_tracer;
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bool div_instruction;
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bool mac_instruction;
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int audio_isa;
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bool L2_cache;
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bool reduce_register;
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bool addr_24;
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bool interruption_level;
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int baseline_instruction;
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bool no_dx_register;
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bool implement_dependant_register;
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bool implement_dependant_sr_encoding;
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bool ifc;
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bool mcu;
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bool ex9;
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int shadow;
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};
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/**
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* Represents a generic Andes core.
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*/
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struct nds32 {
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int common_magic;
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struct reg_cache *core_cache;
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/** Handle for the debug module. */
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struct nds32_edm edm;
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/** Memory information */
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struct nds32_memory memory;
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/** cpu version */
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struct nds32_cpu_version cpu_version;
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/** MMU configuration */
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struct nds32_mmu_config mmu_config;
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/** Misc configuration */
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struct nds32_misc_config misc_config;
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/** Retrieve all core registers, for display. */
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int (*full_context)(struct nds32 *nds32);
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/** Register mappings */
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int (*register_map)(struct nds32 *nds32, int reg_no);
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/** Get debug exception virtual address */
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int (*get_debug_reason)(struct nds32 *nds32, uint32_t *reason);
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/** Restore target registers may be modified in debug state */
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int (*leave_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
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/** Backup target registers may be modified in debug state */
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int (*enter_debug_state)(struct nds32 *nds32, bool enable_watchpoint);
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/** Get address hitted watchpoint */
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int (*get_watched_address)(struct nds32 *nds32, uint32_t *address, uint32_t reason);
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/** maximum interrupt level */
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uint32_t max_interrupt_level;
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/** current interrupt level */
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uint32_t current_interrupt_level;
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uint32_t watched_address;
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/** Flag reporting whether virtual hosting is active. */
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bool virtual_hosting;
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/** Flag reporting whether continue/step hits syscall or not */
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bool hit_syscall;
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/** Value to be returned by virtual hosting SYS_ERRNO request. */
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int virtual_hosting_errno;
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/** Flag reporting whether syscall is aborted */
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bool virtual_hosting_ctrl_c;
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/** Record syscall ID for other operations to do special processing for target */
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int active_syscall_id;
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/** Flag reporting whether global stop is active. */
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bool global_stop;
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/** reset-halt as target examine */
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bool reset_halt_as_examine;
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/** Period to wait after SRST. */
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uint32_t boot_time;
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/** Flag to indicate HSS steps into ISR or not */
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bool step_isr_enable;
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/** Flag to indicate register table is ready or not */
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bool init_arch_info_after_halted;
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/** Flag to indicate audio-extension is enabled or not */
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bool audio_enable;
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/** Flag to indicate fpu-extension is enabled or not */
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bool fpu_enable;
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/** Flag to indicate if auto convert software breakpoints to
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* hardware breakpoints or not in ROM */
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bool auto_convert_hw_bp;
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int (*setup_virtual_hosting)(struct target *target, int enable);
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/** Backpointer to the target. */
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struct target *target;
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void *arch_info;
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};
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struct nds32_reg {
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uint32_t num;
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uint32_t value;
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uint64_t value_64;
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struct target *target;
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struct nds32 *nds32;
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bool enable;
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};
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extern int nds32_config(struct nds32 *nds32);
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extern int nds32_init_arch_info(struct target *target, struct nds32 *nds32);
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extern int nds32_full_context(struct nds32 *nds32);
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extern int nds32_arch_state(struct target *target);
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extern int nds32_add_software_breakpoint(struct target *target,
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struct breakpoint *breakpoint);
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extern int nds32_remove_software_breakpoint(struct target *target,
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struct breakpoint *breakpoint);
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extern int nds32_get_gdb_general_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size);
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extern int nds32_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size);
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extern int nds32_get_gdb_target_description(struct target *target, char **xml,
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char *annex, int32_t offset, uint32_t length);
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extern int nds32_write_buffer(struct target *target, uint32_t address,
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uint32_t size, const uint8_t *buffer);
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extern int nds32_read_buffer(struct target *target, uint32_t address,
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uint32_t size, uint8_t *buffer);
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extern int nds32_bulk_write_memory(struct target *target,
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uint32_t address, uint32_t count, const uint8_t *buffer);
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extern int nds32_read_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer);
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extern int nds32_write_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer);
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extern int nds32_init_register_table(struct nds32 *nds32);
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extern int nds32_init_memory_info(struct nds32 *nds32);
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extern int nds32_restore_context(struct target *target);
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extern int nds32_get_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t *value);
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extern int nds32_set_mapped_reg(struct nds32 *nds32, unsigned regnum, uint32_t value);
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extern int nds32_edm_config(struct nds32 *nds32);
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extern int nds32_check_extension(struct nds32 *nds32);
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extern int nds32_cache_sync(struct target *target, uint32_t address, uint32_t length);
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extern int nds32_mmu(struct target *target, int *enabled);
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extern int nds32_virtual_to_physical(struct target *target, uint32_t address, uint32_t *physical);
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extern int nds32_read_phys_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, uint8_t *buffer);
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extern int nds32_write_phys_memory(struct target *target, uint32_t address,
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uint32_t size, uint32_t count, const uint8_t *buffer);
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extern int nds32_soft_reset_halt(struct target *target);
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extern uint32_t nds32_nextpc(struct nds32 *nds32, int current, uint32_t address);
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extern int nds32_examine_debug_reason(struct nds32 *nds32);
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extern int nds32_step(struct target *target, int current,
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uint32_t address, int handle_breakpoints);
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extern int nds32_target_state(struct nds32 *nds32, enum target_state *state);
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extern int nds32_halt(struct target *target);
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extern int nds32_poll(struct target *target);
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extern int nds32_resume(struct target *target, int current,
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uint32_t address, int handle_breakpoints, int debug_execution);
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extern int nds32_assert_reset(struct target *target);
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extern int nds32_init(struct nds32 *nds32);
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extern int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fileio_info);
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extern int nds32_gdb_fileio_write_memory(struct nds32 *nds32, uint32_t address,
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uint32_t size, const uint8_t *buffer);
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extern int nds32_gdb_fileio_end(struct target *target, int retcode, int fileio_errno, bool ctrl_c);
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extern int nds32_reset_halt(struct nds32 *nds32);
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/** Convert target handle to generic Andes target state handle. */
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static inline struct nds32 *target_to_nds32(struct target *target)
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{
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assert(target != NULL);
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return target->arch_info;
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}
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/** */
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static inline struct aice_port_s *target_to_aice(struct target *target)
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{
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assert(target != NULL);
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return target->tap->priv;
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}
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static inline bool is_nds32(struct nds32 *nds32)
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{
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assert(nds32 != NULL);
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return nds32->common_magic == NDS32_COMMON_MAGIC;
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}
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static inline bool nds32_reach_max_interrupt_level(struct nds32 *nds32)
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{
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assert(nds32 != NULL);
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return nds32->max_interrupt_level == nds32->current_interrupt_level;
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}
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#endif /* __NDS32_H__ */
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