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nds32: add new target type nds32_v2, nds32_v3, nds32_v3m

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Add target code for Andes targets.

Change-Id: Ibf0e1b61b06127ca7d9ed502d98d7e2aeebbbe82
Signed-off-by: Hsiangkai Wang <hsiangkai@gmail.com>
Reviewed-on: http://openocd.zylin.com/1259
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Hsiangkai Wang
2013-02-05 11:55:37 +08:00
committed by Spencer Oliver
parent ceb402dc9e
commit cf8a3c3d70
28 changed files with 10128 additions and 94 deletions
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30
src/target/nds32_reg.h
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@@ -1,5 +1,5 @@
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Copyright (C) 2013 Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
* *
* This program is free software; you can redistribute it and/or modify *
@@ -24,8 +24,7 @@
#define NDS32_REGISTER_DISABLE (0x0)
enum nds32_reg_number_s {
/* general registers */
R0 = 0,
R0 = 0, /* general registers */
R1,
R2,
R3,
@@ -64,9 +63,7 @@ enum nds32_reg_number_s {
D1HI,
ITB,
IFC_LP,
/* system registers */
CR0,
CR0, /* system registers */
CR1,
CR2,
CR3,
@@ -99,6 +96,11 @@ enum nds32_reg_number_s {
IR23,
IR24,
IR25,
IR26,
IR27,
IR28,
IR29,
IR30,
MR0,
MR1,
MR2,
@@ -180,9 +182,7 @@ enum nds32_reg_number_s {
IDR0,
IDR1,
SECUR0,
/* audio registers */
D0L24,
D0L24, /* audio registers */
D1L24,
I0,
I1,
@@ -214,9 +214,7 @@ enum nds32_reg_number_s {
CBE1,
CBE2,
CBE3,
/* fpu */
FPCSR,
FPCSR, /* fpu */
FPCFG,
FS0,
FS1,
@@ -310,11 +308,19 @@ struct nds32_reg_s {
uint8_t size;
};
struct nds32_reg_exception_s {
uint32_t reg_num;
uint32_t ex_value_bit_pos;
uint32_t ex_value_mask;
uint32_t ex_value;
};
void nds32_reg_init(void);
uint32_t nds32_reg_sr_index(uint32_t number);
enum nds32_reg_type_s nds32_reg_type(uint32_t number);
uint8_t nds32_reg_size(uint32_t number);
const char *nds32_reg_simple_name(uint32_t number);
const char *nds32_reg_symbolic_name(uint32_t number);
bool nds32_reg_exception(uint32_t number, uint32_t value);
#endif