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ARM11: minor cleanup, mostly ITR comments

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ITR register handling seemed to be giving me problems, so I updated
the comments to better say what the code is trying to do ... and to
note the preconditions (one of which seems to be an issue) as listed
in the ARM1136 TRM.

Also removed the unused "ARM11_TAP_DEFAULT" from the ITR scan code;
all the callers already specify an exit path, since this register
isn't usable with such vague semantics.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2009-12-11 15:24:08 -08:00
parent 08589462ad
commit cfd79e96a6
2 changed files with 43 additions and 28 deletions
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28
src/target/arm11.c
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@@ -1012,27 +1012,25 @@ static int arm11_write_memory_inner(struct target *target,
}
case 4: {
/* increment: STC p14,c5,[R0],#4 */
/* no increment: STC p14,c5,[R0]*/
uint32_t instr = !no_increment ? 0xeca05e01 : 0xed805e00;
/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
uint32_t *words = (uint32_t*)buffer;
/* "burst" here just means trusting each instruction executes
* fully before we run the next one: per-word roundtrips, to
* check the Ready flag, are not used.
*/
if (!burst)
{
/* STC p14,c5,[R0],#4 */
/* STC p14,c5,[R0]*/
retval = arm11_run_instr_data_to_core(arm11, instr, words, count);
if (retval != ERROR_OK)
return retval;
}
retval = arm11_run_instr_data_to_core(arm11,
instr, words, count);
else
{
/* STC p14,c5,[R0],#4 */
/* STC p14,c5,[R0]*/
retval = arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
if (retval != ERROR_OK)
return retval;
}
retval = arm11_run_instr_data_to_core_noack(arm11,
instr, words, count);
if (retval != ERROR_OK)
return retval;
break;
}
@@ -1309,7 +1307,7 @@ static const struct command_registration arm11_mw_command_handlers[] = {
.name = "burst",
.handler = &arm11_handle_bool_memwrite_burst,
.mode = COMMAND_ANY,
.help = "Enable/Disable non-standard but fast burst mode"
.help = "Enable/Disable potentially risky fast burst mode"
" (default: enabled)",
},
{