armv7a: rework automatic flush-on-write handling

The following changes are implemented:
- Clean&Invalidate the VA range to PoC *before* the write takes place
- Remove SMP handling since DCCIMVA instruction already maintains SMP
  coherence.
- Remove separate Invalidate step

Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3027
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins

src/target/cortex_a.c

@@ -2754,10 +2754,12 @@ static int cortex_a_write_memory(struct target *target, uint32_t address,
 		if (retval != ERROR_OK)
 			return retval;
 	}
-	retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
 
+	/* memory writes bypass the caches, must flush before writing */
 	armv7a_cache_auto_flush_on_write(target, address, size * count);
 
+	retval = cortex_a_write_apb_ab_memory(target, address, size, count, buffer);
+
 	return retval;
 }