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mips: add breakpoint support for EJTAG 2.0

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EJTAG 1.5, 2.0 and 2.5 have different breakpoint register addresses.
This patch add support of EJTAG 2.0, which is part some broadcom
SoCs.

This work was testet on Broadcom BCM7401.

Change-Id: I4b0ee23871fa9205f9001b7c9165e7b6ebe9ccbf
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/1464
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Oleksij Rempel
2013-04-15 12:10:04 +02:00
committed by Spencer Oliver
parent 6a5848faeb
commit d18807e7bc
4 changed files with 152 additions and 23 deletions
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22
src/target/mips32.c
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@@ -472,11 +472,12 @@ int mips32_examine(struct target *target)
static int mips32_configure_ibs(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
int retval, i;
uint32_t bpinfo;
/* get number of inst breakpoints */
retval = target_read_u32(target, EJTAG_IBS, &bpinfo);
retval = target_read_u32(target, ejtag_info->ejtag_ibs_addr, &bpinfo);
if (retval != ERROR_OK)
return retval;
@@ -487,21 +488,23 @@ static int mips32_configure_ibs(struct target *target)
for (i = 0; i < mips32->num_inst_bpoints; i++)
mips32->inst_break_list[i].reg_address =
EJTAG_IBA1 + (0x100 * i);
ejtag_info->ejtag_iba0_addr +
(ejtag_info->ejtag_iba_step_size * i);
/* clear IBIS reg */
retval = target_write_u32(target, EJTAG_IBS, 0);
retval = target_write_u32(target, ejtag_info->ejtag_ibs_addr, 0);
return retval;
}
static int mips32_configure_dbs(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
int retval, i;
uint32_t bpinfo;
/* get number of data breakpoints */
retval = target_read_u32(target, EJTAG_DBS, &bpinfo);
retval = target_read_u32(target, ejtag_info->ejtag_dbs_addr, &bpinfo);
if (retval != ERROR_OK)
return retval;
@@ -512,10 +515,11 @@ static int mips32_configure_dbs(struct target *target)
for (i = 0; i < mips32->num_data_bpoints; i++)
mips32->data_break_list[i].reg_address =
EJTAG_DBA1 + (0x100 * i);
ejtag_info->ejtag_dba0_addr +
(ejtag_info->ejtag_dba_step_size * i);
/* clear DBIS reg */
retval = target_write_u32(target, EJTAG_DBS, 0);
retval = target_write_u32(target, ejtag_info->ejtag_dbs_addr, 0);
return retval;
}
@@ -523,6 +527,7 @@ int mips32_configure_break_unit(struct target *target)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
int retval;
uint32_t dcr;
@@ -534,6 +539,11 @@ int mips32_configure_break_unit(struct target *target)
if (retval != ERROR_OK)
return retval;
/* EJTAG 2.0 does not specify EJTAG_DCR_IB and EJTAG_DCR_DB bits,
* assume IB and DB registers are always present. */
if (ejtag_info->ejtag_version == EJTAG_VERSION_20)
dcr |= EJTAG_DCR_IB | EJTAG_DCR_DB;
if (dcr & EJTAG_DCR_IB) {
retval = mips32_configure_ibs(target);
if (retval != ERROR_OK)