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arm_opcode: Add support for ARM MCRR/MRRC

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Add support for the ARM MCRR/MRRC instructions which require the use of
two registers to transfer a 64-bit co-processor registers. We are going
to use this in a subsequent patch in order to properly dump 64-bit page
table descriptors that exist on ARMv7A with VMSA extensions.

We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.

Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Michael Chalfant <michael.chalfant@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/5228
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Florian Fainelli
2019-03-18 16:00:07 -07:00
committed by Antonio Borneo
parent 1bc4182ceb
commit d27a3a00b8
6 changed files with 262 additions and 0 deletions
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22
src/target/arm_opcodes.h
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@@ -187,6 +187,17 @@
(0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
/* Move to two ARM registers from coprocessor
* cp: Coprocessor number
* op: Coprocessor opcode
* rt: destination register 1
* rt2: destination register 2
* crm: coprocessor source register
*/
#define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \
(0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \
| ((rt) << 12) | ((rt2) << 16))
/* Move to coprocessor from ARM register
* cp: Coprocessor number
* op1: Coprocessor opcode
@@ -199,6 +210,17 @@
(0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
/* Move to coprocessor from two ARM registers
* cp: Coprocessor number
* op: Coprocessor opcode
* rt: destination register 1
* rt2: destination register 2
* crm: coprocessor source register
*/
#define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \
(0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \
| ((rt) << 12) | ((rt2) << 16))
/* Breakpoint instruction (ARMv5)
* im: 16-bit immediate
*/