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target/armv7m: rework Cortex-M register handling part 3

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Move primask/basepri/faultmask/control packing/unpacking from
cortex_m.c and hla_target.c to armv7m.c armv7m_read_core_reg()
and armv7m_write_core_reg() where also the FP 32/64-bit registers
conversion takes place.

Introduce a new hidden register ARMV7M_PMSK_BPRI_FLTMSK_CTRL
for packing/unpacking of special registers in the register cache.

The new packing/unpacking is endianess safe.

While on it improve returned error codes and LOG_ messages.

Just minimal changes in cortex_m.c and hla_target.c, will be
consolidated in the next patch.

Change-Id: Id51e764e243e54b5fdaadf2a202eee7c4bc729fe
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/5863
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Tomas Vanek
2020-10-14 20:23:50 +02:00
committed by Antonio Borneo
parent e4160bd422
commit d3a37b0e76
4 changed files with 170 additions and 176 deletions
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10
src/target/armv7m.h
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@@ -128,6 +128,16 @@ enum {
ARMV7M_PSP = ARMV7M_REGSEL_PSP,
/* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
/* working register for packing/unpacking special regs, hidden from gdb */
ARMV7M_PMSK_BPRI_FLTMSK_CTRL,
/* WARNING: If you use armv7m_write_core_reg() on one of 4 following
* special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
* cache only and are not flushed to CPU HW register.
* To trigger write to CPU HW register, add
* armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
*/
ARMV7M_PRIMASK,
ARMV7M_BASEPRI,
ARMV7M_FAULTMASK,