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- rename log functions to stop conflicts under win32 (wingdi)

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git-svn-id: svn://svn.berlios.de/openocd/trunk@523 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
ntfreak
2008-03-25 15:45:17 +00:00
parent a96f96d1f0
commit d47e1b8f36
72 changed files with 1507 additions and 1515 deletions
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120
src/target/arm11.c
View File

@@ -34,13 +34,13 @@
#if 0
#define FNC_INFO DEBUG("-")
#define FNC_INFO LOG_DEBUG("-")
#else
#define FNC_INFO
#endif
#if 1
#define FNC_INFO_NOTIMPLEMENTED do { DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
#define FNC_INFO_NOTIMPLEMENTED do { LOG_DEBUG("NOT IMPLEMENTED"); /*exit(-1);*/ } while (0)
#else
#define FNC_INFO_NOTIMPLEMENTED
#endif
@@ -324,7 +324,7 @@ void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
{
DEBUG("Bringing target into debug mode");
LOG_DEBUG("Bringing target into debug mode");
*dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
arm11_write_DSCR(arm11, *dscr);
@@ -428,7 +428,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
u32 dscr = arm11_read_DSCR(arm11);
DEBUG("DRAIN, DSCR %08x", dscr);
LOG_DEBUG("DRAIN, DSCR %08x", dscr);
if (dscr & ARM11_DSCR_STICKY_IMPRECISE_DATA_ABORT)
{
@@ -436,7 +436,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
dscr = arm11_read_DSCR(arm11);
DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
LOG_DEBUG("DRAIN, DSCR %08x (DONE)", dscr);
break;
}
@@ -502,7 +502,7 @@ static void arm11_on_enter_debug_state(arm11_common_t * arm11)
{
arm11->simulate_reset_on_next_halt = false;
DEBUG("Reset c1 Control Register");
LOG_DEBUG("Reset c1 Control Register");
/* Write 0 (reset value) to Control register 0 to disable MMU/Cache etc. */
@@ -524,18 +524,18 @@ void arm11_dump_reg_changes(arm11_common_t * arm11)
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
}}
@@ -565,7 +565,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
/* MRC p14,0,r?,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
// DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
}}
arm11_run_instr_data_finish(arm11);
@@ -579,7 +579,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11)
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
}
}
@@ -667,7 +667,7 @@ int arm11_poll(struct target_s *target)
u32 dscr = arm11_read_DSCR(arm11);
DEBUG("DSCR %08x", dscr);
LOG_DEBUG("DSCR %08x", dscr);
arm11_check_init(arm11, &dscr);
@@ -677,7 +677,7 @@ int arm11_poll(struct target_s *target)
{
enum target_state old_state = target->state;
DEBUG("enter TARGET_HALTED");
LOG_DEBUG("enter TARGET_HALTED");
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
@@ -690,7 +690,7 @@ int arm11_poll(struct target_s *target)
{
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
DEBUG("enter TARGET_RUNNING");
LOG_DEBUG("enter TARGET_RUNNING");
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
@@ -724,7 +724,7 @@ int arm11_halt(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state == TARGET_UNKNOWN)
{
@@ -733,7 +733,7 @@ int arm11_halt(struct target_s *target)
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
LOG_WARNING("target was already halted");
return ERROR_OK;
}
@@ -775,23 +775,23 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
{
FNC_INFO;
// DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
arm11_common_t * arm11 = target->arch_info;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!current)
R(PC) = address;
INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
@@ -807,7 +807,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
{
if (bp->address == R(PC))
{
DEBUG("must step over %08x", bp->address);
LOG_DEBUG("must step over %08x", bp->address);
arm11_step(target, 1, 0, 0);
break;
}
@@ -830,7 +830,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
arm11_sc7_run(arm11, brp, asizeof(brp));
DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
brp_num++;
}
@@ -849,7 +849,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b
{
u32 dscr = arm11_read_DSCR(arm11);
DEBUG("DSCR %08x", dscr);
LOG_DEBUG("DSCR %08x", dscr);
if (dscr & ARM11_DSCR_CORE_RESTARTED)
break;
@@ -875,11 +875,11 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
{
FNC_INFO;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -888,7 +888,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
if (!current)
R(PC) = address;
INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
@@ -902,7 +902,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
INFO("Skipping BKPT");
LOG_INFO("Skipping BKPT");
}
/* skip over Wait for interrupt / Standby */
/* mcr 15, 0, r?, cr7, cr0, {4} */
@@ -911,12 +911,12 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
INFO("Skipping WFI");
LOG_INFO("Skipping WFI");
}
/* ignore B to self */
else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
{
INFO("Not stepping jump to self");
LOG_INFO("Not stepping jump to self");
}
else
{
@@ -956,7 +956,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre
{
u32 dscr = arm11_read_DSCR(arm11);
DEBUG("DSCR %08x", dscr);
LOG_DEBUG("DSCR %08x", dscr);
if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
(ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
@@ -1003,7 +1003,7 @@ int arm11_deassert_reset(struct target_s *target)
FNC_INFO;
#if 0
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
@@ -1077,11 +1077,11 @@ int arm11_read_memory(struct target_s *target, u32 address, u32 size, u32 count,
if (target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
arm11_common_t * arm11 = target->arch_info;
@@ -1152,11 +1152,11 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
if (target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
LOG_DEBUG("ADDR %08x SIZE %08x COUNT %08x", address, size, count);
arm11_common_t * arm11 = target->arch_info;
@@ -1230,10 +1230,10 @@ int arm11_write_memory(struct target_s *target, u32 address, u32 size, u32 count
if (address + size * count != r0)
{
ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
if (arm11_config_memwrite_burst)
ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
if (arm11_config_memwrite_error_fatal)
exit(-1);
@@ -1258,7 +1258,7 @@ int arm11_bulk_write_memory(struct target_s *target, u32 address, u32 count, u8
if (target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1286,20 +1286,20 @@ int arm11_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
#if 0
if (breakpoint->type == BKPT_SOFT)
{
INFO("sw breakpoint requested, but software breakpoints not enabled");
LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
#endif
if (!arm11->free_brps)
{
INFO("no breakpoint unit available for hardware breakpoint");
LOG_INFO("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->length != 4)
{
INFO("only breakpoints of four bytes length supported");
LOG_INFO("only breakpoints of four bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -1348,7 +1348,7 @@ int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (argc < 4)
{
ERROR("'target arm11' 4th argument <jtag chain pos>");
LOG_ERROR("'target arm11' 4th argument <jtag chain pos>");
exit(-1);
}
@@ -1368,7 +1368,7 @@ int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (device->ir_length != 5)
{
ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
LOG_ERROR("'target arm11' expects 'jtag_device 5 0x01 0x1F 0x1E'");
exit(-1);
}
@@ -1411,12 +1411,12 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
switch (arm11->device_id & 0x0FFFF000)
{
case 0x07B36000: INFO("found ARM1136"); break;
case 0x07B56000: INFO("found ARM1156"); break;
case 0x07B76000: INFO("found ARM1176"); break;
case 0x07B36000: LOG_INFO("found ARM1136"); break;
case 0x07B56000: LOG_INFO("found ARM1156"); break;
case 0x07B76000: LOG_INFO("found ARM1176"); break;
default:
{
ERROR("'target arm11' expects IDCODE 0x*7B*7****");
LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
exit(-1);
}
}
@@ -1426,7 +1426,7 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
if (arm11->debug_version != ARM11_DEBUG_V6 &&
arm11->debug_version != ARM11_DEBUG_V61)
{
ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
LOG_ERROR("Only ARMv6 v6 and v6.1 architectures supported.");
exit(-1);
}
@@ -1438,7 +1438,7 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
arm11->free_brps = arm11->brp;
arm11->free_wrps = arm11->wrp;
DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
arm11->device_id,
arm11->implementor,
arm11->didr);
@@ -1472,7 +1472,7 @@ int arm11_get_reg(reg_t *reg)
if (target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1535,7 +1535,7 @@ void arm11_build_reg_cache(target_t *target)
ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) ||
ARM11_REGCACHE_COUNT != ARM11_RC_MAX)
{
ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
LOG_ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX);
exit(-1);
}
@@ -1566,7 +1566,7 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args,
{
if (argc == 0)
{
INFO("%s is %s.", name, *var ? "enabled" : "disabled");
LOG_INFO("%s is %s.", name, *var ? "enabled" : "disabled");
return ERROR_OK;
}
@@ -1592,7 +1592,7 @@ int arm11_handle_bool(struct command_context_s *cmd_ctx, char *cmd, char **args,
break;
}
INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
LOG_INFO("%s %s.", *var ? "Enabled" : "Disabled", name);
return ERROR_OK;
}
@@ -1633,7 +1633,7 @@ int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args,
return ERROR_COMMAND_SYNTAX_ERROR;
}
INFO("VCR 0x%08X", arm11_vcr);
LOG_INFO("VCR 0x%08X", arm11_vcr);
return ERROR_OK;
}
@@ -1676,7 +1676,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
{
if (argc != (read ? 6 : 7))
{
ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
}
@@ -1684,7 +1684,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (!arm11)
{
ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
@@ -1693,7 +1693,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (arm11->target->state != TARGET_HALTED)
{
WARNING("target was not halted");
LOG_WARNING("target was not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1707,7 +1707,7 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
if (values[i] > arm11_coproc_instruction_limits[i])
{
ERROR("Parameter %d out of bounds (%d max). %s",
LOG_ERROR("Parameter %d out of bounds (%d max). %s",
i + 2, arm11_coproc_instruction_limits[i],
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
@@ -1732,14 +1732,14 @@ int arm11_handle_mrc_mcr(struct command_context_s *cmd_ctx, char *cmd, char **ar
u32 result;
arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
values[0], values[1], values[2], values[3], values[4], result, result);
}
else
{
arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
values[0], values[1],
values[5],
values[2], values[3], values[4]);

22
src/target/arm11_dbgtap.c
View File

@@ -128,7 +128,7 @@ static int arm11_in_handler_SCAN_N(u8 *in_value, void *priv, struct scan_field_s
if (v != 0x10)
{
ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
LOG_ERROR("'arm11 target' JTAG communication error SCREG SCAN OUT 0x%02x (expected 0x10)", v);
exit(-1);
}
@@ -277,31 +277,31 @@ enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr)
switch (dscr & ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_MASK)
{
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_HALT:
INFO("Debug entry: JTAG HALT");
LOG_INFO("Debug entry: JTAG HALT");
return DBG_REASON_DBGRQ;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BREAKPOINT:
INFO("Debug entry: breakpoint");
LOG_INFO("Debug entry: breakpoint");
return DBG_REASON_BREAKPOINT;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_WATCHPOINT:
INFO("Debug entry: watchpoint");
LOG_INFO("Debug entry: watchpoint");
return DBG_REASON_WATCHPOINT;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_BKPT_INSTRUCTION:
INFO("Debug entry: BKPT instruction");
LOG_INFO("Debug entry: BKPT instruction");
return DBG_REASON_BREAKPOINT;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_EDBGRQ:
INFO("Debug entry: EDBGRQ signal");
LOG_INFO("Debug entry: EDBGRQ signal");
return DBG_REASON_DBGRQ;
case ARM11_DSCR_METHOD_OF_DEBUG_ENTRY_VECTOR_CATCH:
INFO("Debug entry: VCR vector catch");
LOG_INFO("Debug entry: VCR vector catch");
return DBG_REASON_BREAKPOINT;
default:
INFO("Debug entry: unknown");
LOG_INFO("Debug entry: unknown");
return DBG_REASON_DBGRQ;
}
};
@@ -541,7 +541,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32
}}
if (error_count)
ERROR("Transfer errors " ZU, error_count);
LOG_ERROR("Transfer errors " ZU, error_count);
}
@@ -707,7 +707,7 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t
{
if (actions[i - 1].address != AddressIn)
{
WARNING("Scan chain 7 shifted out unexpected address");
LOG_WARNING("Scan chain 7 shifted out unexpected address");
}
if (!actions[i - 1].write)
@@ -718,7 +718,7 @@ void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t
{
if (actions[i - 1].value != DataIn)
{
WARNING("Scan chain 7 shifted out unexpected data");
LOG_WARNING("Scan chain 7 shifted out unexpected data");
}
}
}

16
src/target/arm720t.c
View File

@@ -136,11 +136,11 @@ int arm720t_scan_cp15(target_t *target, u32 out, u32 *in, int instruction, int c
jtag_execute_queue();
if (in)
DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
else
DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
#else
DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
#endif
return ERROR_OK;
@@ -235,7 +235,7 @@ void arm720t_post_debug_entry(target_t *target)
/* examine cp15 control reg */
arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
jtag_execute_queue();
DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
@@ -311,11 +311,11 @@ int arm720t_arch_state(struct target_s *target)
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("BUG: called for a non-ARMv4/5 target");
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
USER("target halted in %s state due to %s, current mode: %s\n"
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
@@ -448,7 +448,7 @@ int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
if (argc < 4)
{
ERROR("'target arm720t' requires at least one additional argument");
LOG_ERROR("'target arm720t' requires at least one additional argument");
exit(-1);
}
@@ -457,7 +457,7 @@ int arm720t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
if (argc >= 5)
variant = args[4];
DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm720t_init_arch_info(target, arm720t, chain_pos, variant);

182
src/target/arm7_9_common.c
View File

@@ -135,7 +135,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -144,7 +144,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->set)
{
WARNING("breakpoint already set");
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
@@ -178,7 +178,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
}
else
{
ERROR("BUG: no hardware comparator available");
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_OK;
}
}
@@ -195,7 +195,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
target->type->read_memory(target, breakpoint->address, 4, 1, (u8 *)&verify);
if (verify != arm7_9->arm_bkpt)
{
ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x", breakpoint->address);
return ERROR_OK;
}
}
@@ -210,7 +210,7 @@ int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
target->type->read_memory(target, breakpoint->address, 2, 1, (u8 *)&verify);
if (verify != arm7_9->thumb_bkpt)
{
ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
LOG_ERROR("Unable to set thumb software breakpoint at address %08x", breakpoint->address);
return ERROR_OK;
}
}
@@ -228,13 +228,13 @@ int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!breakpoint->set)
{
WARNING("breakpoint not set");
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
@@ -286,31 +286,31 @@ int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (arm7_9->force_hw_bkpts)
{
DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
breakpoint->type = BKPT_HARD;
}
if ((breakpoint->type == BKPT_SOFT) && (arm7_9->sw_bkpts_enabled == 0))
{
INFO("sw breakpoint requested, but software breakpoints not enabled");
LOG_INFO("sw breakpoint requested, but software breakpoints not enabled");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->type == BKPT_HARD) && (arm7_9->wp_available < 1))
{
INFO("no watchpoint unit available for hardware breakpoint");
LOG_INFO("no watchpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->length != 2) && (breakpoint->length != 4))
{
INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -327,7 +327,7 @@ int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -353,7 +353,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -392,7 +392,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
}
else
{
ERROR("BUG: no hardware comparator available");
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_OK;
}
@@ -406,13 +406,13 @@ int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!watchpoint->set)
{
WARNING("breakpoint not set");
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
@@ -440,7 +440,7 @@ int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -466,7 +466,7 @@ int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -491,7 +491,7 @@ int arm7_9_enable_sw_bkpts(struct target_s *target)
if (arm7_9->wp_available < 1)
{
WARNING("can't enable sw breakpoints with no watchpoint unit available");
LOG_WARNING("can't enable sw breakpoints with no watchpoint unit available");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
arm7_9->wp_available--;
@@ -518,13 +518,13 @@ int arm7_9_enable_sw_bkpts(struct target_s *target)
}
else
{
ERROR("BUG: both watchpoints used, but wp_available >= 1");
LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
exit(-1);
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
LOG_ERROR("error writing EmbeddedICE registers to enable sw breakpoints");
exit(-1);
};
@@ -584,7 +584,7 @@ int arm7_9_execute_sys_speed(struct target_s *target)
}
if (timeout == 50)
{
ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
return ERROR_TARGET_TIMEOUT;
}
@@ -697,11 +697,11 @@ int arm7_9_poll(target_t *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1))
{
DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
LOG_DEBUG("DBGACK set, dbg_state->value: 0x%x", buf_get_u32(dbg_stat->value, 0, 32));
if (target->state == TARGET_UNKNOWN)
{
target->state = TARGET_RUNNING;
WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
LOG_WARNING("DBGACK set while target was in unknown state. Reset or initialize target.");
}
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
@@ -721,7 +721,7 @@ int arm7_9_poll(target_t *target)
}
if (target->state != TARGET_HALTED)
{
WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
LOG_WARNING("DBGACK set, but the target did not end up in the halted stated %d", target->state);
}
}
else
@@ -737,7 +737,7 @@ int arm7_9_assert_reset(target_t *target)
{
int retval;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state == TARGET_HALTED || target->state == TARGET_UNKNOWN)
{
@@ -754,7 +754,7 @@ int arm7_9_assert_reset(target_t *target)
}
else
{
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
}
}
@@ -782,7 +782,7 @@ int arm7_9_assert_reset(target_t *target)
}
else if (retval != ERROR_OK)
{
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
}
}
@@ -799,7 +799,7 @@ int arm7_9_assert_reset(target_t *target)
int arm7_9_deassert_reset(target_t *target)
{
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
@@ -876,7 +876,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
}
if (i==10)
{
ERROR("Failed to halt CPU after 1 sec");
LOG_ERROR("Failed to halt CPU after 1 sec");
return ERROR_TARGET_TIMEOUT;
}
target->state = TARGET_HALTED;
@@ -895,7 +895,7 @@ int arm7_9_soft_reset_halt(struct target_s *target)
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
{
u32 r0_thumb, pc_thumb;
DEBUG("target entered debug from Thumb state, changing to ARM");
LOG_DEBUG("target entered debug from Thumb state, changing to ARM");
/* Entered debug from Thumb mode */
armv4_5->core_state = ARMV4_5_STATE_THUMB;
arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
@@ -965,24 +965,24 @@ int arm7_9_halt(target_t *target)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
LOG_WARNING("target was already halted");
return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
{
WARNING("target was in unknown state when halt was requested");
LOG_WARNING("target was in unknown state when halt was requested");
}
if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
ERROR("can't request a halt while in reset if nSRST pulls nTRST");
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
}
else
@@ -1033,7 +1033,7 @@ int arm7_9_debug_entry(target_t *target)
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
#ifdef _DEBUG_ARM7_9_
DEBUG("-");
LOG_DEBUG("-");
#endif
if (arm7_9->pre_debug_entry)
@@ -1054,7 +1054,7 @@ int arm7_9_debug_entry(target_t *target)
switch (retval)
{
case ERROR_JTAG_QUEUE_FAILED:
ERROR("JTAG queue failed while writing EmbeddedICE control register");
LOG_ERROR("JTAG queue failed while writing EmbeddedICE control register");
exit(-1);
break;
default:
@@ -1068,22 +1068,22 @@ int arm7_9_debug_entry(target_t *target)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* if the target is in Thumb state, change to ARM state */
if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_ITBIT, 1))
{
DEBUG("target entered debug from Thumb state");
LOG_DEBUG("target entered debug from Thumb state");
/* Entered debug from Thumb mode */
armv4_5->core_state = ARMV4_5_STATE_THUMB;
arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
}
else
{
DEBUG("target entered debug from ARM state");
LOG_DEBUG("target entered debug from ARM state");
/* Entered debug from ARM mode */
armv4_5->core_state = ARMV4_5_STATE_ARM;
}
@@ -1111,15 +1111,15 @@ int arm7_9_debug_entry(target_t *target)
if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
{
target->state = TARGET_UNKNOWN;
ERROR("cpsr contains invalid mode value - communication failure");
LOG_ERROR("cpsr contains invalid mode value - communication failure");
return ERROR_TARGET_FAILURE;
}
DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
if (armv4_5->core_state == ARMV4_5_STATE_THUMB)
{
DEBUG("thumb state, applying fixups");
LOG_DEBUG("thumb state, applying fixups");
context[0] = r0_thumb;
context[15] = pc_thumb;
} else if (armv4_5->core_state == ARMV4_5_STATE_ARM)
@@ -1138,19 +1138,19 @@ int arm7_9_debug_entry(target_t *target)
context[15] -= arm7_9->dbgreq_adjust_pc * ((armv4_5->core_state == ARMV4_5_STATE_ARM) ? 4 : 2);
else
{
ERROR("unknown debug reason: %i", target->debug_reason);
LOG_ERROR("unknown debug reason: %i", target->debug_reason);
}
for (i=0; i<=15; i++)
{
DEBUG("r%i: 0x%8.8x", i, context[i]);
LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
}
DEBUG("entered debug state at PC 0x%x", context[15]);
LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
/* exceptions other than USR & SYS have a saved program status register */
if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
@@ -1183,11 +1183,11 @@ int arm7_9_full_context(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
DEBUG("-");
LOG_DEBUG("-");
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1249,7 +1249,7 @@ int arm7_9_full_context(target_t *target)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG failure");
LOG_ERROR("JTAG failure");
exit(-1);
}
return ERROR_OK;
@@ -1266,11 +1266,11 @@ int arm7_9_restore_context(target_t *target)
int dirty;
int mode_change;
DEBUG("-");
LOG_DEBUG("-");
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1282,7 +1282,7 @@ int arm7_9_restore_context(target_t *target)
*/
for (i = 0; i < 6; i++)
{
DEBUG("examining %s mode", armv4_5_mode_strings[i]);
LOG_DEBUG("examining %s mode", armv4_5_mode_strings[i]);
dirty = 0;
mode_change = 0;
/* check if there are dirty registers in the current mode
@@ -1296,19 +1296,19 @@ int arm7_9_restore_context(target_t *target)
if (reg->valid == 1)
{
dirty = 1;
DEBUG("examining dirty reg: %s", reg->name);
LOG_DEBUG("examining dirty reg: %s", reg->name);
if ((reg_arch_info->mode != ARMV4_5_MODE_ANY)
&& (reg_arch_info->mode != current_mode)
&& !((reg_arch_info->mode == ARMV4_5_MODE_USR) && (armv4_5->core_mode == ARMV4_5_MODE_SYS))
&& !((reg_arch_info->mode == ARMV4_5_MODE_SYS) && (armv4_5->core_mode == ARMV4_5_MODE_USR)))
{
mode_change = 1;
DEBUG("require mode change");
LOG_DEBUG("require mode change");
}
}
else
{
ERROR("BUG: dirty register '%s', but no valid data", reg->name);
LOG_ERROR("BUG: dirty register '%s', but no valid data", reg->name);
}
}
}
@@ -1344,7 +1344,7 @@ int arm7_9_restore_context(target_t *target)
num_regs++;
reg->dirty = 0;
reg->valid = 1;
DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
}
}
@@ -1357,7 +1357,7 @@ int arm7_9_restore_context(target_t *target)
reg_arch_info = reg->arch_info;
if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
{
DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
}
}
@@ -1371,20 +1371,20 @@ int arm7_9_restore_context(target_t *target)
tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
tmp_cpsr |= armv4_5_number_to_mode(i);
tmp_cpsr &= ~0x20;
DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
}
else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
{
/* CPSR has been changed, full restore necessary (mask T bit) */
DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
}
/* restore PC */
DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
armv4_5->core_cache->reg_list[15].dirty = 0;
@@ -1467,11 +1467,11 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
int err;
DEBUG("-");
LOG_DEBUG("-");
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1489,10 +1489,10 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
{
if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
{
DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
arm7_9_unset_breakpoint(target, breakpoint);
DEBUG("enable single-step");
LOG_DEBUG("enable single-step");
arm7_9->enable_single_step(target);
target->debug_reason = DBG_REASON_SINGLESTEP;
@@ -1507,7 +1507,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
}
else
{
ERROR("unhandled core state");
LOG_ERROR("unhandled core state");
exit(-1);
}
@@ -1515,7 +1515,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
embeddedice_write_reg(dbg_ctrl, buf_get_u32(dbg_ctrl->value, 0, dbg_ctrl->size));
err = arm7_9_execute_sys_speed(target);
DEBUG("disable single-step");
LOG_DEBUG("disable single-step");
arm7_9->disable_single_step(target);
if (err != ERROR_OK)
@@ -1526,9 +1526,9 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
}
arm7_9_debug_entry(target);
DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
arm7_9_set_breakpoint(target, breakpoint);
}
}
@@ -1549,7 +1549,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
}
else
{
ERROR("unhandled core state");
LOG_ERROR("unhandled core state");
exit(-1);
}
@@ -1577,7 +1577,7 @@ int arm7_9_resume(struct target_s *target, int current, u32 address, int handle_
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
}
DEBUG("target resumed");
LOG_DEBUG("target resumed");
return ERROR_OK;
}
@@ -1627,7 +1627,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1656,7 +1656,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
}
else
{
ERROR("unhandled core state");
LOG_ERROR("unhandled core state");
exit(-1);
}
@@ -1674,7 +1674,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
} else {
arm7_9_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
DEBUG("target stepped");
LOG_DEBUG("target stepped");
}
if (breakpoint)
@@ -1729,7 +1729,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG failure");
LOG_ERROR("JTAG failure");
exit(-1);
}
@@ -1818,11 +1818,11 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
int retval;
int last_reg = 0;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1923,7 +1923,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
}
break;
default:
ERROR("BUG: we shouldn't get here");
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
break;
}
@@ -1934,13 +1934,13 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
arm7_9->read_xpsr(target, &cpsr, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while reading cpsr");
LOG_ERROR("JTAG error while reading cpsr");
return ERROR_TARGET_DATA_ABORT;
}
if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
{
WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
@@ -1965,12 +1965,12 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
int last_reg = 0;
#ifdef _DEBUG_ARM7_9_
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
#endif
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2086,7 +2086,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
}
break;
default:
ERROR("BUG: we shouldn't get here");
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
break;
}
@@ -2101,13 +2101,13 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
arm7_9->read_xpsr(target, &cpsr, 0);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while reading cpsr");
LOG_ERROR("JTAG error while reading cpsr");
return ERROR_TARGET_DATA_ABORT;
}
if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
{
WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
@@ -2144,7 +2144,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
/* make sure we have a working area */
if (target_alloc_working_area(target, 24, &arm7_9->dcc_working_area) != ERROR_OK)
{
INFO("no working area available, falling back to memory writes");
LOG_INFO("no working area available, falling back to memory writes");
return target->type->write_memory(target, address, 4, count, buffer);
}
@@ -2216,7 +2216,7 @@ int arm7_9_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffe
}
if (i == 100)
{
ERROR("bulk write timed out, target not halted");
LOG_ERROR("bulk write timed out, target not halted");
return ERROR_TARGET_TIMEOUT;
}
@@ -2294,7 +2294,7 @@ int arm7_9_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address + (sizeof(arm7_9_crc_code) - 8), 20000, &armv4_5_info)) != ERROR_OK)
{
ERROR("error executing arm7_9 crc algorithm");
LOG_ERROR("error executing arm7_9 crc algorithm");
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);
target_free_working_area(target, crc_algorithm);
@@ -2377,7 +2377,7 @@ int handle_arm7_9_write_xpsr_command(struct command_context_s *cmd_ctx, char *cm
arm7_9->write_xpsr(target, value, spsr);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while writing to xpsr");
LOG_ERROR("JTAG error while writing to xpsr");
return retval;
}
@@ -2419,7 +2419,7 @@ int handle_arm7_9_write_xpsr_im8_command(struct command_context_s *cmd_ctx, char
arm7_9->write_xpsr_im8(target, value, rotate, spsr);
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while writing 8-bit immediate to xpsr");
LOG_ERROR("JTAG error while writing 8-bit immediate to xpsr");
return retval;
}

20
src/target/arm7tdmi.c
View File

@@ -200,10 +200,10 @@ int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
if (in)
{
DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in);
LOG_DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in);
}
else
DEBUG("out: 0x%8.8x", out);
LOG_DEBUG("out: 0x%8.8x", out);
}
#endif
@@ -249,11 +249,11 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
if (in)
{
DEBUG("in: 0x%8.8x", *in);
LOG_DEBUG("in: 0x%8.8x", *in);
}
else
{
ERROR("BUG: called with in == NULL");
LOG_ERROR("BUG: called with in == NULL");
}
}
#endif
@@ -314,11 +314,11 @@ int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
if (in)
{
DEBUG("in: 0x%8.8x", *in);
LOG_DEBUG("in: 0x%8.8x", *in);
}
else
{
ERROR("BUG: called with in == NULL");
LOG_ERROR("BUG: called with in == NULL");
}
}
#endif
@@ -476,7 +476,7 @@ void arm7tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);
@@ -507,7 +507,7 @@ void arm7tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
/* MSR fetched */
arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), NULL, 0);
@@ -673,7 +673,7 @@ void arm7tdmi_branch_resume(target_t *target)
void arm7tdmi_branch_resume_thumb(target_t *target)
{
DEBUG("-");
LOG_DEBUG("-");
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -849,7 +849,7 @@ int arm7tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
if (argc < 4)
{
ERROR("'target arm7tdmi' requires at least one additional argument");
LOG_ERROR("'target arm7tdmi' requires at least one additional argument");
exit(-1);
}

30
src/target/arm920t.c
View File

@@ -157,7 +157,7 @@ int arm920t_read_cp15_physical(target_t *target, int reg_addr, u32 *value)
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif
return ERROR_OK;
@@ -223,7 +223,7 @@ int arm920t_write_cp15_physical(target_t *target, int reg_addr, u32 value)
jtag_add_dr_scan(4, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
#endif
return ERROR_OK;
@@ -294,7 +294,7 @@ int arm920t_execute_cp15(target_t *target, u32 cp15_opcode, u32 arm_opcode)
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("failed executing JTAG queue, exiting");
LOG_ERROR("failed executing JTAG queue, exiting");
exit(-1);
}
@@ -332,7 +332,7 @@ int arm920t_read_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 address
jtag_execute_queue();
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
LOG_DEBUG("cp15_opcode: %8.8x, address: %8.8x, value: %8.8x", cp15_opcode, address, *value);
#endif
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -367,7 +367,7 @@ int arm920t_write_cp15_interpreted(target_t *target, u32 cp15_opcode, u32 value,
arm920t_write_cp15_physical(target, 0x1e, cp15c15);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
LOG_DEBUG("cp15_opcode: %8.8x, value: %8.8x, address: %8.8x", cp15_opcode, value, address);
#endif
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = 1;
@@ -438,7 +438,7 @@ void arm920t_post_debug_entry(target_t *target)
/* examine cp15 control reg */
arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
jtag_execute_queue();
DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
@@ -459,7 +459,7 @@ void arm920t_post_debug_entry(target_t *target)
arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
if (arm920t->preserve_cache)
@@ -550,11 +550,11 @@ int arm920t_arch_state(struct target_s *target)
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("BUG: called for a non-ARMv4/5 target");
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
USER( "target halted in %s state due to %s, current mode: %s\n"
LOG_USER( "target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
@@ -593,7 +593,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
{
if (arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
{
DEBUG("D-Cache enabled, writing through to main memory");
LOG_DEBUG("D-Cache enabled, writing through to main memory");
u32 pa, cb, ap;
int type, domain;
@@ -607,7 +607,7 @@ int arm920t_write_memory(struct target_s *target, u32 address, u32 size, u32 cou
if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
{
DEBUG("I-Cache enabled, invalidating affected I-Cache line");
LOG_DEBUG("I-Cache enabled, invalidating affected I-Cache line");
arm920t_write_cp15_interpreted(target, 0xee070f35, 0x0, address);
}
}
@@ -715,7 +715,7 @@ int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
if (argc < 4)
{
ERROR("'target arm920t' requires at least one additional argument");
LOG_ERROR("'target arm920t' requires at least one additional argument");
exit(-1);
}
@@ -724,7 +724,7 @@ int arm920t_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
if (argc >= 5)
variant = args[4];
DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm920t_init_arch_info(target, arm920t, chain_pos, variant);
@@ -786,7 +786,7 @@ int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *c
if ((output = fopen(args[0], "w")) == NULL)
{
DEBUG("error opening cache content file");
LOG_DEBUG("error opening cache content file");
return ERROR_OK;
}
@@ -1027,7 +1027,7 @@ int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd
if ((output = fopen(args[0], "w")) == NULL)
{
DEBUG("error opening mmu content file");
LOG_DEBUG("error opening mmu content file");
return ERROR_OK;
}

44
src/target/arm926ejs.c
View File

@@ -108,7 +108,7 @@ int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
}
else if ((t == 0x0f) || (t == 0x00))
{
DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
LOG_DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
return ERROR_OK;
}
return ERROR_JTAG_QUEUE_FAILED;;
@@ -189,7 +189,7 @@ int arm926ejs_cp15_read(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u3
} while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("addr: 0x%x value: %8.8x", address, *value);
LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
#endif
arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
@@ -268,7 +268,7 @@ int arm926ejs_cp15_write(target_t *target, u32 op1, u32 op2, u32 CRn, u32 CRm, u
} while (buf_get_u32(&access, 0, 1) != 1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("addr: 0x%x value: %8.8x", address, value);
LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
#endif
arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
@@ -293,50 +293,50 @@ int arm926ejs_examine_debug_reason(target_t *target)
switch (debug_reason)
{
case 1:
DEBUG("breakpoint from EICE unit 0");
LOG_DEBUG("breakpoint from EICE unit 0");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 2:
DEBUG("breakpoint from EICE unit 1");
LOG_DEBUG("breakpoint from EICE unit 1");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 3:
DEBUG("soft breakpoint (BKPT instruction)");
LOG_DEBUG("soft breakpoint (BKPT instruction)");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 4:
DEBUG("vector catch breakpoint");
LOG_DEBUG("vector catch breakpoint");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 5:
DEBUG("external breakpoint");
LOG_DEBUG("external breakpoint");
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 6:
DEBUG("watchpoint from EICE unit 0");
LOG_DEBUG("watchpoint from EICE unit 0");
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case 7:
DEBUG("watchpoint from EICE unit 1");
LOG_DEBUG("watchpoint from EICE unit 1");
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case 8:
DEBUG("external watchpoint");
LOG_DEBUG("external watchpoint");
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
case 9:
DEBUG("internal debug request");
LOG_DEBUG("internal debug request");
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 10:
DEBUG("external debug request");
LOG_DEBUG("external debug request");
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 11:
ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
LOG_ERROR("BUG: debug re-entry from system speed access shouldn't be handled here");
break;
default:
ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
LOG_ERROR("BUG: unknown debug reason: 0x%x", debug_reason);
target->debug_reason = DBG_REASON_DBGRQ;
retval = ERROR_TARGET_FAILURE;
break;
@@ -445,7 +445,7 @@ void arm926ejs_post_debug_entry(target_t *target)
/* examine cp15 control reg */
arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
jtag_execute_queue();
DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
@@ -465,7 +465,7 @@ void arm926ejs_post_debug_entry(target_t *target)
arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
@@ -551,11 +551,11 @@ int arm926ejs_arch_state(struct target_s *target)
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("BUG: called for a non-ARMv4/5 target");
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
USER(
LOG_USER(
"target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
@@ -706,7 +706,7 @@ int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char
if (argc < 4)
{
ERROR("'target arm926ejs' requires at least one additional argument");
LOG_ERROR("'target arm926ejs' requires at least one additional argument");
exit(-1);
}
@@ -715,7 +715,7 @@ int arm926ejs_target_command(struct command_context_s *cmd_ctx, char *cmd, char
if (argc >= 5)
variant = args[4];
DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);
@@ -937,7 +937,7 @@ static int arm926ejs_mmu(struct target_s *target, int *enabled)
if (target->state != TARGET_HALTED)
{
ERROR("Target not halted");
LOG_ERROR("Target not halted");
return ERROR_TARGET_INVALID;
}
*enabled = arm926ejs->armv4_5_mmu.mmu_enabled;

8
src/target/arm966e.c
View File

@@ -129,7 +129,7 @@ int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
if (argc < 4)
{
ERROR("'target arm966e' requires at least one additional argument");
LOG_ERROR("'target arm966e' requires at least one additional argument");
exit(-1);
}
@@ -138,7 +138,7 @@ int arm966e_target_command(struct command_context_s *cmd_ctx, char *cmd, char **
if (argc >= 5)
variant = args[4];
DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm966e_init_arch_info(target, arm966e, chain_pos, variant);
@@ -235,7 +235,7 @@ int arm966e_read_cp15(target_t *target, int reg_addr, u32 *value)
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
jtag_execute_queue();
DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif
return ERROR_OK;
@@ -290,7 +290,7 @@ int arm966e_write_cp15(target_t *target, int reg_addr, u32 value)
jtag_add_dr_scan(3, fields, -1);
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
#endif
return ERROR_OK;

20
src/target/arm9tdmi.c
View File

@@ -244,10 +244,10 @@ int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int s
if (in)
{
DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x, in: 0x%8.8x", instr, out, *in);
}
else
DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
LOG_DEBUG("instr: 0x%8.8x, out: 0x%8.8x", instr, out);
}
#endif
@@ -304,11 +304,11 @@ int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
if (in)
{
DEBUG("in: 0x%8.8x", *in);
LOG_DEBUG("in: 0x%8.8x", *in);
}
else
{
ERROR("BUG: called with in == NULL");
LOG_ERROR("BUG: called with in == NULL");
}
}
#endif
@@ -380,11 +380,11 @@ int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size,
if (in)
{
DEBUG("in: 0x%8.8x", *in);
LOG_DEBUG("in: 0x%8.8x", *in);
}
else
{
ERROR("BUG: called with in == NULL");
LOG_ERROR("BUG: called with in == NULL");
}
}
#endif
@@ -544,7 +544,7 @@ void arm9tdmi_write_xpsr(target_t *target, u32 xpsr, int spsr)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
/* MSR1 fetched */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
@@ -580,7 +580,7 @@ void arm9tdmi_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
/* MSR fetched */
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
@@ -745,7 +745,7 @@ void arm9tdmi_branch_resume(target_t *target)
void arm9tdmi_branch_resume_thumb(target_t *target)
{
DEBUG("-");
LOG_DEBUG("-");
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -992,7 +992,7 @@ int arm9tdmi_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
if (argc < 4)
{
ERROR("'target arm9tdmi' requires at least one additional argument");
LOG_ERROR("'target arm9tdmi' requires at least one additional argument");
exit(-1);
}

8
src/target/arm_disassembler.c
View File

@@ -57,7 +57,7 @@ int evaluate_pld(u32 opcode, u32 address, arm_instruction_t *instruction)
return ERROR_OK;
}
ERROR("should never reach this point");
LOG_ERROR("should never reach this point");
return -1;
}
@@ -1317,7 +1317,7 @@ int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
return evaluate_cdp_mcr_mrc(opcode, address, instruction);
}
ERROR("should never reach this point");
LOG_ERROR("should never reach this point");
return -1;
}
@@ -2076,7 +2076,7 @@ int thumb_evaluate_opcode(u16 opcode, u32 address, arm_instruction_t *instructio
}
}
ERROR("should never reach this point (opcode=%04x)",opcode);
LOG_ERROR("should never reach this point (opcode=%04x)",opcode);
return -1;
}
@@ -2110,7 +2110,7 @@ int arm_access_size(arm_instruction_t *instruction)
}
else
{
ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type);
LOG_ERROR("BUG: instruction type %i isn't a load/store instruction", instruction->type);
return 0;
}
}

10
src/target/arm_simulator.c
View File

@@ -160,7 +160,7 @@ u32 arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifte
}
else
{
ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
return_value = 0xffffffff;
}
@@ -253,7 +253,7 @@ int pass_condition(u32 cpsr, u32 opcode)
}
ERROR("BUG: should never get here");
LOG_ERROR("BUG: should never get here");
return 0;
}
@@ -444,7 +444,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
else
{
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
WARNING("no updating of flags yet");
LOG_WARNING("no updating of flags yet");
if (instruction.info.data_proc.Rd == 15)
return ERROR_OK;
@@ -460,7 +460,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
}
else
{
WARNING("no updating of flags yet");
LOG_WARNING("no updating of flags yet");
}
}
/* load register instructions */
@@ -497,7 +497,7 @@ int arm_simulate_step(target_t *target, u32 *dry_run_pc)
}
else
{
ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
}
if (instruction.info.load_store.index_mode == 0)

40
src/target/armv4_5.c
View File

@@ -183,7 +183,7 @@ int armv4_5_mode_to_number(enum armv4_5_mode mode)
case ARMV4_5_MODE_SYS: return 6; break;
case ARMV4_5_MODE_ANY: return 0; break; /* map MODE_ANY to user mode */
default:
ERROR("invalid mode value encountered");
LOG_ERROR("invalid mode value encountered");
return -1;
}
}
@@ -201,7 +201,7 @@ enum armv4_5_mode armv4_5_number_to_mode(int number)
case 5: return ARMV4_5_MODE_UND; break;
case 6: return ARMV4_5_MODE_SYS; break;
default:
ERROR("mode index out of bounds");
LOG_ERROR("mode index out of bounds");
return -1;
}
};
@@ -243,7 +243,7 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
if (armv4_5_target->core_state == ARMV4_5_STATE_ARM)
{
/* change state to Thumb */
DEBUG("changing to Thumb state");
LOG_DEBUG("changing to Thumb state");
armv4_5_target->core_state = ARMV4_5_STATE_THUMB;
}
}
@@ -253,14 +253,14 @@ int armv4_5_set_core_reg(reg_t *reg, u8 *buf)
if (armv4_5_target->core_state == ARMV4_5_STATE_THUMB)
{
/* change state to ARM */
DEBUG("changing to ARM state");
LOG_DEBUG("changing to ARM state");
armv4_5_target->core_state = ARMV4_5_STATE_ARM;
}
}
if (armv4_5_target->core_mode != (value & 0x1f))
{
DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
LOG_DEBUG("changing ARM core mode to '%s'", armv4_5_mode_strings[armv4_5_mode_to_number(value & 0x1f)]);
armv4_5_target->core_mode = value & 0x1f;
armv4_5_target->write_core_reg(target, 16, ARMV4_5_MODE_ANY, value);
}
@@ -328,11 +328,11 @@ int armv4_5_arch_state(struct target_s *target)
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("BUG: called for a non-ARMv4/5 target");
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
armv4_5_state_strings[armv4_5->core_state],
target_debug_reason_strings[target->debug_reason],
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
@@ -507,13 +507,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
if (armv4_5_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("current target isn't an ARMV4/5 target");
LOG_ERROR("current target isn't an ARMV4/5 target");
return ERROR_TARGET_INVALID;
}
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -535,13 +535,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
exit(-1);
}
if (reg->size != reg_params[i].size)
{
ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
exit(-1);
}
@@ -555,13 +555,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
exit_breakpoint_size = 2;
else
{
ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
exit(-1);
}
if (armv4_5_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
LOG_DEBUG("setting core_mode: 0x%2.2x", armv4_5_algorithm_info->core_mode);
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 5, armv4_5_algorithm_info->core_mode);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
@@ -569,7 +569,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
{
ERROR("can't add breakpoint to finish algorithm execution");
LOG_ERROR("can't add breakpoint to finish algorithm execution");
return ERROR_TARGET_FAILURE;
}
@@ -582,7 +582,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
target->type->poll(target);
if ((timeout_ms -= 10) <= 0)
{
ERROR("timeout waiting for algorithm to complete, trying to halt target");
LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target");
target->type->halt(target);
timeout_ms = 1000;
while (target->state != TARGET_HALTED)
@@ -591,7 +591,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
target->type->poll(target);
if ((timeout_ms -= 10) <= 0)
{
ERROR("target didn't reenter debug state, exiting");
LOG_ERROR("target didn't reenter debug state, exiting");
exit(-1);
}
}
@@ -602,7 +602,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
if ((retval != ERROR_TARGET_TIMEOUT) &&
(buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point))
{
WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
}
@@ -622,13 +622,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
reg_t *reg = register_get_by_name(armv4_5->core_cache, reg_params[i].reg_name, 0);
if (!reg)
{
ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
exit(-1);
}
if (reg->size != reg_params[i].size)
{
ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
exit(-1);
}
@@ -638,7 +638,7 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
for (i = 0; i <= 16; i++)
{
DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;

12
src/target/armv4_5_mmu.c
View File

@@ -49,19 +49,19 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
4, 1, (u8*)&first_lvl_descriptor);
first_lvl_descriptor = target_buffer_get_u32(target, (u8*)&first_lvl_descriptor);
DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
if ((first_lvl_descriptor & 0x3) == 0)
{
*type = -1;
ERROR("Address translation failure");
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
if (!armv4_5_mmu->has_tiny_pages && ((first_lvl_descriptor & 0x3) == 3))
{
*type = -1;
ERROR("Address translation failure");
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
@@ -94,12 +94,12 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
second_lvl_descriptor = target_buffer_get_u32(target, (u8*)&second_lvl_descriptor);
DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 0)
{
*type = -1;
ERROR("Address translation failure");
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}
@@ -132,7 +132,7 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
/* should not happen */
*type = -1;
ERROR("Address translation failure");
LOG_ERROR("Address translation failure");
return ERROR_TARGET_TRANSLATION_FAULT;
}

36
src/target/armv7m.c
View File

@@ -143,7 +143,7 @@ enum armv7m_runcontext armv7m_get_context(target_t *target)
if (armv7m->debug_context == armv7m->core_cache)
return ARMV7M_DEBUG_CONTEXT;
ERROR("Invalid runcontext");
LOG_ERROR("Invalid runcontext");
exit(-1);
}
@@ -155,7 +155,7 @@ int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
if ((target->state != TARGET_HALTED) && (target->state != TARGET_RESET))
{
WARNING("target not halted, switch context ");
LOG_WARNING("target not halted, switch context ");
return ERROR_TARGET_NOT_HALTED;
}
@@ -171,7 +171,7 @@ int armv7m_use_context(target_t *target, enum armv7m_runcontext new_ctx)
armv7m->core_cache = armv7m->debug_context;
break;
default:
ERROR("Invalid runcontext");
LOG_ERROR("Invalid runcontext");
exit(-1);
}
/* Mark registers in new context as dirty to force reload when run */
@@ -191,7 +191,7 @@ int armv7m_restore_context(target_t *target)
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
DEBUG(" ");
LOG_DEBUG(" ");
if (armv7m->pre_restore_context)
armv7m->pre_restore_context(target);
@@ -296,11 +296,11 @@ int armv7m_write_core_reg(struct target_s *target, int num)
retval = armv7m->store_core_reg_u32(target, armv7m_core_reg->type, armv7m_core_reg->num, reg_value);
if (retval != ERROR_OK)
{
ERROR("JTAG failure");
LOG_ERROR("JTAG failure");
armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
DEBUG("write core reg %i value 0x%x", num , reg_value);
LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
armv7m->core_cache->reg_list[num].valid = 1;
armv7m->core_cache->reg_list[num].dirty = 0;
@@ -361,13 +361,13 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC)
{
ERROR("current target isn't an ARMV7M target");
LOG_ERROR("current target isn't an ARMV7M target");
return ERROR_TARGET_INVALID;
}
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -387,13 +387,13 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
if (!reg)
{
ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
exit(-1);
}
if (reg->size != reg_params[i].size)
{
ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
exit(-1);
}
@@ -404,7 +404,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
/* ARMV7M always runs in Thumb state */
if ((retval = breakpoint_add(target, exit_point, 2, BKPT_SOFT)) != ERROR_OK)
{
ERROR("can't add breakpoint to finish algorithm execution");
LOG_ERROR("can't add breakpoint to finish algorithm execution");
return ERROR_TARGET_FAILURE;
}
@@ -419,7 +419,7 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
target->type->poll(target);
if ((timeout_ms -= 5) <= 0)
{
ERROR("timeout waiting for algorithm to complete, trying to halt target");
LOG_ERROR("timeout waiting for algorithm to complete, trying to halt target");
target->type->halt(target);
timeout_ms = 1000;
while (target->state != TARGET_HALTED)
@@ -428,12 +428,12 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
target->type->poll(target);
if ((timeout_ms -= 10) <= 0)
{
ERROR("target didn't reenter debug state, exiting");
LOG_ERROR("target didn't reenter debug state, exiting");
exit(-1);
}
}
armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
DEBUG("failed algoritm halted at 0x%x ", pc);
LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
retval = ERROR_TARGET_TIMEOUT;
}
}
@@ -456,13 +456,13 @@ int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_
if (!reg)
{
ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
exit(-1);
}
if (reg->size != reg_params[i].size)
{
ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params[i].reg_name);
exit(-1);
}
@@ -478,7 +478,7 @@ int armv7m_arch_state(struct target_s *target)
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
LOG_USER("target halted in %s state due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
armv7m_state_strings[armv7m->core_state],
target_debug_reason_strings[target->debug_reason],
armv7m_mode_strings[armv7m->core_mode],
@@ -642,7 +642,7 @@ int armv7m_checksum_memory(struct target_s *target, u32 address, u32 count, u32*
if ((retval = target->type->run_algorithm(target, 0, NULL, 2, reg_params,
crc_algorithm->address, crc_algorithm->address + (sizeof(cortex_m3_crc_code)-6), 20000, &armv7m_info)) != ERROR_OK)
{
ERROR("error executing cortex_m3 crc algorithm");
LOG_ERROR("error executing cortex_m3 crc algorithm");
destroy_reg_param(&reg_params[0]);
destroy_reg_param(&reg_params[1]);
target_free_working_area(target, crc_algorithm);

28
src/target/breakpoints.c
View File

@@ -70,27 +70,27 @@ int breakpoint_add(target_t *target, u32 address, u32 length, enum breakpoint_ty
switch (retval)
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
INFO("can't add %s breakpoint, resource not available", breakpoint_type_strings[(*breakpoint_p)->type]);
LOG_INFO("can't add %s breakpoint, resource not available", breakpoint_type_strings[(*breakpoint_p)->type]);
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
return retval;
break;
case ERROR_TARGET_NOT_HALTED:
INFO("can't add breakpoint while target is running");
LOG_INFO("can't add breakpoint while target is running");
free((*breakpoint_p)->orig_instr);
free(*breakpoint_p);
*breakpoint_p = NULL;
return retval;
break;
default:
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
break;
}
}
DEBUG("added %s breakpoint at 0x%8.8x of length 0x%8.8x",
LOG_DEBUG("added %s breakpoint at 0x%8.8x of length 0x%8.8x",
breakpoint_type_strings[(*breakpoint_p)->type],
(*breakpoint_p)->address, (*breakpoint_p)->length);
@@ -118,11 +118,11 @@ int breakpoint_remove(target_t *target, u32 address)
switch (retval)
{
case ERROR_TARGET_NOT_HALTED:
INFO("can't remove breakpoint while target is running");
LOG_INFO("can't remove breakpoint while target is running");
return retval;
break;
default:
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
break;
}
@@ -133,7 +133,7 @@ int breakpoint_remove(target_t *target, u32 address)
}
else
{
ERROR("no breakpoint at address 0x%8.8x found", address);
LOG_ERROR("no breakpoint at address 0x%8.8x found", address);
}
return ERROR_OK;
@@ -181,25 +181,25 @@ int watchpoint_add(target_t *target, u32 address, u32 length, enum watchpoint_rw
switch (retval)
{
case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
INFO("can't add %s watchpoint, resource not available", watchpoint_rw_strings[(*watchpoint_p)->rw]);
LOG_INFO("can't add %s watchpoint, resource not available", watchpoint_rw_strings[(*watchpoint_p)->rw]);
free (*watchpoint_p);
*watchpoint_p = NULL;
return retval;
break;
case ERROR_TARGET_NOT_HALTED:
INFO("can't add watchpoint while target is running");
LOG_INFO("can't add watchpoint while target is running");
free (*watchpoint_p);
*watchpoint_p = NULL;
return retval;
break;
default:
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
break;
}
}
DEBUG("added %s watchpoint at 0x%8.8x of length 0x%8.8x",
LOG_DEBUG("added %s watchpoint at 0x%8.8x of length 0x%8.8x",
watchpoint_rw_strings[(*watchpoint_p)->rw],
(*watchpoint_p)->address, (*watchpoint_p)->length);
@@ -227,11 +227,11 @@ int watchpoint_remove(target_t *target, u32 address)
switch (retval)
{
case ERROR_TARGET_NOT_HALTED:
INFO("can't remove watchpoint while target is running");
LOG_INFO("can't remove watchpoint while target is running");
return retval;
break;
default:
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
break;
}
@@ -241,7 +241,7 @@ int watchpoint_remove(target_t *target, u32 address)
}
else
{
ERROR("no watchpoint at address 0x%8.8x found", address);
LOG_ERROR("no watchpoint at address 0x%8.8x found", address);
}
return ERROR_OK;

130
src/target/cortex_m3.c
View File

@@ -103,7 +103,7 @@ int cortex_m3_clear_halt(target_t *target)
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
return ERROR_OK;
}
@@ -119,7 +119,7 @@ int cortex_m3_single_step_core(target_t *target)
ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN );
ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN );
cortex_m3->dcb_dhcsr |= C_MASKINTS;
DEBUG(" ");
LOG_DEBUG(" ");
cortex_m3_clear_halt(target);
return ERROR_OK;
@@ -171,7 +171,7 @@ int cortex_m3_endreset_event(target_t *target)
cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
@@ -284,7 +284,7 @@ int cortex_m3_examine_exception_reason(target_t *target)
break;
}
swjdp_transaction_endcheck(swjdp);
DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
shcsr, except_sr, cfsr, except_ar);
return ERROR_OK;
}
@@ -300,7 +300,7 @@ int cortex_m3_debug_entry(target_t *target)
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
DEBUG(" ");
LOG_DEBUG(" ");
if (armv7m->pre_debug_entry)
armv7m->pre_debug_entry(target);
@@ -342,7 +342,7 @@ int cortex_m3_debug_entry(target_t *target)
cortex_m3_examine_exception_reason(target);
}
DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s", armv7m_mode_strings[armv7m->core_mode], \
*(u32*)(armv7m->core_cache->reg_list[15].value), target_state_strings[target->state]);
if (armv7m->post_debug_entry)
@@ -384,7 +384,7 @@ int cortex_m3_poll(target_t *target)
if (target->state == TARGET_RESET)
{
/* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr);
LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr);
cortex_m3_endreset_event(target);
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
@@ -403,7 +403,7 @@ int cortex_m3_poll(target_t *target)
}
if (prev_target_state == TARGET_DEBUG_RUNNING)
{
DEBUG(" ");
LOG_DEBUG(" ");
if ((retval = cortex_m3_debug_entry(target)) != ERROR_OK)
return retval;
@@ -418,7 +418,7 @@ int cortex_m3_poll(target_t *target)
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, target_state_strings[target->state]);
return ERROR_OK;
}
@@ -429,24 +429,24 @@ int cortex_m3_halt(target_t *target)
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
LOG_WARNING("target was already halted");
return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
{
WARNING("target was in unknown state when halt was requested");
LOG_WARNING("target was in unknown state when halt was requested");
}
if (target->state == TARGET_RESET)
{
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) && jtag_srst)
{
ERROR("can't request a halt while in reset if nSRST pulls nTRST");
LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
}
else
@@ -480,7 +480,7 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
/* Check that we are using process_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
{
DEBUG("Changing to process contex registers");
LOG_DEBUG("Changing to process contex registers");
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
}
@@ -502,12 +502,12 @@ int cortex_m3_soft_reset_halt(struct target_s *target)
ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{
DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
cortex_m3_poll(target);
return ERROR_OK;
}
else
DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout);
LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout);
}
timeout++;
usleep(1000);
@@ -533,7 +533,7 @@ int cortex_m3_prepare_reset_halt(struct target_s *target)
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr);
LOG_DEBUG("dcb_dhcsr 0x%x, dcb_demcr 0x%x, ", dcb_dhcsr, dcb_demcr);
return ERROR_OK;
}
@@ -549,7 +549,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -558,7 +558,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
/* Check that we are using process_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
{
DEBUG("Incorrect context in resume");
LOG_DEBUG("Incorrect context in resume");
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
}
@@ -575,7 +575,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
/* Check that we are using debug_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_DEBUG_CONTEXT)
{
DEBUG("Incorrect context in debug_exec resume");
LOG_DEBUG("Incorrect context in debug_exec resume");
armv7m_use_context(target, ARMV7M_DEBUG_CONTEXT);
}
/* Disable interrupts */
@@ -608,7 +608,7 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
/* Single step past breakpoint at current address */
if ((breakpoint = breakpoint_find(target, resume_pc)))
{
DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
cortex_m3_unset_breakpoint(target, breakpoint);
cortex_m3_single_step_core(target);
cortex_m3_set_breakpoint(target, breakpoint);
@@ -629,13 +629,13 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand
{
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
DEBUG("target resumed at 0x%x",resume_pc);
LOG_DEBUG("target resumed at 0x%x",resume_pc);
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
DEBUG("target debug resumed at 0x%x",resume_pc);
LOG_DEBUG("target debug resumed at 0x%x",resume_pc);
}
return ERROR_OK;
@@ -652,14 +652,14 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
/* Check that we are using process_context, or change and print warning */
if (armv7m_get_context(target) != ARMV7M_PROCESS_CONTEXT)
{
WARNING("Incorrect context in step, must be process");
LOG_WARNING("Incorrect context in step, must be process");
armv7m_use_context(target, ARMV7M_PROCESS_CONTEXT);
}
@@ -690,12 +690,12 @@ int cortex_m3_step(struct target_s *target, int current, u32 address, int handle
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
cortex_m3_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
return ERROR_OK;
}
@@ -706,7 +706,7 @@ int cortex_m3_assert_reset(target_t *target)
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
@@ -735,7 +735,7 @@ int cortex_m3_assert_reset(target_t *target)
}
else
{
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
}
}
@@ -763,7 +763,7 @@ int cortex_m3_assert_reset(target_t *target)
}
else if (retval != ERROR_OK)
{
ERROR("unknown error");
LOG_ERROR("unknown error");
exit(-1);
}
}
@@ -780,7 +780,7 @@ int cortex_m3_assert_reset(target_t *target)
int cortex_m3_deassert_reset(target_t *target)
{
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* deassert reset lines */
jtag_add_reset(0, 0);
@@ -819,7 +819,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->set)
{
WARNING("breakpoint already set");
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
@@ -834,8 +834,8 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
fp_num++;
if (fp_num >= cortex_m3->fp_num_code)
{
DEBUG("ERROR Can not find free FP Comparator");
WARNING("ERROR Can not find free FP Comparator");
LOG_DEBUG("ERROR Can not find free FP Comparator");
LOG_WARNING("ERROR Can not find free FP Comparator");
exit(-1);
}
breakpoint->set = fp_num + 1;
@@ -843,7 +843,7 @@ int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
comparator_list[fp_num].used = 1;
comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
}
else if (breakpoint->type == BKPT_SOFT)
{
@@ -866,7 +866,7 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
if (!breakpoint->set)
{
WARNING("breakpoint not set");
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
@@ -875,7 +875,7 @@ int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
int fp_num = breakpoint->set - 1;
if ((fp_num < 0) || (fp_num >= cortex_m3->fp_num_code))
{
DEBUG("Invalid FP Comparator number in breakpoint");
LOG_DEBUG("Invalid FP Comparator number in breakpoint");
return ERROR_OK;
}
comparator_list[fp_num].used = 0;
@@ -912,25 +912,25 @@ int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if ((breakpoint->type == BKPT_HARD) && (breakpoint->address >= 0x20000000))
{
INFO("flash patch comparator requested outside code memory region");
LOG_INFO("flash patch comparator requested outside code memory region");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->type == BKPT_SOFT) && (breakpoint->address < 0x20000000))
{
INFO("soft breakpoint requested in code (flash) memory region");
LOG_INFO("soft breakpoint requested in code (flash) memory region");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->type == BKPT_HARD) && (cortex_m3->fp_code_available < 1))
{
INFO("no flash patch comparator unit available for hardware breakpoint");
LOG_INFO("no flash patch comparator unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if ((breakpoint->length != 2))
{
INFO("only breakpoints of two bytes length supported");
LOG_INFO("only breakpoints of two bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -949,7 +949,7 @@ int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -981,7 +981,7 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (watchpoint->set)
{
WARNING("watchpoint already set");
LOG_WARNING("watchpoint already set");
return ERROR_OK;
}
@@ -991,8 +991,8 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
dwt_num++;
if (dwt_num >= cortex_m3->dwt_num_comp)
{
DEBUG("ERROR Can not find free DWT Comparator");
WARNING("ERROR Can not find free DWT Comparator");
LOG_DEBUG("ERROR Can not find free DWT Comparator");
LOG_WARNING("ERROR Can not find free DWT Comparator");
return -1;
}
watchpoint->set = dwt_num + 1;
@@ -1010,11 +1010,11 @@ int cortex_m3_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
LOG_DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
}
else
{
WARNING("Cannot watch data values"); /* Move this test to add_watchpoint */
LOG_WARNING("Cannot watch data values"); /* Move this test to add_watchpoint */
return ERROR_OK;
}
@@ -1032,7 +1032,7 @@ int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint
if (!watchpoint->set)
{
WARNING("watchpoint not set");
LOG_WARNING("watchpoint not set");
return ERROR_OK;
}
@@ -1040,7 +1040,7 @@ int cortex_m3_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint
if ((dwt_num < 0) || (dwt_num >= cortex_m3->dwt_num_comp))
{
DEBUG("Invalid DWT Comparator number in watchpoint");
LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
return ERROR_OK;
}
comparator_list[dwt_num].used = 0;
@@ -1060,7 +1060,7 @@ int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1087,7 +1087,7 @@ int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoin
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1129,10 +1129,10 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
if (retval != ERROR_OK)
{
ERROR("JTAG failure %i",retval);
LOG_ERROR("JTAG failure %i",retval);
return ERROR_JTAG_DEVICE_ERROR;
}
DEBUG("load from core reg %i value 0x%x",num,*value);
LOG_DEBUG("load from core reg %i value 0x%x",num,*value);
}
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
{
@@ -1152,7 +1152,7 @@ int cortex_m3_load_core_reg_u32(struct target_s *target, enum armv7m_regtype typ
armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
ahbap_write_system_u32(swjdp, 0x20000000, savedram);
swjdp_transaction_endcheck(swjdp);
DEBUG("load from special reg %i value 0x%x", SYSm, *value);
LOG_DEBUG("load from special reg %i value 0x%x", SYSm, *value);
}
else
{
@@ -1176,11 +1176,11 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
retval = ahbap_write_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
ERROR("JTAG failure %i", retval);
LOG_ERROR("JTAG failure %i", retval);
armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
return ERROR_JTAG_DEVICE_ERROR;
}
DEBUG("write core reg %i value 0x%x", num, value);
LOG_DEBUG("write core reg %i value 0x%x", num, value);
}
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
{
@@ -1201,7 +1201,7 @@ int cortex_m3_store_core_reg_u32(struct target_s *target, enum armv7m_regtype ty
armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
ahbap_write_system_u32(swjdp, 0x20000000, savedram);
swjdp_transaction_endcheck(swjdp);
DEBUG("write special reg %i value 0x%x ", SYSm, value);
LOG_DEBUG("write special reg %i value 0x%x ", SYSm, value);
}
else
{
@@ -1237,7 +1237,7 @@ int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 co
retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
}
@@ -1268,7 +1268,7 @@ int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 c
retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
ERROR("BUG: we shouldn't get here");
LOG_ERROR("BUG: we shouldn't get here");
exit(-1);
}
@@ -1301,8 +1301,8 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
/* Read from Device Identification Registers */
target_read_u32(target, CPUID, &cpuid);
if (((cpuid >> 4) & 0xc3f) == 0xc23)
DEBUG("CORTEX-M3 processor detected");
DEBUG("cpuid: 0x%8.8x", cpuid);
LOG_DEBUG("CORTEX-M3 processor detected");
LOG_DEBUG("cpuid: 0x%8.8x", cpuid);
target_read_u32(target, NVIC_ICTR, &ictr);
cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
@@ -1310,7 +1310,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
for (i = 0; i < cortex_m3->intlinesnum; i++)
{
target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]);
LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]);
}
/* Setup FPB */
@@ -1325,7 +1325,7 @@ int cortex_m3_init_target(struct command_context_s *cmd_ctx, struct target_s *ta
cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
}
DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
/* Setup DWT */
target_read_u32(target, DWT_CTRL, &dwtcr);
@@ -1354,7 +1354,7 @@ int cortex_m3_dcc_read(swjdp_common_t *swjdp, u8 *value, u8 *ctrl)
*ctrl = (u8)dcrdr;
*value = (u8)(dcrdr >> 8);
DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
/* write ack back to software dcc register
* signify we have read data */
@@ -1470,7 +1470,7 @@ int cortex_m3_target_command(struct command_context_s *cmd_ctx, char *cmd, char
if (argc < 4)
{
ERROR("'target cortex_m3' requires at least one additional argument");
LOG_ERROR("'target cortex_m3' requires at least one additional argument");
exit(-1);
}

42
src/target/cortex_swjdp.c
View File

@@ -187,13 +187,13 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
waitcount++;
if (waitcount > 100)
{
WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
LOG_WARNING("Timeout waiting for ACK = OK/FAULT in SWJDP transaction");
return ERROR_JTAG_DEVICE_ERROR;
}
}
else
{
WARNING("Invalid ACK in SWJDP transaction");
LOG_WARNING("Invalid ACK in SWJDP transaction");
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -205,7 +205,7 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
/* Check for STICKYERR and STICKYORUN */
if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
{
DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
/* Check power to debug regions */
if ((ctrlstat & 0xf0000000) != 0xf0000000)
{
@@ -216,24 +216,24 @@ int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
if (ctrlstat & SSTICKYORUN)
ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
if (ctrlstat & SSTICKYERR)
ERROR("SWJ-DP STICKY ERROR");
LOG_ERROR("SWJ-DP STICKY ERROR");
/* Clear Sticky Error Bits */
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
jtag_execute_queue();
DEBUG("swjdp: status 0x%x", ctrlstat);
LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
/* Can we find out the reason for the error ?? */
ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
}
jtag_execute_queue();
return ERROR_JTAG_DEVICE_ERROR;
@@ -317,13 +317,13 @@ int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
if (csw != swjdp->ap_csw_value)
{
/* DEBUG("swjdp : Set CSW %x",csw); */
/* LOG_DEBUG("swjdp : Set CSW %x",csw); */
ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
/* DEBUG("swjdp : Set TAR %x",tar); */
/* LOG_DEBUG("swjdp : Set TAR %x",tar); */
ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
swjdp->ap_tar_value = tar;
}
@@ -452,7 +452,7 @@ int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 addres
if (errorcount > 1)
{
WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
return ERROR_JTAG_DEVICE_ERROR;
}
}
@@ -495,7 +495,7 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
{
if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -516,7 +516,7 @@ int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
@@ -586,7 +586,7 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
{
if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -607,7 +607,7 @@ int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32
ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
@@ -700,7 +700,7 @@ int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address
if (errorcount > 1)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
}
@@ -756,7 +756,7 @@ int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -841,7 +841,7 @@ int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 a
ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
WARNING("Block read error address 0x%x, count 0x%x", address, count);
LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -942,7 +942,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
u32 ctrlstat;
int cnt = 0;
DEBUG(" ");
LOG_DEBUG(" ");
swjdp->ap_csw_value = -1;
swjdp->ap_tar_value = -1;
@@ -960,7 +960,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
/* Check that we have debug power domains activated */
while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
{
DEBUG("swjdp: wait CDBGPWRUPACK");
LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
jtag_execute_queue();
usleep(10000);
@@ -968,7 +968,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
{
DEBUG("swjdp: wait CSYSPWRUPACK");
LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
jtag_execute_queue();
usleep(10000);
@@ -983,7 +983,7 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
return ERROR_OK;
}

16
src/target/embeddedice.c
View File

@@ -149,7 +149,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
arm7_9->has_single_step = 1;
break;
case 3:
ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
@@ -172,13 +172,13 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
arm7_9->has_monitor_mode = 1;
break;
case 7:
WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
default:
ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
}
/* explicitly disable monitor mode */
@@ -197,13 +197,13 @@ int embeddedice_get_reg(reg_t *reg)
{
if (embeddedice_read_reg(reg) != ERROR_OK)
{
ERROR("BUG: error scheduling EmbeddedICE register read");
LOG_ERROR("BUG: error scheduling EmbeddedICE register read");
exit(-1);
}
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("register read failed");
LOG_ERROR("register read failed");
}
return ERROR_OK;
@@ -346,7 +346,7 @@ int embeddedice_set_reg(reg_t *reg, u32 value)
{
if (embeddedice_write_reg(reg, value) != ERROR_OK)
{
ERROR("BUG: error scheduling EmbeddedICE register write");
LOG_ERROR("BUG: error scheduling EmbeddedICE register write");
exit(-1);
}
@@ -363,7 +363,7 @@ int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf)
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("register write failed");
LOG_ERROR("register write failed");
exit(-1);
}
return ERROR_OK;
@@ -373,7 +373,7 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
{
embeddedice_reg_t *ice_reg = reg->arch_info;
DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(ice_reg->jtag_info, 0x2);

26
src/target/etb.c
View File

@@ -162,13 +162,13 @@ int etb_get_reg(reg_t *reg)
{
if (etb_read_reg(reg) != ERROR_OK)
{
ERROR("BUG: error scheduling etm register read");
LOG_ERROR("BUG: error scheduling etm register read");
exit(-1);
}
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("register read failed");
LOG_ERROR("register read failed");
}
return ERROR_OK;
@@ -248,7 +248,7 @@ int etb_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
u8 reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
DEBUG("%i", etb_reg->addr);
LOG_DEBUG("%i", etb_reg->addr);
jtag_add_end_state(TAP_RTI);
etb_scann(etb_reg->etb, 0x0);
@@ -313,7 +313,7 @@ int etb_set_reg(reg_t *reg, u32 value)
{
if (etb_write_reg(reg, value) != ERROR_OK)
{
ERROR("BUG: error scheduling etm register write");
LOG_ERROR("BUG: error scheduling etm register write");
exit(-1);
}
@@ -330,7 +330,7 @@ int etb_set_reg_w_exec(reg_t *reg, u8 *buf)
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("register write failed");
LOG_ERROR("register write failed");
exit(-1);
}
return ERROR_OK;
@@ -342,7 +342,7 @@ int etb_write_reg(reg_t *reg, u32 value)
u8 reg_addr = etb_reg->addr & 0x7f;
scan_field_t fields[3];
DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
jtag_add_end_state(TAP_RTI);
etb_scann(etb_reg->etb, 0x0);
@@ -415,7 +415,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
if (argc != 2)
{
ERROR("incomplete 'etb config <target> <chain_pos>' command");
LOG_ERROR("incomplete 'etb config <target> <chain_pos>' command");
exit(-1);
}
@@ -423,7 +423,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
if (!target)
{
ERROR("target number '%s' not defined", args[0]);
LOG_ERROR("target number '%s' not defined", args[0]);
exit(-1);
}
@@ -437,7 +437,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
if (!jtag_device)
{
ERROR("jtag device number '%s' not defined", args[1]);
LOG_ERROR("jtag device number '%s' not defined", args[1]);
exit(-1);
}
@@ -455,7 +455,7 @@ int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cmd, char
}
else
{
ERROR("target has no ETM defined, ETB left unconfigured");
LOG_ERROR("target has no ETM defined, ETB left unconfigured");
}
return ERROR_OK;
@@ -516,13 +516,13 @@ trace_status_t etb_status(etm_context_t *etm_ctx)
if (etb_timeout == 0)
{
ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
}
if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
{
ERROR("trace completed, but no trigger condition detected");
LOG_ERROR("trace completed, but no trigger condition detected");
}
etm_ctx->capture_status &= ~TRACE_RUNNING;
@@ -693,7 +693,7 @@ int etb_start_capture(etm_context_t *etm_ctx)
{
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
{
ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
etb_ctrl_value |= 0x2;

38
src/target/etm.c
View File

@@ -278,7 +278,7 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co
if (!etb)
{
ERROR("etb selected as etm capture driver, but no ETB configured");
LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
return ERROR_OK;
}
@@ -289,7 +289,7 @@ reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_co
if (etm_ctx->capture_driver->init(etm_ctx) != ERROR_OK)
{
ERROR("ETM capture driver initialization failed");
LOG_ERROR("ETM capture driver initialization failed");
exit(-1);
}
@@ -300,13 +300,13 @@ int etm_get_reg(reg_t *reg)
{
if (etm_read_reg(reg) != ERROR_OK)
{
ERROR("BUG: error scheduling etm register read");
LOG_ERROR("BUG: error scheduling etm register read");
exit(-1);
}
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("register read failed");
LOG_ERROR("register read failed");
}
return ERROR_OK;
@@ -318,7 +318,7 @@ int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
u8 reg_addr = etm_reg->addr & 0x7f;
scan_field_t fields[3];
DEBUG("%i", etm_reg->addr);
LOG_DEBUG("%i", etm_reg->addr);
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
@@ -378,7 +378,7 @@ int etm_set_reg(reg_t *reg, u32 value)
{
if (etm_write_reg(reg, value) != ERROR_OK)
{
ERROR("BUG: error scheduling etm register write");
LOG_ERROR("BUG: error scheduling etm register write");
exit(-1);
}
@@ -395,7 +395,7 @@ int etm_set_reg_w_exec(reg_t *reg, u8 *buf)
if (jtag_execute_queue() != ERROR_OK)
{
ERROR("register write failed");
LOG_ERROR("register write failed");
exit(-1);
}
return ERROR_OK;
@@ -407,7 +407,7 @@ int etm_write_reg(reg_t *reg, u32 value)
u8 reg_addr = etm_reg->addr & 0x7f;
scan_field_t fields[3];
DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(etm_reg->jtag_info, 0x6);
@@ -526,7 +526,7 @@ int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
ctx->current_pc - ctx->image->sections[section].base_address,
4, buf, &size_read)) != ERROR_OK)
{
ERROR("error while reading instruction: %i", retval);
LOG_ERROR("error while reading instruction: %i", retval);
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
opcode = target_buffer_get_u32(ctx->target, buf);
@@ -539,7 +539,7 @@ int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
ctx->current_pc - ctx->image->sections[section].base_address,
2, buf, &size_read)) != ERROR_OK)
{
ERROR("error while reading instruction: %i", retval);
LOG_ERROR("error while reading instruction: %i", retval);
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
opcode = target_buffer_get_u16(ctx->target, buf);
@@ -547,12 +547,12 @@ int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
}
else if (ctx->core_state == ARMV4_5_STATE_JAZELLE)
{
ERROR("BUG: tracing of jazelle code not supported");
LOG_ERROR("BUG: tracing of jazelle code not supported");
exit(-1);
}
else
{
ERROR("BUG: unknown core state encountered");
LOG_ERROR("BUG: unknown core state encountered");
exit(-1);
}
@@ -724,7 +724,7 @@ int etmv1_data(etm_context_t *ctx, int size, u32 *data)
if (size == 8)
{
ERROR("TODO: add support for 64-bit values");
LOG_ERROR("TODO: add support for 64-bit values");
return -1;
}
else if (size == 4)
@@ -808,7 +808,7 @@ int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
/* a positive return values means the current branch was abandoned,
* and a new branch was encountered in cycle ctx->pipe_index + retval;
*/
WARNING("abandoned branch encountered, correctnes of analysis uncertain");
LOG_WARNING("abandoned branch encountered, correctnes of analysis uncertain");
ctx->pipe_index += retval;
continue;
}
@@ -853,7 +853,7 @@ int etmv1_analyze_trace(etm_context_t *ctx, struct command_context_s *cmd_ctx)
}
break;
default: /* reserved */
ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
exit(-1);
break;
}
@@ -1223,7 +1223,7 @@ int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char
if (argc != 5)
{
ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
LOG_ERROR("incomplete 'etm config <target> <port_width> <port_mode> <clocking> <capture_driver>' command");
exit(-1);
}
@@ -1231,7 +1231,7 @@ int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char
if (!target)
{
ERROR("target number '%s' not defined", args[0]);
LOG_ERROR("target number '%s' not defined", args[0]);
exit(-1);
}
@@ -1309,7 +1309,7 @@ int handle_etm_config_command(struct command_context_s *cmd_ctx, char *cmd, char
{
/* no supported capture driver found, don't register an ETM */
free(etm_ctx);
ERROR("trace capture driver '%s' not found", args[4]);
LOG_ERROR("trace capture driver '%s' not found", args[4]);
return ERROR_OK;
}
@@ -1393,7 +1393,7 @@ int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char *
max_port_size = 16;
break;
default:
ERROR("Illegal max_port_size");
LOG_ERROR("Illegal max_port_size");
exit(-1);
}
command_print(cmd_ctx, "max. port size: %i", max_port_size);

4
src/target/etm_dummy.c
View File

@@ -46,7 +46,7 @@ int handle_etm_dummy_config_command(struct command_context_s *cmd_ctx, char *cmd
if (!target)
{
ERROR("target number '%s' not defined", args[0]);
LOG_ERROR("target number '%s' not defined", args[0]);
exit(-1);
}
@@ -62,7 +62,7 @@ int handle_etm_dummy_config_command(struct command_context_s *cmd_ctx, char *cmd
}
else
{
ERROR("target has no ETM defined, ETM dummy left unconfigured");
LOG_ERROR("target has no ETM defined, ETM dummy left unconfigured");
}
return ERROR_OK;

16
src/target/feroceon.c
View File

@@ -229,7 +229,7 @@ void feroceon_write_xpsr(target_t *target, u32 xpsr, int spsr)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -270,7 +270,7 @@ void feroceon_write_xpsr_im8(target_t *target, u8 xpsr_im, int rot, int spsr)
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
LOG_DEBUG("xpsr_im: %2.2x, rot: %i, spsr: %i", xpsr_im, rot, spsr);
arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr_im, rot, 1, spsr), 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -320,7 +320,7 @@ void feroceon_branch_resume(target_t *target)
void feroceon_branch_resume_thumb(target_t *target)
{
DEBUG("-");
LOG_DEBUG("-");
armv4_5_common_t *armv4_5 = target->arch_info;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -415,7 +415,7 @@ void feroceon_enable_single_step(target_t *target)
u32 current_pc, current_opcode;
current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
target_read_u32(target, current_pc, &current_opcode);
ERROR("BUG: couldn't calculate PC of next instruction, "
LOG_ERROR("BUG: couldn't calculate PC of next instruction, "
"current opcode is 0x%8.8x", current_opcode);
next_pc = current_pc;
}
@@ -501,7 +501,7 @@ int feroceon_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buf
/* make sure we have a working area */
if (target_alloc_working_area(target, dcc_size, &arm7_9->dcc_working_area) != ERROR_OK)
{
INFO("no working area available, falling back to memory writes");
LOG_INFO("no working area available, falling back to memory writes");
return target->type->write_memory(target, address, 4, count, buffer);
}
@@ -578,7 +578,7 @@ int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *tar
/* the COMMS_CTRL bits are all contiguous */
if (buf_get_u32(arm7_9->eice_cache->reg_list[EICE_COMMS_CTRL].value, 2, 4) != 6)
ERROR("unexpected Feroceon EICE version signature");
LOG_ERROR("unexpected Feroceon EICE version signature");
arm7_9->eice_cache->reg_list[EICE_DBG_CTRL].size = 6;
arm7_9->eice_cache->reg_list[EICE_DBG_STAT].size = 5;
@@ -613,7 +613,7 @@ int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
if (argc < 4)
{
ERROR("'target arm926ejs' requires at least one additional argument");
LOG_ERROR("'target arm926ejs' requires at least one additional argument");
exit(-1);
}
@@ -622,7 +622,7 @@ int feroceon_target_command(struct command_context_s *cmd_ctx, char *cmd, char *
if (argc >= 5)
variant = args[4];
DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
LOG_DEBUG("chain_pos: %i, variant: %s", chain_pos, variant);
arm926ejs_init_arch_info(target, arm926ejs, chain_pos, variant);

50
src/target/image.c
View File

@@ -70,7 +70,7 @@ static int autodetect_image_type(image_t *image, char *url)
/* check header against known signatures */
if (strncmp((char*)buffer,ELFMAG,SELFMAG)==0)
{
DEBUG("ELF image detected.");
LOG_DEBUG("ELF image detected.");
image->type = IMAGE_ELF;
}
else if ((buffer[0]==':') /* record start byte */
@@ -83,7 +83,7 @@ static int autodetect_image_type(image_t *image, char *url)
&&(buffer[7]=='0') /* record type : 00 -> 05 */
&&(buffer[8]>='0')&&(buffer[8]<'6'))
{
DEBUG("IHEX image detected.");
LOG_DEBUG("IHEX image detected.");
image->type = IMAGE_IHEX;
}
else if ((buffer[0] == 'S') /* record start byte */
@@ -92,7 +92,7 @@ static int autodetect_image_type(image_t *image, char *url)
&&(isxdigit(buffer[3]))
&&(buffer[1] >= '0') && (buffer[1] < '9'))
{
DEBUG("S19 image detected.");
LOG_DEBUG("S19 image detected.");
image->type = IMAGE_SRECORD;
}
else
@@ -315,7 +315,7 @@ int image_ihex_buffer_complete(image_t *image)
}
else
{
ERROR("unhandled IHEX record type: %i", record_type);
LOG_ERROR("unhandled IHEX record type: %i", record_type);
return ERROR_IMAGE_FORMAT_ERROR;
}
@@ -325,12 +325,12 @@ int image_ihex_buffer_complete(image_t *image)
if ((u8)checksum != (u8)(~cal_checksum + 1))
{
/* checksum failed */
ERROR("incorrect record checksum found in IHEX file");
LOG_ERROR("incorrect record checksum found in IHEX file");
return ERROR_IMAGE_CHECKSUM;
}
}
ERROR("premature end of IHEX file, no end-of-file record found");
LOG_ERROR("premature end of IHEX file, no end-of-file record found");
return ERROR_IMAGE_FORMAT_ERROR;
}
@@ -345,23 +345,23 @@ int image_elf_read_headers(image_t *image)
if ((retval = fileio_read(&elf->fileio, sizeof(Elf32_Ehdr), (u8*)elf->header, &read_bytes)) != ERROR_OK)
{
ERROR("cannot read ELF file header, read failed");
LOG_ERROR("cannot read ELF file header, read failed");
return ERROR_FILEIO_OPERATION_FAILED;
}
if (read_bytes != sizeof(Elf32_Ehdr))
{
ERROR("cannot read ELF file header, only partially read");
LOG_ERROR("cannot read ELF file header, only partially read");
return ERROR_FILEIO_OPERATION_FAILED;
}
if (strncmp((char*)elf->header->e_ident,ELFMAG,SELFMAG)!=0)
{
ERROR("invalid ELF file, bad magic number");
LOG_ERROR("invalid ELF file, bad magic number");
return ERROR_IMAGE_FORMAT_ERROR;
}
if (elf->header->e_ident[EI_CLASS]!=ELFCLASS32)
{
ERROR("invalid ELF file, only 32bits files are supported");
LOG_ERROR("invalid ELF file, only 32bits files are supported");
return ERROR_IMAGE_FORMAT_ERROR;
}
@@ -370,20 +370,20 @@ int image_elf_read_headers(image_t *image)
if ((elf->endianness!=ELFDATA2LSB)
&&(elf->endianness!=ELFDATA2MSB))
{
ERROR("invalid ELF file, unknown endianess setting");
LOG_ERROR("invalid ELF file, unknown endianess setting");
return ERROR_IMAGE_FORMAT_ERROR;
}
elf->segment_count = field16(elf,elf->header->e_phnum);
if (elf->segment_count==0)
{
ERROR("invalid ELF file, no program headers");
LOG_ERROR("invalid ELF file, no program headers");
return ERROR_IMAGE_FORMAT_ERROR;
}
if ((retval = fileio_seek(&elf->fileio, field32(elf,elf->header->e_phoff))) != ERROR_OK)
{
ERROR("cannot seek to ELF program header table, read failed");
LOG_ERROR("cannot seek to ELF program header table, read failed");
return retval;
}
@@ -391,12 +391,12 @@ int image_elf_read_headers(image_t *image)
if ((retval = fileio_read(&elf->fileio, elf->segment_count*sizeof(Elf32_Phdr), (u8*)elf->segments, &read_bytes)) != ERROR_OK)
{
ERROR("cannot read ELF segment headers, read failed");
LOG_ERROR("cannot read ELF segment headers, read failed");
return retval;
}
if (read_bytes != elf->segment_count*sizeof(Elf32_Phdr))
{
ERROR("cannot read ELF segment headers, only partially read");
LOG_ERROR("cannot read ELF segment headers, only partially read");
return ERROR_FILEIO_OPERATION_FAILED;
}
@@ -434,24 +434,24 @@ int image_elf_read_section(image_t *image, int section, u32 offset, u32 size, u8
*size_read = 0;
DEBUG("load segment %d at 0x%x (sz=0x%x)",section,offset,size);
LOG_DEBUG("load segment %d at 0x%x (sz=0x%x)",section,offset,size);
/* read initialized data in current segment if any */
if (offset<field32(elf,segment->p_filesz))
{
/* maximal size present in file for the current segment */
read_size = MIN(size, field32(elf,segment->p_filesz)-offset);
DEBUG("read elf: size = 0x%x at 0x%x",read_size,
LOG_DEBUG("read elf: size = 0x%x at 0x%x",read_size,
field32(elf,segment->p_offset)+offset);
/* read initialized area of the segment */
if ((retval = fileio_seek(&elf->fileio, field32(elf,segment->p_offset)+offset)) != ERROR_OK)
{
ERROR("cannot find ELF segment content, seek failed");
LOG_ERROR("cannot find ELF segment content, seek failed");
return retval;
}
if ((retval = fileio_read(&elf->fileio, read_size, buffer, &really_read)) != ERROR_OK)
{
ERROR("cannot read ELF segment content, read failed");
LOG_ERROR("cannot read ELF segment content, read failed");
return retval;
}
buffer += read_size;
@@ -613,7 +613,7 @@ int image_mot_buffer_complete(image_t *image)
}
else
{
ERROR("unhandled S19 record type: %i", record_type);
LOG_ERROR("unhandled S19 record type: %i", record_type);
return ERROR_IMAGE_FORMAT_ERROR;
}
@@ -625,12 +625,12 @@ int image_mot_buffer_complete(image_t *image)
if( cal_checksum != 0xFF )
{
/* checksum failed */
ERROR("incorrect record checksum found in S19 file");
LOG_ERROR("incorrect record checksum found in S19 file");
return ERROR_IMAGE_CHECKSUM;
}
}
ERROR("premature end of S19 file, no end-of-file record found");
LOG_ERROR("premature end of S19 file, no end-of-file record found");
return ERROR_IMAGE_FORMAT_ERROR;
}
@@ -673,7 +673,7 @@ int image_open(image_t *image, char *url, char *type_string)
if ((retval = image_ihex_buffer_complete(image)) != ERROR_OK)
{
ERROR("failed buffering IHEX image, check daemon output for additional information");
LOG_ERROR("failed buffering IHEX image, check daemon output for additional information");
fileio_close(&image_ihex->fileio);
return retval;
}
@@ -724,7 +724,7 @@ int image_open(image_t *image, char *url, char *type_string)
if ((retval = image_mot_buffer_complete(image)) != ERROR_OK)
{
ERROR("failed buffering S19 image, check daemon output for additional information");
LOG_ERROR("failed buffering S19 image, check daemon output for additional information");
fileio_close(&image_mot->fileio);
return retval;
}
@@ -761,7 +761,7 @@ int image_read_section(image_t *image, int section, u32 offset, u32 size, u8 *bu
/* don't read past the end of a section */
if (offset + size > image->sections[section].size)
{
DEBUG("read past end of section: 0x%8.8x + 0x%8.8x > 0x%8.8x",
LOG_DEBUG("read past end of section: 0x%8.8x + 0x%8.8x > 0x%8.8x",
offset, size, image->sections[section].size);
return ERROR_INVALID_ARGUMENTS;
}

18
src/target/oocd_trace.c
View File

@@ -54,7 +54,7 @@ int oocd_trace_read_reg(oocd_trace_t *oocd_trace, int reg, u32 *value)
bytes_to_read -= bytes_read;
}
DEBUG("reg #%i: 0x%8.8x\n", reg, *value);
LOG_DEBUG("reg #%i: 0x%8.8x\n", reg, *value);
return ERROR_OK;
}
@@ -71,7 +71,7 @@ int oocd_trace_write_reg(oocd_trace_t *oocd_trace, int reg, u32 value)
data[4] = (value & 0xff000000) >> 24;
bytes_written = write(oocd_trace->tty_fd, data, 5);
DEBUG("reg #%i: 0x%8.8x\n", reg, value);
LOG_DEBUG("reg #%i: 0x%8.8x\n", reg, value);
return ERROR_OK;
}
@@ -93,7 +93,7 @@ int oocd_trace_read_memory(oocd_trace_t *oocd_trace, u8 *data, u32 address, u32
if ((bytes_read = read(oocd_trace->tty_fd,
((u8*)data) + (size * 16) - bytes_to_read, bytes_to_read)) < 0)
{
DEBUG("read() returned %i (%s)", bytes_read, strerror(errno));
LOG_DEBUG("read() returned %i (%s)", bytes_read, strerror(errno));
}
else
bytes_to_read -= bytes_read;
@@ -112,7 +112,7 @@ int oocd_trace_init(etm_context_t *etm_ctx)
if(oocd_trace->tty_fd < 0)
{
ERROR("can't open tty");
LOG_ERROR("can't open tty");
return ERROR_ETM_CAPTURE_INIT_FAILED;
}
@@ -143,7 +143,7 @@ int oocd_trace_init(etm_context_t *etm_ctx)
* read up any leftover characters to ensure communication is in sync */
while ((bytes_read = read(oocd_trace->tty_fd, trash, sizeof(trash))) > 0)
{
DEBUG("%i bytes read\n", bytes_read);
LOG_DEBUG("%i bytes read\n", bytes_read);
};
return ERROR_OK;
@@ -248,7 +248,7 @@ int oocd_trace_start_capture(etm_context_t *etm_ctx)
if (((etm_ctx->portmode & ETM_PORT_MODE_MASK) != ETM_PORT_NORMAL)
|| ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_4BIT))
{
DEBUG("OpenOCD+trace only supports normal 4-bit ETM mode");
LOG_DEBUG("OpenOCD+trace only supports normal 4-bit ETM mode");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
@@ -303,7 +303,7 @@ int handle_oocd_trace_config_command(struct command_context_s *cmd_ctx, char *cm
if (argc != 2)
{
ERROR("incomplete 'oocd_trace config <target> <tty>' command");
LOG_ERROR("incomplete 'oocd_trace config <target> <tty>' command");
exit(-1);
}
@@ -327,7 +327,7 @@ int handle_oocd_trace_config_command(struct command_context_s *cmd_ctx, char *cm
}
else
{
ERROR("target has no ETM defined, OpenOCD+trace left unconfigured");
LOG_ERROR("target has no ETM defined, OpenOCD+trace left unconfigured");
}
return ERROR_OK;
@@ -409,7 +409,7 @@ int handle_oocd_trace_resync_command(struct command_context_s *cmd_ctx, char *cm
bytes_written = write(oocd_trace->tty_fd, cmd_array, 1);
command_print(cmd_ctx, "requesting traceclock resync");
DEBUG("resyncing traceclk pll");
LOG_DEBUG("resyncing traceclk pll");
return ERROR_OK;
}

100
src/target/target.c
View File

@@ -211,7 +211,7 @@ target_t* get_current_target(command_context_t *cmd_ctx)
if (target == NULL)
{
ERROR("BUG: current_target out of bounds");
LOG_ERROR("BUG: current_target out of bounds");
exit(-1);
}
@@ -233,11 +233,11 @@ int target_init_handler(struct target_s *target, enum target_event event, void *
script = open_file_from_path(target->reset_script, "r");
if (!script)
{
ERROR("couldn't open script file %s", target->reset_script);
LOG_ERROR("couldn't open script file %s", target->reset_script);
return ERROR_OK;
}
INFO("executing reset script '%s'", target->reset_script);
LOG_INFO("executing reset script '%s'", target->reset_script);
command_run_file(cmd_ctx, script, COMMAND_EXEC);
fclose(script);
@@ -330,7 +330,7 @@ int target_process_reset(struct command_context_s *cmd_ctx)
target_register_event_callback(target_init_handler, cmd_ctx);
break;
default:
ERROR("BUG: unknown target->reset_mode");
LOG_ERROR("BUG: unknown target->reset_mode");
}
target = target->next;
}
@@ -362,12 +362,12 @@ int target_process_reset(struct command_context_s *cmd_ctx)
{
if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec)))
{
USER("Timed out waiting for reset");
LOG_USER("Timed out waiting for reset");
goto done;
}
/* this will send alive messages on e.g. GDB remote protocol. */
usleep(500*1000);
USER_N("%s", ""); /* avoid warning about zero length formatting message*/
LOG_USER_N("%s", ""); /* avoid warning about zero length formatting message*/
goto again;
}
}
@@ -409,7 +409,7 @@ int target_init(struct command_context_s *cmd_ctx)
{
if (target->type->init_target(cmd_ctx, target) != ERROR_OK)
{
ERROR("target '%s' init failed", target->type->name);
LOG_ERROR("target '%s' init failed", target->type->name);
exit(-1);
}
@@ -563,7 +563,7 @@ int target_call_event_callbacks(target_t *target, enum target_event event)
target_event_callback_t *callback = target_event_callbacks;
target_event_callback_t *next_callback;
DEBUG("target event %i", event);
LOG_DEBUG("target event %i", event);
while (callback)
{
@@ -651,7 +651,7 @@ int target_alloc_working_area(struct target_s *target, u32 size, working_area_t
/* only allocate multiples of 4 byte */
if (size % 4)
{
ERROR("BUG: code tried to allocate unaligned number of bytes, padding");
LOG_ERROR("BUG: code tried to allocate unaligned number of bytes, padding");
size = CEIL(size, 4);
}
@@ -673,7 +673,7 @@ int target_alloc_working_area(struct target_s *target, u32 size, working_area_t
u32 first_free = target->working_area;
u32 free_size = target->working_area_size;
DEBUG("allocating new working area");
LOG_DEBUG("allocating new working area");
c = target->working_areas;
while (c)
@@ -686,7 +686,7 @@ int target_alloc_working_area(struct target_s *target, u32 size, working_area_t
if (free_size < size)
{
WARNING("not enough working area available(requested %d, free %d)", size, free_size);
LOG_WARNING("not enough working area available(requested %d, free %d)", size, free_size);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -777,11 +777,11 @@ int target_arch_state(struct target_s *target)
int retval;
if (target==NULL)
{
USER("No target has been configured");
LOG_USER("No target has been configured");
return ERROR_OK;
}
USER("target state: %s", target_state_strings[target->state]);
LOG_USER("target state: %s", target_state_strings[target->state]);
if (target->state!=TARGET_HALTED)
return ERROR_OK;
@@ -798,7 +798,7 @@ int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buff
{
int retval;
DEBUG("writing buffer of %i byte at 0x%8.8x", size, address);
LOG_DEBUG("writing buffer of %i byte at 0x%8.8x", size, address);
if (((address % 2) == 0) && (size == 2))
{
@@ -862,7 +862,7 @@ int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffe
{
int retval;
DEBUG("reading buffer of %i byte at 0x%8.8x", size, address);
LOG_DEBUG("reading buffer of %i byte at 0x%8.8x", size, address);
if (((address % 2) == 0) && (size == 2))
{
@@ -921,7 +921,7 @@ int target_checksum_memory(struct target_s *target, u32 address, u32 size, u32*
buffer = malloc(size);
if (buffer == NULL)
{
ERROR("error allocating buffer for section (%d bytes)", size);
LOG_ERROR("error allocating buffer for section (%d bytes)", size);
return ERROR_INVALID_ARGUMENTS;
}
retval = target_read_buffer(target, address, size, buffer);
@@ -957,12 +957,12 @@ int target_read_u32(struct target_s *target, u32 address, u32 *value)
if (retval == ERROR_OK)
{
*value = target_buffer_get_u32(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
LOG_DEBUG("address: 0x%8.8x failed", address);
}
return retval;
@@ -977,12 +977,12 @@ int target_read_u16(struct target_s *target, u32 address, u16 *value)
if (retval == ERROR_OK)
{
*value = target_buffer_get_u16(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
LOG_DEBUG("address: 0x%8.8x failed", address);
}
return retval;
@@ -994,12 +994,12 @@ int target_read_u8(struct target_s *target, u32 address, u8 *value)
if (retval == ERROR_OK)
{
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
LOG_DEBUG("address: 0x%8.8x failed", address);
}
return retval;
@@ -1010,12 +1010,12 @@ int target_write_u32(struct target_s *target, u32 address, u32 value)
int retval;
u8 value_buf[4];
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u32(target, value_buf, value);
if ((retval = target->type->write_memory(target, address, 4, 1, value_buf)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
LOG_DEBUG("failed: %i", retval);
}
return retval;
@@ -1026,12 +1026,12 @@ int target_write_u16(struct target_s *target, u32 address, u16 value)
int retval;
u8 value_buf[2];
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u16(target, value_buf, value);
if ((retval = target->type->write_memory(target, address, 2, 1, value_buf)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
LOG_DEBUG("failed: %i", retval);
}
return retval;
@@ -1041,11 +1041,11 @@ int target_write_u8(struct target_s *target, u32 address, u8 value)
{
int retval;
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
LOG_DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
if ((retval = target->type->read_memory(target, address, 1, 1, &value)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
LOG_DEBUG("failed: %i", retval);
}
return retval;
@@ -1141,7 +1141,7 @@ int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
/* register target specific commands */
if (target_types[i]->register_commands(cmd_ctx) != ERROR_OK)
{
ERROR("couldn't register '%s' commands", args[0]);
LOG_ERROR("couldn't register '%s' commands", args[0]);
exit(-1);
}
@@ -1162,7 +1162,7 @@ int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
(*last_target_p)->endianness = TARGET_LITTLE_ENDIAN;
else
{
ERROR("endianness must be either 'little' or 'big', not '%s'", args[1]);
LOG_ERROR("endianness must be either 'little' or 'big', not '%s'", args[1]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1179,7 +1179,7 @@ int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
(*last_target_p)->reset_mode = RESET_RUN_AND_INIT;
else
{
ERROR("unknown target startup mode %s", args[2]);
LOG_ERROR("unknown target startup mode %s", args[2]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
(*last_target_p)->run_and_halt_time = 1000; /* default 1s */
@@ -1226,7 +1226,7 @@ int handle_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
/* no matching target found */
if (!found)
{
ERROR("target '%s' not found", args[0]);
LOG_ERROR("target '%s' not found", args[0]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1240,7 +1240,7 @@ int handle_target_script_command(struct command_context_s *cmd_ctx, char *cmd, c
if (argc < 3)
{
ERROR("incomplete target_script command");
LOG_ERROR("incomplete target_script command");
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1277,7 +1277,7 @@ int handle_target_script_command(struct command_context_s *cmd_ctx, char *cmd, c
}
else
{
ERROR("unknown event type: '%s", args[1]);
LOG_ERROR("unknown event type: '%s", args[1]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1337,7 +1337,7 @@ int handle_working_area_command(struct command_context_s *cmd_ctx, char *cmd, ch
}
else
{
ERROR("unrecognized <backup|nobackup> argument (%s)", args[3]);
LOG_ERROR("unrecognized <backup|nobackup> argument (%s)", args[3]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1359,7 +1359,7 @@ int handle_target(void *priv)
if (target_continous_poll)
if ((retval = target->type->poll(target)) != ERROR_OK)
{
ERROR("couldn't poll target(%d). It's due for a reset.", retval);
LOG_ERROR("couldn't poll target(%d). It's due for a reset.", retval);
}
}
@@ -1376,7 +1376,7 @@ int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args
int count = 0;
char *value;
DEBUG("-");
LOG_DEBUG("-");
target = get_current_target(cmd_ctx);
@@ -1451,7 +1451,7 @@ int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args
reg_arch_type_t *arch_type = register_get_arch_type(reg->arch_type);
if (arch_type == NULL)
{
ERROR("BUG: encountered unregistered arch type");
LOG_ERROR("BUG: encountered unregistered arch type");
return ERROR_OK;
}
arch_type->get(reg);
@@ -1471,7 +1471,7 @@ int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char **args
reg_arch_type_t *arch_type = register_get_arch_type(reg->arch_type);
if (arch_type == NULL)
{
ERROR("BUG: encountered unregistered arch type");
LOG_ERROR("BUG: encountered unregistered arch type");
return ERROR_OK;
}
@@ -1575,7 +1575,7 @@ static int wait_state(struct command_context_s *cmd_ctx, char *cmd, enum target_
gettimeofday(&now, NULL);
if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec) && (now.tv_usec >= timeout.tv_usec)))
{
ERROR("timed out while waiting for target %s", target_state_strings[state]);
LOG_ERROR("timed out while waiting for target %s", target_state_strings[state]);
break;
}
}
@@ -1588,7 +1588,7 @@ int handle_halt_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
int retval;
target_t *target = get_current_target(cmd_ctx);
DEBUG("-");
LOG_DEBUG("-");
if ((retval = target->type->halt(target)) != ERROR_OK)
{
@@ -1615,7 +1615,7 @@ int handle_daemon_startup_command(struct command_context_s *cmd_ctx, char *cmd,
}
}
WARNING("invalid daemon_startup configuration directive: %s", args[0]);
LOG_WARNING("invalid daemon_startup configuration directive: %s", args[0]);
return ERROR_OK;
}
@@ -1624,7 +1624,7 @@ int handle_soft_reset_halt_command(struct command_context_s *cmd_ctx, char *cmd,
{
target_t *target = get_current_target(cmd_ctx);
USER("requesting target halt and executing a soft reset");
LOG_USER("requesting target halt and executing a soft reset");
target->type->soft_reset_halt(target);
@@ -1637,7 +1637,7 @@ int handle_reset_command(struct command_context_s *cmd_ctx, char *cmd, char **ar
enum target_reset_mode reset_mode = target->reset_mode;
enum target_reset_mode save = target->reset_mode;
DEBUG("-");
LOG_DEBUG("-");
if (argc >= 1)
{
@@ -1705,7 +1705,7 @@ int handle_step_command(struct command_context_s *cmd_ctx, char *cmd, char **arg
{
target_t *target = get_current_target(cmd_ctx);
DEBUG("-");
LOG_DEBUG("-");
if (argc == 0)
target->type->step(target, 1, 0, 1); /* current pc, addr = 0, handle breakpoints */
@@ -1789,7 +1789,7 @@ int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char **args,
}
} else
{
ERROR("Failure examining memory");
LOG_ERROR("Failure examining memory");
}
free(buffer);
@@ -1830,7 +1830,7 @@ int handle_mw_command(struct command_context_s *cmd_ctx, char *cmd, char **args,
}
if (retval!=ERROR_OK)
{
ERROR("Failure examining memory");
LOG_ERROR("Failure examining memory");
}
return ERROR_OK;
@@ -2012,7 +2012,7 @@ int handle_verify_image_command(struct command_context_s *cmd_ctx, char *cmd, ch
if (!target)
{
ERROR("no target selected");
LOG_ERROR("no target selected");
return ERROR_OK;
}
@@ -2152,7 +2152,7 @@ int handle_bp_command(struct command_context_s *cmd_ctx, char *cmd, char **args,
if ((retval = breakpoint_add(target, strtoul(args[0], NULL, 0), length, hw)) != ERROR_OK)
{
ERROR("Failure setting breakpoints");
LOG_ERROR("Failure setting breakpoints");
}
else
{
@@ -2228,7 +2228,7 @@ int handle_wp_command(struct command_context_s *cmd_ctx, char *cmd, char **args,
if ((retval = watchpoint_add(target, strtoul(args[0], NULL, 0),
strtoul(args[1], NULL, 0), type, data_value, data_mask)) != ERROR_OK)
{
ERROR("Failure setting breakpoints");
LOG_ERROR("Failure setting breakpoints");
}
}
else

10
src/target/target_request.c
View File

@@ -42,7 +42,7 @@ int target_asciimsg(target_t *target, u32 length)
target->type->target_request_data(target, CEIL(length, 4), (u8*)msg);
msg[length] = 0;
DEBUG("%s", msg);
LOG_DEBUG("%s", msg);
while (c)
{
@@ -55,7 +55,7 @@ int target_asciimsg(target_t *target, u32 length)
int target_charmsg(target_t *target, u8 msg)
{
USER_N("%c", msg);
LOG_USER_N("%c", msg);
return ERROR_OK;
}
@@ -68,7 +68,7 @@ int target_hexmsg(target_t *target, int size, u32 length)
debug_msg_receiver_t *c = target->dbgmsg;
int i;
DEBUG("size: %i, length: %i", size, length);
LOG_DEBUG("size: %i, length: %i", size, length);
target->type->target_request_data(target, CEIL(length * size, 4), (u8*)data);
@@ -90,7 +90,7 @@ int target_hexmsg(target_t *target, int size, u32 length)
if ((i%8 == 7) || (i == length - 1))
{
DEBUG("%s", line);
LOG_DEBUG("%s", line);
while (c)
{
@@ -136,7 +136,7 @@ int target_request(target_t *target, u32 request)
* break;
*/
default:
ERROR("unknown target request: %2.2x", target_req_cmd);
LOG_ERROR("unknown target request: %2.2x", target_req_cmd);
break;
}

2
src/target/trace.c
View File

@@ -35,7 +35,7 @@ int trace_point(target_t *target, int number)
{
trace_t *trace = target->trace_info;
DEBUG("tracepoint: %i", number);
LOG_DEBUG("tracepoint: %i", number);
if (number < trace->num_trace_points)
trace->trace_points[number].hit_counter++;

204
src/target/xscale.c
View File

@@ -194,13 +194,13 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("target isn't an XScale target");
LOG_ERROR("target isn't an XScale target");
return -1;
}
if (xscale->common_magic != XSCALE_COMMON_MAGIC)
{
ERROR("target isn't an XScale target");
LOG_ERROR("target isn't an XScale target");
return -1;
}
@@ -283,7 +283,7 @@ int xscale_read_dcsr(target_t *target)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while reading DCSR");
LOG_ERROR("JTAG error while reading DCSR");
return retval;
}
@@ -382,7 +382,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while receiving data from debug handler");
LOG_ERROR("JTAG error while receiving data from debug handler");
break;
}
@@ -405,7 +405,7 @@ int xscale_receive(target_t *target, u32 *buffer, int num_words)
{
if (attempts++==1000)
{
ERROR("Failed to receiving data from debug handler after 1000 attempts");
LOG_ERROR("Failed to receiving data from debug handler after 1000 attempts");
retval=ERROR_TARGET_TIMEOUT;
break;
}
@@ -503,14 +503,14 @@ int xscale_read_tx(target_t *target, int consume)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while reading TX");
LOG_ERROR("JTAG error while reading TX");
return ERROR_TARGET_TIMEOUT;
}
gettimeofday(&now, NULL);
if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
{
ERROR("time out reading TX register");
LOG_ERROR("time out reading TX register");
return ERROR_TARGET_TIMEOUT;
}
if (!((!(field0_in & 1)) && consume))
@@ -518,7 +518,7 @@ int xscale_read_tx(target_t *target, int consume)
goto done;
}
}
DEBUG("waiting 10ms");
LOG_DEBUG("waiting 10ms");
usleep(10*1000); /* avoid flooding the logs */
}
done:
@@ -580,7 +580,7 @@ int xscale_write_rx(target_t *target)
timeval_add_time(&timeout, 1, 0);
/* poll until rx_read is low */
DEBUG("polling RX");
LOG_DEBUG("polling RX");
for (;;)
{
int i;
@@ -590,20 +590,20 @@ int xscale_write_rx(target_t *target)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while writing RX");
LOG_ERROR("JTAG error while writing RX");
return retval;
}
gettimeofday(&now, NULL);
if ((now.tv_sec > timeout.tv_sec) || ((now.tv_sec == timeout.tv_sec)&& (now.tv_usec > timeout.tv_usec)))
{
ERROR("time out writing RX register");
LOG_ERROR("time out writing RX register");
return ERROR_TARGET_TIMEOUT;
}
if (!(field0_in & 1))
goto done;
}
DEBUG("waiting 10ms");
LOG_DEBUG("waiting 10ms");
usleep(10*1000); /* wait 10ms to avoid flooding the logs */
}
done:
@@ -614,7 +614,7 @@ int xscale_write_rx(target_t *target)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while writing RX");
LOG_ERROR("JTAG error while writing RX");
return retval;
}
@@ -716,7 +716,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
output[0] = *buffer;
break;
default:
ERROR("BUG: size neither 4, 2 nor 1");
LOG_ERROR("BUG: size neither 4, 2 nor 1");
exit(-1);
}
@@ -728,7 +728,7 @@ int xscale_send(target_t *target, u8 *buffer, int count, int size)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while sending data to debug handler");
LOG_ERROR("JTAG error while sending data to debug handler");
return retval;
}
@@ -801,7 +801,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
ERROR("JTAG error while writing DCSR");
LOG_ERROR("JTAG error while writing DCSR");
return retval;
}
@@ -819,7 +819,7 @@ unsigned int parity (unsigned int v)
v ^= v >> 8;
v ^= v >> 4;
v &= 0xf;
DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
return (0x6996 >> v) & 1;
}
@@ -833,7 +833,7 @@ int xscale_load_ic(target_t *target, int mini, u32 va, u32 buffer[8])
scan_field_t fields[2];
DEBUG("loading miniIC at 0x%8.8x", va);
LOG_DEBUG("loading miniIC at 0x%8.8x", va);
jtag_add_end_state(TAP_RTI);
xscale_jtag_set_instr(xscale->jtag_info.chain_pos, xscale->jtag_info.ldic); /* LDIC */
@@ -1014,11 +1014,11 @@ int xscale_arch_state(struct target_s *target)
if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
{
ERROR("BUG: called for a non-ARMv4/5 target");
LOG_ERROR("BUG: called for a non-ARMv4/5 target");
exit(-1);
}
USER("target halted in %s state due to %s, current mode: %s\n"
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"cpsr: 0x%8.8x pc: 0x%8.8x\n"
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
@@ -1057,7 +1057,7 @@ int xscale_poll(target_t *target)
}
else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
USER("error while polling TX register, reset CPU");
LOG_USER("error while polling TX register, reset CPU");
/* here we "lie" so GDB won't get stuck and a reset can be perfomed */
target->state = TARGET_HALTED;
}
@@ -1103,13 +1103,13 @@ int xscale_debug_entry(target_t *target)
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_cache->reg_list[15].valid = 1;
DEBUG("r0: 0x%8.8x", buffer[0]);
LOG_DEBUG("r0: 0x%8.8x", buffer[0]);
/* move pc from buffer to register cache */
buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, buffer[1]);
armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_cache->reg_list[15].valid = 1;
DEBUG("pc: 0x%8.8x", buffer[1]);
LOG_DEBUG("pc: 0x%8.8x", buffer[1]);
/* move data from buffer to register cache */
for (i = 1; i <= 7; i++)
@@ -1117,22 +1117,22 @@ int xscale_debug_entry(target_t *target)
buf_set_u32(armv4_5->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
armv4_5->core_cache->reg_list[i].dirty = 1;
armv4_5->core_cache->reg_list[i].valid = 1;
DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
LOG_DEBUG("r%i: 0x%8.8x", i, buffer[i + 1]);
}
buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, buffer[9]);
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 1;
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
DEBUG("cpsr: 0x%8.8x", buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8x", buffer[9]);
armv4_5->core_mode = buffer[9] & 0x1f;
if (armv4_5_mode_to_number(armv4_5->core_mode) == -1)
{
target->state = TARGET_UNKNOWN;
ERROR("cpsr contains invalid mode value - communication failure");
LOG_ERROR("cpsr contains invalid mode value - communication failure");
return ERROR_TARGET_FAILURE;
}
DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
LOG_DEBUG("target entered debug state in %s mode", armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)]);
if (buffer[9] & 0x20)
armv4_5->core_state = ARMV4_5_STATE_THUMB;
@@ -1207,7 +1207,7 @@ int xscale_debug_entry(target_t *target)
break;
case 0x7: /* Reserved */
default:
ERROR("Method of Entry is 'Reserved'");
LOG_ERROR("Method of Entry is 'Reserved'");
exit(-1);
break;
}
@@ -1261,22 +1261,22 @@ int xscale_halt(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
if (target->state == TARGET_HALTED)
{
WARNING("target was already halted");
LOG_WARNING("target was already halted");
return ERROR_OK;
}
else if (target->state == TARGET_UNKNOWN)
{
/* this must not happen for a xscale target */
ERROR("target was in unknown state when halt was requested");
LOG_ERROR("target was in unknown state when halt was requested");
return ERROR_TARGET_INVALID;
}
else if (target->state == TARGET_RESET)
{
DEBUG("target->state == TARGET_RESET");
LOG_DEBUG("target->state == TARGET_RESET");
}
else
{
@@ -1306,7 +1306,7 @@ int xscale_enable_single_step(struct target_s *target, u32 next_pc)
}
else
{
ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
LOG_ERROR("BUG: xscale->ibcr0_used is set, but no breakpoint with that address found");
exit(-1);
}
}
@@ -1338,11 +1338,11 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_
int retval;
int i;
DEBUG("-");
LOG_DEBUG("-");
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1376,7 +1376,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_
u32 next_pc;
/* there's a breakpoint at the current PC, we have to step over it */
DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
xscale_unset_breakpoint(target, breakpoint);
/* calculate PC of next instruction */
@@ -1384,10 +1384,10 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_
{
u32 current_opcode;
target_read_u32(target, current_pc, &current_opcode);
ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
}
DEBUG("enable single-step");
LOG_DEBUG("enable single-step");
xscale_enable_single_step(target, next_pc);
/* restore banked registers */
@@ -1405,26 +1405,26 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_
/* send CPSR */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
/* wait for and process debug entry */
xscale_debug_entry(target);
DEBUG("disable single-step");
LOG_DEBUG("disable single-step");
xscale_disable_single_step(target);
DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
xscale_set_breakpoint(target, breakpoint);
}
}
@@ -1448,18 +1448,18 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_
/* send CPSR */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target->debug_reason = DBG_REASON_NOTHALTED;
@@ -1476,7 +1476,7 @@ int xscale_resume(struct target_s *target, int current, u32 address, int handle_
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
}
DEBUG("target resumed");
LOG_DEBUG("target resumed");
xscale->handler_running = 1;
@@ -1495,7 +1495,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1531,10 +1531,10 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br
{
u32 current_opcode;
target_read_u32(target, current_pc, &current_opcode);
ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
}
DEBUG("enable single-step");
LOG_DEBUG("enable single-step");
xscale_enable_single_step(target, next_pc);
/* restore banked registers */
@@ -1552,18 +1552,18 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br
/* send CPSR */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
for (i = 7; i >= 0; i--)
{
/* send register */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8x", i, buf_get_u32(armv4_5->core_cache->reg_list[i].value, 0, 32));
}
/* send PC */
xscale_send_u32(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
@@ -1573,7 +1573,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br
/* wait for and process debug entry */
xscale_debug_entry(target);
DEBUG("disable single-step");
LOG_DEBUG("disable single-step");
xscale_disable_single_step(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
@@ -1583,7 +1583,7 @@ int xscale_step(struct target_s *target, int current, u32 address, int handle_br
xscale_set_breakpoint(target, breakpoint);
}
DEBUG("target stepped");
LOG_DEBUG("target stepped");
return ERROR_OK;
@@ -1594,7 +1594,7 @@ int xscale_assert_reset(target_t *target)
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
DEBUG("target->state: %s", target_state_strings[target->state]);
LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
/* TRST every time. We want to be able to support daemon_startup attach */
jtag_add_reset(1, 0);
@@ -1647,7 +1647,7 @@ int xscale_deassert_reset(target_t *target)
breakpoint_t *breakpoint = target->breakpoints;
DEBUG("-");
LOG_DEBUG("-");
xscale->ibcr_available = 2;
xscale->ibcr0_used = 0;
@@ -1691,13 +1691,13 @@ int xscale_deassert_reset(target_t *target)
if ((binary_size = debug_handler.size) % 4)
{
ERROR("debug_handler.bin: size not a multiple of 4");
LOG_ERROR("debug_handler.bin: size not a multiple of 4");
exit(-1);
}
if (binary_size > 0x800)
{
ERROR("debug_handler.bin: larger than 2kb");
LOG_ERROR("debug_handler.bin: larger than 2kb");
exit(-1);
}
@@ -1808,11 +1808,11 @@ int xscale_full_context(target_t *target)
int i, j;
DEBUG("-");
LOG_DEBUG("-");
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1882,11 +1882,11 @@ int xscale_restore_context(target_t *target)
int i, j;
DEBUG("-");
LOG_DEBUG("-");
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1953,11 +1953,11 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count
int i;
int retval;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2002,7 +2002,7 @@ int xscale_read_memory(struct target_s *target, u32 address, u32 size, u32 count
*buffer++ = buf32[i] & 0xff;
break;
default:
ERROR("should never get here");
LOG_ERROR("should never get here");
exit(-1);
}
}
@@ -2030,11 +2030,11 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
xscale_common_t *xscale = armv4_5->arch_info;
int retval;
DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2079,7 +2079,7 @@ int xscale_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
buffer += 1;
break;
default:
ERROR("should never get here");
LOG_ERROR("should never get here");
exit(-1);
}
}
@@ -2196,7 +2196,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2205,7 +2205,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (breakpoint->set)
{
WARNING("breakpoint already set");
LOG_WARNING("breakpoint already set");
return ERROR_OK;
}
@@ -2226,7 +2226,7 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
}
else
{
ERROR("BUG: no hardware comparator available");
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_OK;
}
}
@@ -2260,19 +2260,19 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (xscale->force_hw_bkpts)
{
DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
LOG_DEBUG("forcing use of hardware breakpoint at address 0x%8.8x", breakpoint->address);
breakpoint->type = BKPT_HARD;
}
if ((breakpoint->type == BKPT_HARD) && (xscale->ibcr_available < 1))
{
INFO("no breakpoint unit available for hardware breakpoint");
LOG_INFO("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
else
@@ -2282,7 +2282,7 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if ((breakpoint->length != 2) && (breakpoint->length != 4))
{
INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
LOG_INFO("only breakpoints of two (Thumb) or four (ARM) bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -2296,13 +2296,13 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!breakpoint->set)
{
WARNING("breakpoint not set");
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
@@ -2344,7 +2344,7 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2369,7 +2369,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2387,7 +2387,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
enable = 0x1;
break;
default:
ERROR("BUG: watchpoint->rw neither read, write nor access");
LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
}
if (!xscale->dbr0_used)
@@ -2408,7 +2408,7 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
}
else
{
ERROR("BUG: no hardware comparator available");
LOG_ERROR("BUG: no hardware comparator available");
return ERROR_OK;
}
@@ -2422,7 +2422,7 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2450,13 +2450,13 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if (!watchpoint->set)
{
WARNING("breakpoint not set");
LOG_WARNING("breakpoint not set");
return ERROR_OK;
}
@@ -2484,7 +2484,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
if (target->state != TARGET_HALTED)
{
WARNING("target not halted");
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2662,7 +2662,7 @@ int xscale_read_trace(target_t *target)
if (target->state != TARGET_HALTED)
{
WARNING("target must be stopped to read trace data");
LOG_WARNING("target must be stopped to read trace data");
return ERROR_TARGET_NOT_HALTED;
}
@@ -2697,7 +2697,7 @@ int xscale_read_trace(target_t *target)
if (j == 256)
{
DEBUG("no trace data collected");
LOG_DEBUG("no trace data collected");
return ERROR_XSCALE_NO_TRACE_DATA;
}
@@ -2762,7 +2762,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
4, buf, &size_read)) != ERROR_OK)
{
ERROR("error while reading instruction: %i", retval);
LOG_ERROR("error while reading instruction: %i", retval);
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
opcode = target_buffer_get_u32(target, buf);
@@ -2775,7 +2775,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
xscale->trace.current_pc - xscale->trace.image->sections[section].base_address,
2, buf, &size_read)) != ERROR_OK)
{
ERROR("error while reading instruction: %i", retval);
LOG_ERROR("error while reading instruction: %i", retval);
return ERROR_TRACE_INSTRUCTION_UNAVAILABLE;
}
opcode = target_buffer_get_u16(target, buf);
@@ -2783,7 +2783,7 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
}
else
{
ERROR("BUG: unknown core state encountered");
LOG_ERROR("BUG: unknown core state encountered");
exit(-1);
}
@@ -2866,7 +2866,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
next_pc_ok = 1;
if (((chkpt == 0) && (next_pc != trace_data->chkpt0))
|| ((chkpt == 1) && (next_pc != trace_data->chkpt1)))
WARNING("checkpointed indirect branch target address doesn't match checkpoint");
LOG_WARNING("checkpointed indirect branch target address doesn't match checkpoint");
}
/* explicit fall-through */
case 12: /* Checkpointed Direct Branch */
@@ -2885,7 +2885,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
}
else
{
WARNING("more than two checkpointed branches encountered");
LOG_WARNING("more than two checkpointed branches encountered");
}
break;
case 15: /* Roll-over */
@@ -2893,7 +2893,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
continue;
default: /* Reserved */
command_print(cmd_ctx, "--- reserved trace message ---");
ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
LOG_ERROR("BUG: trace message %i is reserved", (trace_data->entries[i].data & 0xf0) >> 4);
return ERROR_OK;
}
@@ -3172,7 +3172,7 @@ int xscale_target_command(struct command_context_s *cmd_ctx, char *cmd, char **a
if (argc < 5)
{
ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
LOG_ERROR("'target xscale' requires four arguments: <endianess> <startup_mode> <chain_pos> <variant>");
return ERROR_OK;
}
@@ -3196,13 +3196,13 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char
if (argc < 2)
{
ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
LOG_ERROR("'xscale debug_handler <target#> <address>' command takes two required operands");
return ERROR_OK;
}
if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
{
ERROR("no target '%s' configured", args[0]);
LOG_ERROR("no target '%s' configured", args[0]);
return ERROR_OK;
}
@@ -3220,7 +3220,7 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char
}
else
{
ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
LOG_ERROR("xscale debug_handler <address> must be between 0x800 and 0x1fef800 or between 0xfe000800 and 0xfffff800");
}
return ERROR_OK;
@@ -3236,13 +3236,13 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
if (argc < 2)
{
ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
LOG_ERROR("'xscale cache_clean_address <target#> <address>' command takes two required operands");
return ERROR_OK;
}
if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
{
ERROR("no target '%s' configured", args[0]);
LOG_ERROR("no target '%s' configured", args[0]);
return ERROR_OK;
}
@@ -3255,7 +3255,7 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
if (cache_clean_address & 0xffff)
{
ERROR("xscale cache_clean_address <address> must be 64kb aligned");
LOG_ERROR("xscale cache_clean_address <address> must be 64kb aligned");
}
else
{
@@ -3310,7 +3310,7 @@ static int xscale_mmu(struct target_s *target, int *enabled)
if (target->state != TARGET_HALTED)
{
ERROR("Target not halted");
LOG_ERROR("Target not halted");
return ERROR_TARGET_INVALID;
}
*enabled = xscale->armv4_5_mmu.mmu_enabled;