Share trigger code between 0.11 and 0.13 code.
The actual implementation of triggers didn't change between those two versions, so there's no need to duplicate the code. In the process, I also fixed a minor multicore bug where tselect didn't always get written on all harts.
This commit is contained in:
Tim Newsome
+327
-21
@@ -248,6 +248,7 @@ static int riscv_init_target(struct command_context *cmd_ctx,
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if (!target->arch_info)
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return ERROR_FAIL;
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riscv_info_t *info = (riscv_info_t *) target->arch_info;
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riscv_info_init(target, info);
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info->cmd_ctx = cmd_ctx;
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select_dtmcontrol.num_bits = target->tap->ir_length;
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@@ -273,32 +274,329 @@ static int oldriscv_halt(struct target *target)
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return tt->halt(target);
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}
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static int riscv_add_breakpoint(struct target *target,
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struct breakpoint *breakpoint)
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static void trigger_from_breakpoint(struct trigger *trigger,
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const struct breakpoint *breakpoint)
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{
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struct target_type *tt = get_target_type(target);
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return tt->add_breakpoint(target, breakpoint);
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trigger->address = breakpoint->address;
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trigger->length = breakpoint->length;
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trigger->mask = ~0LL;
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trigger->read = false;
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trigger->write = false;
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trigger->execute = true;
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// unique_id is unique across both breakpoints and watchpoints.
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trigger->unique_id = breakpoint->unique_id;
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}
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static int riscv_remove_breakpoint(struct target *target,
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static int maybe_add_trigger_t1(struct target *target, unsigned hartid,
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struct trigger *trigger, uint64_t tdata1)
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{
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RISCV_INFO(r);
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const uint32_t bpcontrol_x = 1<<0;
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const uint32_t bpcontrol_w = 1<<1;
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const uint32_t bpcontrol_r = 1<<2;
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const uint32_t bpcontrol_u = 1<<3;
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const uint32_t bpcontrol_s = 1<<4;
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const uint32_t bpcontrol_h = 1<<5;
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const uint32_t bpcontrol_m = 1<<6;
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const uint32_t bpcontrol_bpmatch = 0xf << 7;
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const uint32_t bpcontrol_bpaction = 0xff << 11;
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if (tdata1 & (bpcontrol_r | bpcontrol_w | bpcontrol_x)) {
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// Trigger is already in use, presumably by user code.
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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tdata1 = set_field(tdata1, bpcontrol_r, trigger->read);
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tdata1 = set_field(tdata1, bpcontrol_w, trigger->write);
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tdata1 = set_field(tdata1, bpcontrol_x, trigger->execute);
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tdata1 = set_field(tdata1, bpcontrol_u, !!(r->misa & (1 << ('U' - 'A'))));
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tdata1 = set_field(tdata1, bpcontrol_s, !!(r->misa & (1 << ('S' - 'A'))));
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tdata1 = set_field(tdata1, bpcontrol_h, !!(r->misa & (1 << ('H' - 'A'))));
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tdata1 |= bpcontrol_m;
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tdata1 = set_field(tdata1, bpcontrol_bpmatch, 0); // exact match
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tdata1 = set_field(tdata1, bpcontrol_bpaction, 0); // cause bp exception
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
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riscv_reg_t tdata1_rb = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TDATA1);
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
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PRIx64 " to tdata1 it contains 0x%" PRIx64,
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tdata1, tdata1_rb);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
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return ERROR_OK;
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}
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static int maybe_add_trigger_t2(struct target *target, unsigned hartid,
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struct trigger *trigger, uint64_t tdata1)
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{
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RISCV_INFO(r);
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// tselect is already set
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if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
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// Trigger is already in use, presumably by user code.
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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// address/data match trigger
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tdata1 |= MCONTROL_DMODE(riscv_xlen(target));
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tdata1 = set_field(tdata1, MCONTROL_ACTION,
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MCONTROL_ACTION_DEBUG_MODE);
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tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
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tdata1 |= MCONTROL_M;
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if (r->misa & (1 << ('H' - 'A')))
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tdata1 |= MCONTROL_H;
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if (r->misa & (1 << ('S' - 'A')))
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tdata1 |= MCONTROL_S;
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if (r->misa & (1 << ('U' - 'A')))
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tdata1 |= MCONTROL_U;
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if (trigger->execute)
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tdata1 |= MCONTROL_EXECUTE;
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if (trigger->read)
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tdata1 |= MCONTROL_LOAD;
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if (trigger->write)
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tdata1 |= MCONTROL_STORE;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, tdata1);
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uint64_t tdata1_rb = riscv_get_register_on_hart(target, hartid, GDB_REGNO_TDATA1);
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LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
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if (tdata1 != tdata1_rb) {
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LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%"
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PRIx64 " to tdata1 it contains 0x%" PRIx64,
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tdata1, tdata1_rb);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA2, trigger->address);
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return ERROR_OK;
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}
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static int add_trigger(struct target *target, struct trigger *trigger)
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{
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RISCV_INFO(r);
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riscv_reg_t tselect[RISCV_MAX_HARTS];
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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tselect[hartid] = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TSELECT);
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}
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unsigned int i;
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for (i = 0; i < r->trigger_count[0]; i++) {
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if (r->trigger_unique_id[i] != -1) {
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continue;
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}
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riscv_set_register_on_hart(target, 0, GDB_REGNO_TSELECT, i);
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uint64_t tdata1 = riscv_get_register_on_hart(target, 0, GDB_REGNO_TDATA1);
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int type = get_field(tdata1, MCONTROL_TYPE(riscv_xlen(target)));
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int result = ERROR_OK;
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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if (hartid > 0) {
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
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}
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switch (type) {
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case 1:
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result = maybe_add_trigger_t1(target, hartid, trigger, tdata1);
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break;
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case 2:
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result = maybe_add_trigger_t2(target, hartid, trigger, tdata1);
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break;
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default:
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LOG_DEBUG("trigger %d has unknown type %d", i, type);
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continue;
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}
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if (result != ERROR_OK) {
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continue;
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}
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}
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if (result != ERROR_OK) {
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continue;
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}
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LOG_DEBUG("Using resource %d for bp %d", i,
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trigger->unique_id);
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r->trigger_unique_id[i] = trigger->unique_id;
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break;
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}
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT,
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tselect[hartid]);
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}
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if (i >= r->trigger_count[0]) {
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LOG_ERROR("Couldn't find an available hardware trigger.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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return ERROR_OK;
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}
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int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
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{
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if (breakpoint->type == BKPT_SOFT) {
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if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
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breakpoint->orig_instr) != ERROR_OK) {
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LOG_ERROR("Failed to read original instruction at 0x%" TARGET_PRIxADDR,
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breakpoint->address);
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return ERROR_FAIL;
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}
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int retval;
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if (breakpoint->length == 4) {
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retval = target_write_u32(target, breakpoint->address, ebreak());
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} else {
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retval = target_write_u16(target, breakpoint->address, ebreak_c());
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}
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%"
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TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
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return ERROR_FAIL;
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}
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} else if (breakpoint->type == BKPT_HARD) {
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struct trigger trigger;
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trigger_from_breakpoint(&trigger, breakpoint);
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int result = add_trigger(target, &trigger);
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if (result != ERROR_OK) {
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return result;
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}
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} else {
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LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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breakpoint->set = true;
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return ERROR_OK;
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}
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static int remove_trigger(struct target *target, struct trigger *trigger)
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{
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RISCV_INFO(r);
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unsigned int i;
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for (i = 0; i < r->trigger_count[0]; i++) {
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if (r->trigger_unique_id[i] == trigger->unique_id) {
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break;
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}
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}
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if (i >= r->trigger_count[0]) {
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LOG_ERROR("Couldn't find the hardware resources used by hardware "
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"trigger.");
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return ERROR_FAIL;
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}
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LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
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for (int hartid = 0; hartid < riscv_count_harts(target); ++hartid) {
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_reg_t tselect = riscv_get_register_on_hart(target, hartid, GDB_REGNO_TSELECT);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, i);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TDATA1, 0);
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
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}
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r->trigger_unique_id[i] = -1;
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return ERROR_OK;
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}
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int riscv_remove_breakpoint(struct target *target,
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struct breakpoint *breakpoint)
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{
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struct target_type *tt = get_target_type(target);
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return tt->remove_breakpoint(target, breakpoint);
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if (breakpoint->type == BKPT_SOFT) {
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if (target_write_memory(target, breakpoint->address, breakpoint->length, 1,
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breakpoint->orig_instr) != ERROR_OK) {
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LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
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"0x%" TARGET_PRIxADDR, breakpoint->length, breakpoint->address);
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return ERROR_FAIL;
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}
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} else if (breakpoint->type == BKPT_HARD) {
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struct trigger trigger;
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trigger_from_breakpoint(&trigger, breakpoint);
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int result = remove_trigger(target, &trigger);
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if (result != ERROR_OK) {
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return result;
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}
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} else {
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LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
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return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
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}
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breakpoint->set = false;
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return ERROR_OK;
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}
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static int riscv_add_watchpoint(struct target *target,
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struct watchpoint *watchpoint)
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static void trigger_from_watchpoint(struct trigger *trigger,
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const struct watchpoint *watchpoint)
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{
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struct target_type *tt = get_target_type(target);
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return tt->add_watchpoint(target, watchpoint);
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trigger->address = watchpoint->address;
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trigger->length = watchpoint->length;
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trigger->mask = watchpoint->mask;
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trigger->value = watchpoint->value;
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trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
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trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
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trigger->execute = false;
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// unique_id is unique across both breakpoints and watchpoints.
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trigger->unique_id = watchpoint->unique_id;
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}
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static int riscv_remove_watchpoint(struct target *target,
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int riscv_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
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{
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struct trigger trigger;
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trigger_from_watchpoint(&trigger, watchpoint);
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int result = add_trigger(target, &trigger);
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if (result != ERROR_OK) {
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return result;
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}
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watchpoint->set = true;
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return ERROR_OK;
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}
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int riscv_remove_watchpoint(struct target *target,
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struct watchpoint *watchpoint)
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{
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struct target_type *tt = get_target_type(target);
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return tt->remove_watchpoint(target, watchpoint);
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struct trigger trigger;
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trigger_from_watchpoint(&trigger, watchpoint);
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int result = remove_trigger(target, &trigger);
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if (result != ERROR_OK) {
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return result;
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}
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watchpoint->set = false;
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return ERROR_OK;
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}
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static int oldriscv_step(struct target *target, int current, uint32_t address,
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@@ -880,6 +1178,8 @@ void riscv_info_init(struct target *target, riscv_info_t *r)
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r->registers_initialized = false;
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r->current_hartid = target->coreid;
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memset(r->trigger_unique_id, 0xff, sizeof(r->trigger_unique_id));
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for (size_t h = 0; h < RISCV_MAX_HARTS; ++h) {
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r->xlen[h] = -1;
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r->debug_buffer_addr[h] = -1;
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@@ -1033,7 +1333,6 @@ void riscv_set_current_hartid(struct target *target, int hartid)
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&& (!riscv_rtos_enabled(target) || (previous_hartid == hartid))
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&& target->reg_cache->reg_list[GDB_REGNO_XPR0].size == (unsigned)riscv_xlen(target)
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&& (!riscv_rtos_enabled(target) || (r->rtos_hartid != -1))) {
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LOG_DEBUG("registers already initialized, skipping");
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return;
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} else
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LOG_DEBUG("Initializing registers: xlen=%d", riscv_xlen(target));
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@@ -1107,7 +1406,7 @@ void riscv_set_register_on_hart(struct target *target, int hartid,
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enum gdb_regno regid, uint64_t value)
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{
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RISCV_INFO(r);
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LOG_DEBUG("[%d] reg[%d] <- %" PRIx64, hartid, regid, value);
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LOG_DEBUG("[%d] reg[0x%x] <- %" PRIx64, hartid, regid, value);
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assert(r->set_register);
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return r->set_register(target, hartid, regid, value);
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}
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@@ -1120,13 +1419,15 @@ riscv_reg_t riscv_get_register(struct target *target, enum gdb_regno r)
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uint64_t riscv_get_register_on_hart(struct target *target, int hartid, enum gdb_regno regid)
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{
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RISCV_INFO(r);
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LOG_DEBUG("reading register %d on hart %d", regid, hartid);
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return r->get_register(target, hartid, regid);
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uint64_t value = r->get_register(target, hartid, regid);
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LOG_DEBUG("[%d] reg[0x%x] = %" PRIx64, hartid, regid, value);
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return value;
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}
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bool riscv_is_halted(struct target *target)
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{
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RISCV_INFO(r);
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assert(r->is_halted);
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return r->is_halted(target);
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}
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@@ -1261,16 +1562,19 @@ int riscv_enumerate_triggers(struct target *target)
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if (!riscv_hart_enabled(target, hartid))
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continue;
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riscv_reg_t tselect = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TSELECT);
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for (unsigned t = 0; t < RISCV_MAX_TRIGGERS; ++t) {
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r->trigger_count[hartid] = t;
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riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, t);
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uint64_t tselect = riscv_get_register_on_hart(target, hartid,
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uint64_t tselect_rb = riscv_get_register_on_hart(target, hartid,
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GDB_REGNO_TSELECT);
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// Mask off the top bit, which is used as tdrmode in old
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// implementations.
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tselect &= ~(1ULL << (riscv_xlen(target)-1));
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if (tselect != t)
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tselect_rb &= ~(1ULL << (riscv_xlen(target)-1));
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if (tselect_rb != t)
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break;
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uint64_t tdata1 = riscv_get_register_on_hart(target, hartid,
|
||||
@@ -1290,6 +1594,8 @@ int riscv_enumerate_triggers(struct target *target)
|
||||
}
|
||||
}
|
||||
|
||||
riscv_set_register_on_hart(target, hartid, GDB_REGNO_TSELECT, tselect);
|
||||
|
||||
LOG_DEBUG("[%d] Found %d triggers", hartid, r->trigger_count[hartid]);
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user