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target/aarch64: a64 disassembler

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Add A64 (AArch64) Disassembler using Capstone framework.

Change-Id: Ia92b57001843b11a818af940a468b131e42a03fd
Signed-off-by: Mete Balci <metebalci@gmail.com>
[Antonio Borneo: Rebased on current HEAD]
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5004
Tested-by: jenkins
This commit is contained in:
Mete Balci
2019-03-30 12:27:57 +01:00
committed by Antonio Borneo
parent a31e579e87
commit d7d70c2719
5 changed files with 224 additions and 1 deletions
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doc/openocd.texi
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@@ -9349,6 +9349,12 @@ target code relies on. In a configuration file, the command would typically be c
However, normally it is not necessary to use the command at all.
@end deffn
@deffn Command {aarch64 disassemble} address [count]
@cindex disassemble
Disassembles @var{count} instructions starting at @var{address}.
If @var{count} is not specified, a single instruction is disassembled.
@end deffn
@deffn Command {aarch64 smp} [on|off]
Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger