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Cortex-M3: improved core exception handling

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This updates three aspects of debugger/exception interactions:

 - Save the user's "vector_catch" setting, and restore it after reset.
   Previously, it was obliterated (rather annoyingly) each time.

 - Don't catch BusFault and HardFault exceptions unless the user says
   to do so.  Target firmware may need to handle them.

 - Don't modify SHCSR to prevent escalating BusFault to HardFault.
   Target firmware may expect to handle it as a HardFault.

Those simplifications fix several bugs.  In one annoying case, OpenOCD
would cause the target to lock up on ome faults which triggered after
the debugger disconnected.

NOTE:  a known remaining issue is that OpenOCD can still leave DEMCR
set after an otherwise-clean OpenOCD shutdown.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2010-01-13 03:16:37 -08:00
parent b8e930e3bf
commit d91941d5a0
3 changed files with 33 additions and 23 deletions
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9
src/target/armv7m.h
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@@ -106,9 +106,14 @@ struct armv7m_common
int exception_number;
struct swjdp_common swjdp_info;
uint32_t demcr;
/* Direct processor core register read and writes */
int (*load_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
int (*store_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
int (*load_core_reg_u32)(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t *value);
int (*store_core_reg_u32)(struct target *target,
enum armv7m_regtype type, uint32_t num, uint32_t value);
/* register cache to processor synchronization */
int (*read_core_reg)(struct target *target, unsigned num);
int (*write_core_reg)(struct target *target, unsigned num);