pld: add support for altera/intel devices
Change-Id: I7977d39c9037ae71139f78c8d381f5f925dc3489 Signed-off-by: Daniel Anselmi <danselmi@gmx.ch> Reviewed-on: https://review.openocd.org/c/openocd/+/7355 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Daniel Anselmi
committed by
Antonio Borneo
Antonio Borneo
parent
7c6d446440
commit
db0609aeb4
@@ -0,0 +1,20 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# BeMicro Cyclone III
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adapter driver ftdi
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ftdi channel 0
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ftdi layout_init 0x0008 0x008b
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ftdi vid_pid 0x0403 0xa4a0
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reset_config none
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transport select jtag
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adapter speed 10000
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source [find cpld/altera-cycloneiii.cfg]
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#quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
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#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load 0 cycloneiii_blinker.rbf"
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# "ipdbg -start -tap cycloneiii.tap -hub 0x00e -tool 0 -port 5555"
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@@ -1,8 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Altera MAXV 5M24OZ/5M570Z CPLD
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# see MAX V Device Handbook
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# Table 6-3: 32-Bit MAX V Device IDCODE
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# Version Part Number Manuf. ID LSB
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# 0000 0010 0000 1010 0111 000 0110 1110 1
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jtag newtap 5m570z tap -expected-id 0x020a60dd -irlen 10
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# file altera-5m570z-cpld.cfg replaced by altera-maxv.cfg
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echo "DEPRECATED: use altera-maxv.cfg instead of deprecated altera-5m570z-cpld.cfg"
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#just to be backward compatible:
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#tap will be 5m570z.tap instead of maxv.tap:
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set CHIPNAME 5m570z
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source [find cpld/altera-maxv.cfg]
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@@ -1,24 +1,12 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Altera MAXII EPM240T100C CPLD
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# file altera-epm240.cfg replaced by altera-maxii.cfg
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echo "DEPRECATED: use altera-maxii.cfg instead of deprecated altera-epm240.cfg"
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME epm240
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}
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# see MAX II Device Handbook
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# Table 3-3: 32-Bit MAX II Device IDCODE
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# Version Part Number Manuf. ID LSB
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# 0000 0010 0000 1010 0001 000 0110 1110 1
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x020a10dd \
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-expected-id 0x020a20dd \
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-expected-id 0x020a30dd \
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-expected-id 0x020a40dd \
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-expected-id 0x020a50dd \
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-expected-id 0x020a60dd
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#just to be backward compatible:
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#tap will be epm240.tap instead of maxii.tap:
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set CHIPNAME epm240
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source [find cpld/altera-maxii.cfg]
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# 200ns seems like a good speed
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# c.f. Table 5-34: MAX II JTAG Timing Parameters
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@@ -0,0 +1,30 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# see MAX 10 FPGA Device Architecture
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# Table 3-1: IDCODE Information for MAX 10 Devices
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# Intel MAX 10M02 0x31810dd
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# Intel MAX 10M04 0x318a0dd
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# Intel MAX 10M08 0x31820dd
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# Intel MAX 10M16 0x31830dd
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# Intel MAX 10M25 0x31840dd
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# Intel MAX 10M40 0x318d0dd
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# Intel MAX 10M50 0x31850dd
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# Intel MAX 10M02 0x31010dd
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# Intel MAX 10M04 0x310a0dd
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# Intel MAX 10M08 0x31020dd
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# Intel MAX 10M16 0x31030dd
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# Intel MAX 10M25 0x31040dd
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# Intel MAX 10M40 0x310d0dd
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# Intel MAX 10M50 0x31050dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME max10
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}
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jtag newtap $_CHIPNAME tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
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-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
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-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
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-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
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-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
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@@ -0,0 +1,21 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Altera MAXII CPLD
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME maxii
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}
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# see MAX II Device Handbook
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# Table 3-3: 32-Bit MAX II Device IDCODE
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# Version Part Number Manuf. ID LSB
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# 0000 0010 0000 1010 0001 000 0110 1110 1
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x020a10dd \
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-expected-id 0x020a20dd \
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-expected-id 0x020a30dd \
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-expected-id 0x020a40dd \
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-expected-id 0x020a50dd \
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-expected-id 0x020a60dd
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@@ -0,0 +1,19 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Altera MAXV 5M24OZ/5M570Z CPLD
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# see MAX V Device Handbook
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# Table 6-3: 32-Bit MAX V Device IDCODE
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# 5M40Z 5M80Z 5M160Z 5M240Z: 0x020A50DD
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# 5M570Z: 0x020A60DD
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# 5M1270Z: 0x020A30DD
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# 5M1270Z 5M2210Z: 0x020A40DD
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME maxv
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}
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x020A50DD -expected-id 0x020A60DD \
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-expected-id 0x020A30DD -expected-id 0x020A40DD
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@@ -1,24 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# see MAX 10 FPGA Device Architecture
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# Table 3-1: IDCODE Information for MAX 10 Devices
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# Intel MAX 10M02 0x31810dd
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# Intel MAX 10M04 0x318a0dd
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# Intel MAX 10M08 0x31820dd
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# Intel MAX 10M16 0x31830dd
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# Intel MAX 10M25 0x31840dd
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# Intel MAX 10M40 0x318d0dd
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# Intel MAX 10M50 0x31850dd
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# Intel MAX 10M02 0x31010dd
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# Intel MAX 10M04 0x310a0dd
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# Intel MAX 10M08 0x31020dd
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# Intel MAX 10M16 0x31030dd
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# Intel MAX 10M25 0x31040dd
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# Intel MAX 10M40 0x310d0dd
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# Intel MAX 10M50 0x31050dd
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# file altera-10m50.cfg replaced by altera-max10.cfg
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echo "DEPRECATED: use altera-max10.cfg instead of deprecated altera-10m50.cfg"
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jtag newtap 10m50 tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
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-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
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-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
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-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
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-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
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#just to be backward compatible:
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#tap will be 10m50.tap instead of max10.tap:
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set CHIPNAME 10m50
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source [find cpld/altera-max10.cfg]
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@@ -0,0 +1,31 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Arria II FPGA
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# Arria II Device Handbook
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# Table 11–2. 32-Bit IDCODE for Arria II Devices
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#GX:
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#EP2AGX45: 0x025120dd
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#EP2AGX65: 0x025020dd
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#EP2AGX95: 0x025130dd
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#EP2AGX125: 0x025030dd
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#EP2AGX190: 0x025140dd
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#EP2AGX260: 0x025040dd
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#EP2AGZ225: 0x024810dd
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#EP2AGZ300: 0x0240a0dd
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#EP2AGZ350: 0x024820dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME arriaii
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}
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x025120dd -expected-id 0x025040dd \
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-expected-id 0x025020dd -expected-id 0x024810dd \
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-expected-id 0x025130dd -expected-id 0x0240a0dd \
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-expected-id 0x025030dd -expected-id 0x024820dd \
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-expected-id 0x025140dd
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pld device intel $_CHIPNAME.tap arriaii
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@@ -0,0 +1,34 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone 10 FPGA
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# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
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# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
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# GX085: 0x02e120dd
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# GX105: 0x02e320dd
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# GX150: 0x02e720dd
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# GX220: 0x02ef20dd
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# 10cl006: 0x020f10dd
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# 10cl010: 0x020f10dd
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# 10cl016: 0x020f20dd
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# 10cl025: 0x020f30dd
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# 10cl040: 0x020f40dd
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# 10cl055: 0x020f50dd
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# 10cl080: 0x020f60dd
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# 10cl120: 0x020f70dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cyclone10
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}
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x02e720dd -expected-id 0x02e120dd \
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-expected-id 0x02ef20dd -expected-id 0x02e320dd \
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-expected-id 0x020f10dd -expected-id 0x020f20dd \
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-expected-id 0x020f30dd -expected-id 0x020f40dd \
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-expected-id 0x020f50dd -expected-id 0x020f60dd \
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-expected-id 0x020f70dd
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pld device intel $_CHIPNAME.tap cyclone10
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@@ -0,0 +1,35 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone III FPGA
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# see Cyclone III Device Handbook
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# Table 12-2: Device IDCODE for Cyclone III Device Family
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#EP3C5 0x020f10dd
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#EP3C10 0x020f10dd
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#EP3C16 0x020f20dd
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#EP3C25 0x020f30dd
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#EP3C40 0x020f40dd
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#EP3C55 0x020f50dd
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#EP3C80 0x020f60dd
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#EP3C120 0x020f70dd
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#Cyclone III LS
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#EP3CLS70 0x027010dd
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#EP3CLS100 0x027000dd
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#EP3CLS150 0x027030dd
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#EP3CLS200 0x027020dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cycloneiii
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}
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x020f10dd -expected-id 0x020f20dd \
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-expected-id 0x020f30dd -expected-id 0x020f40dd \
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-expected-id 0x020f50dd -expected-id 0x020f60dd \
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-expected-id 0x020f70dd -expected-id 0x027010dd \
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-expected-id 0x027000dd -expected-id 0x027030dd \
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-expected-id 0x027020dd
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pld device intel $_CHIPNAME.tap cycloneiii
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@@ -0,0 +1,41 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone IV FPGA
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# see Cyclone IV Device Handbook
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# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
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#EP4CE6 0x020f10dd
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#EP4CE10 0x020f10dd
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#EP4CE15 0x020f20dd
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#EP4CE22 0x020f30dd
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#EP4CE30 0x020f40dd
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#EP4CE40 0x020f40dd
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#EP4CE55 0x020f50dd
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#EP4CE75 0x020f60dd
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#EP4CE115 0x020f70dd
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#EP4CGX15 0x028010dd
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#EP4CGX22 0x028120dd
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#EP4CGX30 (3) 0x028020dd
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#EP4CGX30 (4) 0x028230dd
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#EP4CGX50 0x028130dd
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#EP4CGX75 0x028030dd
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#EP4CGX110 0x028140dd
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#EP4CGX150 0x028040dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cycloneiv
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}
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x020f10dd -expected-id 0x020f20dd \
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-expected-id 0x020f30dd -expected-id 0x020f40dd \
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-expected-id 0x020f50dd -expected-id 0x020f60dd \
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-expected-id 0x020f70dd -expected-id 0x028010dd \
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-expected-id 0x028120dd -expected-id 0x028020dd \
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-expected-id 0x028230dd -expected-id 0x028130dd \
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-expected-id 0x028030dd -expected-id 0x028140dd \
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-expected-id 0x028040dd
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pld device intel $_CHIPNAME.tap cycloneiv
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@@ -0,0 +1,47 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Intel Cyclone 5 FPGA
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# see Cyclone V Device Handbook
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# Table 9-1: IDCODE Information for Cyclone V Devices
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#5CEA2 0x02b150dd
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#5CEA4 0x02b050dd
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#5CEA5 0x02b220dd
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#5CEA7 0x02b130dd
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#5CEA9 0x02b140dd
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#5CGXC3 0x02b010dd
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#5CGXC4 0x02b120dd
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#5CGXC5 0x02b020dd
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#5CGXC7 0x02b030dd
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#5CGXC9 0x02b040dd
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#5CGTD5 0x02b020dd
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#5CGTD7 0x02b030dd
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#5CGTD9 0x02b040dd
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#5CSEA2 0x02d110dd
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#5CSEA4 0x02d010dd
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#5CSEA5 0x02d120dd
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#5CSEA6 0x02d020dd
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#5CSXC2 0x02d110dd
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#5CSXC4 0x02d010dd
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#5CSXC5 0x02d120dd
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#5CSXC6 0x02d020dd
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#5CSTD5 0x02d120dd
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#5CSTD6 0x02d020dd
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cyclonev
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}
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jtag newtap $_CHIPNAME tap -irlen 10 \
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-expected-id 0x02b150dd -expected-id 0x02b050dd \
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-expected-id 0x02b220dd -expected-id 0x02b130dd \
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-expected-id 0x02b140dd -expected-id 0x02b010dd \
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-expected-id 0x02b120dd -expected-id 0x02b020dd \
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-expected-id 0x02b030dd -expected-id 0x02b040dd \
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-expected-id 0x02d110dd -expected-id 0x02d010dd \
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-expected-id 0x02d120dd -expected-id 0x02d020dd
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pld device intel $_CHIPNAME.tap cyclonev
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@@ -1,6 +1,9 @@
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# SPDX-License-Identifier: GPL-2.0-or-later
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# Altera Cyclone III EP3C10
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# see Cyclone III Device Handbook, Volume 1;
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# Table 14–5. 32-Bit Cyclone III Device IDCODE
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jtag newtap ep3c10 tap -expected-id 0x020f10dd -irlen 10
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# file altera-ep3c10.cfg replaced by altera-cycloneiii.cfg
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echo "DEPRECATED: use altera-cycloneiii.cfg instead of deprecated altera-ep3c10.cfg"
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#just to be backward compatible:
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#tap will be ep3c10.tap instead of cycloneiii.tap:
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set CHIPNAME ep3c10
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source [find fpga/altera-cycloneiii.cfg]
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