Move TCL script files -- Step 2 of 2:

- Move src/tcl to tcl/. - Update top Makefile.am to use new path name. git-svn-id: svn://svn.berlios.de/openocd/trunk@1919 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-05-27 06:49:24 +00:00
parent 140d6c8e79
commit dbbc9c41f7
134 changed files with 1 additions and 1 deletions
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -0,0 +1,61 @@
+## -*- tcl -*-
+##
+
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # This config file was defaulting to big endian..
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {	
+   set  _CPUTAPID $CPUTAPID    
+} else {	 
+   set  _CPUTAPID 0xffffffff
+}
+
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# This is for the case that TRST/SRST is not wired on your JTAG adaptor.
+# Don't really need them anyways.  
+reset_config none
+
+## JTAG scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+##
+## Target configuration
+##
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# allocate the entire SRAM as working area
+$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
+
+## flash configuration
+# only target number is needed
+flash bank aduc702x 0 0 0 0 0
+
+## If you use the watchdog, the following code makes sure that the board
+## doesn't reboot when halted via JTAG.  Yes, on the older generation
+## AdUC702x, timer3 continues running even when the CPU is halted.
+
+proc watchdog_service {} {
+    global watchdog_hdl
+    mww 0xffff036c 0
+#    puts "watchdog!!"
+    set watchdog_hdl [after 500 watchdog_service]
+}
+
+$_TARGETNAME configure -event reset-halt-post {  watchdog_service }
+$_TARGETNAME configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl }
--- a/tcl/target/at91eb40a.cfg
+++ b/tcl/target/at91eb40a.cfg
@@ -0,0 +1,61 @@
+#Script for AT91EB40a
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+ 
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+#flash driver
+flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	puts "Running reset init script for AT91EB40A"
+	# Reset script for AT91EB40a
+	reg cpsr 0x000000D3
+	mww 0xFFE00020 0x1
+	mww 0xFFE00024 0x00000000  
+	mww 0xFFE00000 0x01002539 
+	mww 0xFFFFF124 0xFFFFFFFF  
+	mww 0xffff0010 0x100
+	mww 0xffff0034 0x100
+}
--- a/tcl/target/at91r40008.cfg
+++ b/tcl/target/at91r40008.cfg
@@ -0,0 +1,50 @@
+
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at9r40008
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+
+
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	wait_halt
+	sleep 10
+	poll
+	# Ethernut 3 remapping is required to access external flash memory.
+	mww 0xffe00000 0x1000213d
+	mww 0xffe00004 0x20003e3d
+	mww 0xffe00020 0x00000001
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
+
+flash bank cfi 0x10000000 0x400000 2 2 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/at91rm9200.cfg
+++ b/tcl/target/at91rm9200.cfg
@@ -0,0 +1,51 @@
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91rm9200
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x05b0203f
+}
+
+# Never allow the following!
+if { $_CPUTAPID == 0x15b0203f } {
+   puts "-------------------------------------------------------"
+   puts "- ERROR:                                              -"
+   puts "- ERROR: TapID 0x15b0203f is wrong for at91rm9200      -"
+   puts "- ERROR: The chip/board has a JTAG select pin/jumper  -"
+   puts "- ERROR:                                              -"
+   puts "- ERROR: In one position (0x05b0203f) it selects the   -"
+   puts "- ERROR: ARM CPU, in the other position (0x1b0203f)   -"
+   puts "- ERROR: it selects boundry-scan not the ARM          -"
+   puts "- ERROR:                                              -"
+   puts "-------------------------------------------------------"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME 
+# AT91RM9200 has a 16K block of sram @ 0x0020.0000
+$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+
+# This chip has a DCC ... use it
+arm7_9 dcc_downloads enable
+
+
+
+
+
--- a/tcl/target/at91sam9260.cfg
+++ b/tcl/target/at91sam9260.cfg
@@ -0,0 +1,42 @@
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+
+
--- a/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
+++ b/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
@@ -0,0 +1,127 @@
+
+
+
+jtag_khz 4
+
+
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst
+
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+$_TARGETNAME invoke-event halted
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+
+scan_chain
+$_TARGETNAME configure -event reset-deassert-post {at91sam_init}
+
+
+# Flash configuration
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
+
+
+proc at91sam_init { } {
+	
+	# at reset chip runs at 32khz
+	jtag_khz 8
+	halt
+	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
+	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+	sleep 20                          # wait 20 ms
+	mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+	sleep 10                          # wait 10 ms
+	mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
+	sleep 20                          # wait 20 ms
+	mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
+	sleep 10                          # wait 10 ms
+	mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
+	sleep 10                          # wait 10 ms
+
+	# Now run at anything fast... ie: 10mhz!
+	jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xffffec00 0x0a0a0a0a         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x0b0b0b0b         # SMC_PULSE0
+	mww 0xffffec08 0x00160016         # SMC_CYCLE0
+	mww 0xffffec0c 0x00161003         # SMC_MODE0
+
+	flash probe 0                     # Identify flash bank 0
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
+	mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
+
+	mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+	#mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
+}
+
+
+
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -0,0 +1,170 @@
+#
+# Utility code for DaVinci-family chips
+#
+
+# davinci_pinmux:  assigns PINMUX$reg <== $value
+proc davinci_pinmux {soc reg value} {
+	mww [expr [dict get $soc sysbase] + 4 * $reg] $value
+}
+
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+	set value ""
+	ocd_mem2array value 32 $reg 1
+	return $value(0)
+}
+
+# mmw: "memory modify word", updates value of $reg
+#	$reg <== ((value & ~$clearbits) | $setbits)
+proc mmw {reg setbits clearbits} {
+	set old [mrw $reg]
+	set new [expr ($old & ~$clearbits) | $setbits]
+	mww $reg $new
+}
+
+#
+# pll_setup: initialize PLL
+#  - pll_addr ... physical addr of controller
+#  - mult ... pll multiplier
+#  - config ... dict mapping { prediv, postdiv, div[1-9] } to dividers
+#
+# For PLLs that don't have a given register (e.g. plldiv8), or where a
+# given divider is non-programmable, caller provides *NO* config mapping.
+#
+# REVISIT there are minor differences between the PLL controllers.
+# Handle those; maybe check the ID register.  This version behaves
+# for at least the dm355.  On dm6446 and dm357 the PLLRST polarity
+# is different.  On dm365 there are more changes.
+#
+proc pll_setup {pll_addr mult config} {
+	set pll_ctrl_addr [expr $pll_addr + 0x100]
+	set pll_ctrl [mrw $pll_ctrl_addr]
+
+	# 1 - clear CLKMODE (bit 8) iff using on-chip oscillator
+	# NOTE:  this assumes we should clear that bit
+	set pll_ctrl [expr $pll_ctrl & ~0x0100]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 2 - clear PLLENSRC (bit 5)
+	set pll_ctrl [expr $pll_ctrl & ~0x0020]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 3 - clear PLLEN (bit 0) ... enter bypass mode
+	set pll_ctrl [expr $pll_ctrl & ~0x0001]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 4 - wait at least 4 refclk cycles
+	sleep 1
+
+	# 5 - set PLLRST (bit 3)
+	set pll_ctrl [expr $pll_ctrl | 0x0008]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 6 - set PLLDIS (bit 4)
+	set pll_ctrl [expr $pll_ctrl | 0x0010]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 7 - clear PLLPWRDN (bit 1)
+	set pll_ctrl [expr $pll_ctrl & ~0x0002]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 8 - clear PLLDIS (bit 4)
+	set pll_ctrl [expr $pll_ctrl & ~0x0010]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 9 - optional:  write prediv, postdiv, and pllm
+	# NOTE:  for dm355 PLL1, postdiv is controlled via MISC register
+	mww [expr $pll_addr + 0x0110] [expr ($mult - 1) & 0xff]
+	if { [dict exists $config prediv] } {
+		set div [dict get $config prediv]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x0114] $div
+	}
+	if { [dict exists $config postdiv] } {
+		set div [dict get $config postdiv]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x0128] $div
+	}
+
+	# 10 - optional:  set plldiv1, plldiv2, ...
+	# NOTE:  this assumes some registers have their just-reset values:
+	#	- PLLSTAT.GOSTAT is clear when we enter
+	#	- ALNCTL has everything set
+	set go 0
+	if { [dict exists $config div1] } {
+		set div [dict get $config div1]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x0118] $div
+		set go 1
+	}
+	if { [dict exists $config div2] } {
+		1et div [dict get $config div2]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x011c] $div
+		set go 1
+	}
+	if { [dict exists $config div3] } {
+		set div [dict get $config div3]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x011c] $div
+		set go 1
+	}
+	if { [dict exists $config div4] } {
+		set div [dict get $config div4]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x0160] $div
+		set go 1
+	}
+	if { [dict exists $config div5] } {
+		set div [dict get $config div5]
+		set div [expr 0x8000 | ($div - 1)]
+		mww [expr $pll_addr + 0x0164] $div
+		set go 1
+	}
+	if {$go != 0} {
+		# write pllcmd.GO; poll pllstat.GO
+		mww [expr $pll_addr + 0x0138] 0x01
+		set pllstat [expr $pll_addr + 0x013c]
+		while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
+	}
+
+	# 11 - wait at least 5 usec for reset to finish
+	# (assume covered by overheads including JTAG messaging)
+
+	# 12 - clear PLLRST (bit 3)
+	set pll_ctrl [expr $pll_ctrl & ~0x0008]
+	mww $pll_ctrl_addr $pll_ctrl
+
+	# 13 - wait at least 8000 refclk cycles for PLL to lock
+	# if we assume 24 MHz (slowest osc), that's 1/3 msec
+	sleep 3
+
+	# 14 - set PLLEN (bit 0) ... leave bypass mode
+	set pll_ctrl [expr $pll_ctrl | 0x0001]
+	mww $pll_ctrl_addr $pll_ctrl
+}
+
+# NOTE:  dm6446 requires EMURSTIE set in MDCTL before certain
+# modules can be enabled.
+
+# prepare a non-DSP module to be enabled; finish with psc_go
+proc psc_enable {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable
+proc psc_go {} {
+	set psc_addr 0x01c41000
+	set ptstat_addr [expr $psc_addr + 0x0128]
+
+	# just in case PTSTAT.go isn't clear
+	while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
+
+	# write PTCMD.go ... ignoring any DSP power domain
+	mww [expr $psc_addr + 0x0120] 1
+
+	# wait for PTSTAT.go to clear (again ignoring DSP power domain)
+	while { [expr [mrw $ptstat_addr] & 0x01] != 0 } { sleep 1 }
+}
--- a/tcl/target/epc9301.cfg
+++ b/tcl/target/epc9301.cfg
@@ -0,0 +1,31 @@
+# Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME ep9301
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
+
+#flash configuration
+#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
+flash bank cfi 0x60000000 0x1000000 2 2 0
--- a/tcl/target/feroceon.cfg
+++ b/tcl/target/feroceon.cfg
@@ -0,0 +1,30 @@
+######################################
+# Target:    Marvell Feroceon CPU core
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME feroceon
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x20a023d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
--- a/tcl/target/imx21.cfg
+++ b/tcl/target/imx21.cfg
@@ -0,0 +1,32 @@
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME imx21
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+
+# Note above there is 1 tap 
+
+# The CPU tap
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0792611f
+}
+jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+arm7_9 dcc_downloads enable
--- a/tcl/target/imx27.cfg
+++ b/tcl/target/imx27.cfg
@@ -0,0 +1,42 @@
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME imx27
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+
+# Note above there are 2 taps 
+
+# The bs tap
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+   set _BSTAPID 0x1b900f0f
+}
+jtag newtap $_CHIPNAME bs  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID
+
+# The CPU tap
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07926121
+}
+jtag newtap $_CHIPNAME cpu  -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Create the GDB Target.
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size  0x8000 -work-area-backup 1
+# Internal to the chip, there is 45K of SRAM
+#
+
+arm7_9 dcc_downloads enable
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -0,0 +1,62 @@
+# imx31 config
+#
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME imx31
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID ] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x2190101d
+}
+
+#========================================
+# The "system jtag controller" 
+# IMX31 reference manual, page 6-28 - figure 6-14
+if { [info exists SJCTAPID ] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
+
+# The "SDMA" - <S>mart <DMA> controller debug tap
+# Based on some IO pins - this can be disabled & removed
+# See diagram: 6-14
+#   SIGNAL NAME:
+#    SJC_MOD - controls multiplexer - disables ARM1136
+#    SDMA_BYPASS - disables SDMA    - 
+#  
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0xf -expected-id 0x0
+
+# Per section 40.17.1, table 40-85 the IR register is 4 bits
+# But this conflicts with Diagram 6-13, "3bits ir and drs"
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+
+proc power_restore {} { puts "Sensed power restore. No action." } 
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
--- a/tcl/target/imx35.cfg
+++ b/tcl/target/imx35.cfg
@@ -0,0 +1,50 @@
+# imx35 config
+#
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME imx35
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x07b3601d
+}
+
+if { [info exists SDMATAPID ] } {
+   set _SDMATAPID $SDMATAPID
+} else {
+   set _SDMATAPID 0x0882601d
+}
+
+#========================================
+# The "system jtag controller" 
+# IMX31 reference manual, page 6-28 - figure 6-14
+if { [info exists SJCTAPID ] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x2b900f0f
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x0 -irmask 0x0 -expected-id $_SJCTAPID
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+# No IDCODE for this TAP
+jtag newtap $_CHIPNAME whatchacallit -irlen 4 -ircapture 0 -irmask 0x0 -expected-id 0x0
+
+jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+proc power_restore {} { puts "Sensed power restore. No action." } 
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
--- a/tcl/target/is5114.cfg
+++ b/tcl/target/is5114.cfg
@@ -0,0 +1,49 @@
+# script for Insilica IS-5114
+# AKA: Atmel AT76C114 - an ARM946 chip
+# ATMEL sold his product line to Insilica...
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME is5114
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a little endian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+jtag_rclk 16
+
+reset_config trst_and_srst
+
+# Do not specify a tap id here...
+#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe
+jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 
+#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe
+# This is the "arm946" chip.
+jtag newtap $_CHIPNAME cpu      -irlen 4 -ircapture 0x0e -irmask 0xf
+#OLD SYNTAX: jtag_device 5 0x1 0x1 0x1e
+jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1
+
+
+#arm946e-s and 
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN  -chain-position $_TARGETNAME  -variant arm966e
+
+$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	jtag_rclk 3000
+}
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
--- a/tcl/target/ixp42x.cfg
+++ b/tcl/target/ixp42x.cfg
@@ -0,0 +1,32 @@
+#xscale ixp42x CPU
+
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME ixp42x
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a bigendian
+   set  _ENDIAN big
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can?t set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
+
--- a/tcl/target/lm3s3748.cfg
+++ b/tcl/target/lm3s3748.cfg
@@ -0,0 +1,49 @@
+# Script for luminary lm3s3748
+#
+# NB! work in progress! Duplicated from lm3s811.cfg, but does
+# it need modification??
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME lm3s3748
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a little endian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x3ba00477
+}
+
+# RCLK 
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#lm3s3748 Evaluation Board has only srst
+reset_config srst_only
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+# the luminary variant causes a software reset rather than asserting SRST
+# this stops the debug registers from being cleared
+# this will be fixed in later revisions of silicon
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+
+# 8k working area at base of ram
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+
+#flash configuration
+flash bank stellaris 0 0 0 0 0
--- a/tcl/target/lm3s6965.cfg
+++ b/tcl/target/lm3s6965.cfg
@@ -0,0 +1,46 @@
+# script for luminary lm3s6965
+
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME lm3s6965
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a little endian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x3ba00477
+}
+
+# jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#LM3S6965 Evaluation Board has only srst
+reset_config srst_only
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
+# the luminary variant causes a software reset rather than asserting SRST
+# this stops the debug registers from being cleared
+# this will be fixed in later revisions of silicon
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+
+# 4k working area at base of ram
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash configuration
+flash bank stellaris 0 0 0 0 0
--- a/tcl/target/lm3s811.cfg
+++ b/tcl/target/lm3s811.cfg
@@ -0,0 +1,45 @@
+# Script for luminary lm3s811
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME lm3s811
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a little endian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x3ba00477
+}
+
+# jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#LM3S811 Evaluation Board has only srst
+reset_config srst_only
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID
+
+# the luminary variant causes a software reset rather than asserting SRST
+# this stops the debug registers from being cleared
+# this will be fixed in later revisions of silicon
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+
+# 8k working area at base of ram
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+
+#flash configuration
+flash bank stellaris 0 0 0 0 0
--- a/tcl/target/lpc2103.cfg
+++ b/tcl/target/lpc2103.cfg
@@ -0,0 +1,39 @@
+# NXP LPC2103 ARM7TDMI-S with 32kB Flash and 8kB SRAM, clocked with 12MHz crystal
+
+if { [info exists CHIPNAME] } {	
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lpc2103
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4f1f0f0f 
+}
+
+# LPC2000 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+# reset delays
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+# 8kB of internal SRAM
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x2000 -work-area-backup 0
+
+# 32kB of internal Flash, core clocked with 12MHz crystal
+# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
+flash bank lpc2000 0x0 0x8000 0 0 0 lpc2000_v2 12000 calc_checksum
--- a/tcl/target/lpc2124.cfg
+++ b/tcl/target/lpc2124.cfg
@@ -0,0 +1,42 @@
+#LPC-2124 CPU
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME lpc2124
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+    set _CPUTAPID 0x4f1f0f0f
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+# reset delays
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+jtag_khz 1000
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14745 calc_checksum
--- a/tcl/target/lpc2129.cfg
+++ b/tcl/target/lpc2129.cfg
@@ -0,0 +1,41 @@
+#LPC-2129 CPU
+
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME lpc2129
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+# reset delays
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
--- a/tcl/target/lpc2148.cfg
+++ b/tcl/target/lpc2148.cfg
@@ -0,0 +1,56 @@
+# Use RCLK. If RCLK is not available fall back to 500kHz. 
+# 
+# Depending on cabling you might be able to eek this up to 2000kHz.
+jtag_rclk 500
+
+if { [info exists CHIPNAME] } {	
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME lpc2148
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x4f1f0f0f
+}
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# NOTE!!! LPCs need reset pulled while RTCK is low. 0 to activate
+# JTAG, power-on reset is not enough, i.e. you need to perform a
+# reset before being able to talk to the LPC2148, attach is not possible.
+
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	# Force target into ARM state.
+	soft_reset_halt
+
+	# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
+	# "User Flash Mode" where interrupt vectors are _not_ remapped,
+	# and reside in flash instead).
+	#
+	# See section 7.1 on page 32 ("Memory Mapping control register") in
+	# "UM10139: Volume 1: LPC214x User Manual", Rev. 02 -- 25 July 2006.
+	# http://www.standardics.nxp.com/support/documents/microcontrollers/pdf/user.manual.lpc2141.lpc2142.lpc2144.lpc2146.lpc2148.pdf
+	mwb 0xE01FC040 0x01
+}
+
+# flash bank lpc2000 <base> <size> 0 0 <target#> <variant> <clock> [calc_checksum]
+flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 calc_checksum
--- a/tcl/target/lpc2294.cfg
+++ b/tcl/target/lpc2294.cfg
@@ -0,0 +1,38 @@
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME lpc2294
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash configuration
+#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
+flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/lpc2378.cfg
+++ b/tcl/target/lpc2378.cfg
@@ -0,0 +1,49 @@
+# NXP LPC2378 ARM7TDMI-S with 512kB Flash and 32kB Local On-Chip SRAM (58kB total), clocked with 4MHz internal RC oscillator
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc2378
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4f1f0f0f
+}
+
+#delays on reset lines
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+# LPC2378 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x8000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	# Force target into ARM state
+	soft_reset_halt
+	#do not remap 0x0000-0x0020 to anything but the flash
+	mwb 0xE01FC040 0x01
+}
+
+# LPC2378 has 512kB of FLASH, but upper 8kB are occupied by bootloader.
+# After reset the chip uses its internal 4MHz RC oscillator
+#flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
+flash bank lpc2000 0x0 0x0007D000 0 0 0 lpc2000_v2 4000 calc_checksum
+
+# 4MHz / 6 = 666kHz, so use 500
+jtag_khz 500
--- a/tcl/target/lpc2478.cfg
+++ b/tcl/target/lpc2478.cfg
@@ -0,0 +1,35 @@
+# Testing feeedback wanted!
+set _CHIPNAME lpc2478
+set _ENDIAN little
+set _CPUTAPID 0x4f1f0f0f
+
+# Use RCLK. If RCLK is not available fall back to 500kHz. 
+# 
+# Depending on cabling you might be able to eek this up to 2000kHz.
+jtag_rclk 500
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+
+$_TARGETNAME configure -event reset-init {
+	# Force target into ARM state
+	soft_reset_halt
+	# FIX!!!! should we remap the range below??? Is this applicable to
+	# Copied from LPC2148.
+	#do not remap 0x0000-0x0020 to anything but the flash
+	mwb 0xE01FC040 0x01
+}
+
+
+flash bank lpc2000 0x0 0x7D000 0 0 0 lpc2000_v2 12000 calc_checksum
--- a/tcl/target/mega128.cfg
+++ b/tcl/target/mega128.cfg
@@ -0,0 +1,42 @@
+# for avr
+
+   set  _CHIPNAME avr
+   set  _ENDIAN little
+
+# jtag speed
+jtag_khz 4500
+
+reset_config  srst_only
+jtag_nsrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x8970203F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+flash bank avr 0 0 0 0 0
+
+#to use it, script will be like:
+#init
+#jtag_khz 4500
+#reset init
+#verify_ircapture disable
+#
+#halt
+#wait halt
+#poll
+#avr mass_erase 0
+#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#reset run
+#shutdown
+#
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/netx500.cfg
+++ b/tcl/target/netx500.cfg
@@ -0,0 +1,34 @@
+#Hilscher netX 500 CPU
+
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME netx500
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+#jtag scan chain
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -0,0 +1,57 @@
+#File omap3530.cfg - as found on the BEAGLEBOARD
+#  Assumption is it is generic for all OMAP3530 
+
+#TI OMAP3 processor - http://www.ti.com 
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME omap3
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a little endianness
+  set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+  set _CPUTAPID 0x0B6D602F
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID -disable
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0xf -expected-id 0x0b7ae02f
+
+target create omap3.cpu cortex_m3 -endian little -chain-position omap3.cpu
+
+jtag configure $_CHIPNAME.cpu -event tap-enable {
+	puts "Enabling Cortex-A8 @ OMAP3"
+	irscan omap3.jrc 7 -endstate IRPAUSE
+	drscan omap3.jrc 8 0x89 -endstate DRPAUSE
+	irscan omap3.jrc 2 -endstate IRPAUSE
+	drscan omap3.jrc 32 0xa3002108  -endstate RUN/IDLE
+	irscan omap3.jrc 0x3F -endstate RUN/IDLE
+	runtest 10
+	puts "Cortex-A8 @ OMAP3 enabled"
+}
+
+proc omap3_dbginit { } {
+     version
+     jtag tapenable omap3.cpu
+     targets
+     # sleep 1000
+     # dap apsel 1
+     # sleep 1000
+     # dap apsel 1
+     # dap info 1
+     omap3.cpu mww 0x54011FB0 0xC5ACCE55 4
+     omap3.cpu mdw 0x54011314
+     omap3.cpu mdw 0x54011314
+     # omap3.cpu mdw 0x54011080
+     omap3.cpu mww 0x5401d030 0x00002000 4
+}
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -0,0 +1,63 @@
+#TI OMAP5912 dual core processor - http://www.ti.com 
+#on a OMAP5912 OSK board http://www.spectrumdigital.com.
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME omap5912
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a bigendian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME unknown1 -irlen 38 -ircapture 0x0 -irmask 0x0 
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME unknown2 irlen 8 -ircapture  0x0 -irmask 0x0 
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+$_TARGETNAME configure -event reset-init {
+	#
+	# halt target
+	#
+	poll
+	sleep 1
+	halt
+	wait_halt
+	#
+	# disable wdt
+	#
+	mww 0xfffec808 0x000000f5
+	mww 0xfffec808 0x000000a0
+
+	mww 0xfffeb048 0x0000aaaa
+	sleep 500
+	mww 0xfffeb048 0x00005555
+	sleep 500
+	#
+	# detect flash
+	#
+	flash probe 0
+}
+
+# omap5912 lcd frame buffer as working area
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank cfi 0x00000000 0x1000000 2 2 0
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -0,0 +1,40 @@
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME pic32mx
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x30938053
+}
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5  -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
+
+flash bank pic32mx 0xbd000000 0 0 0 0
+flash bank pic32mx 0xbfc00000 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -0,0 +1,104 @@
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME pxa255
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255
+$_TARGETNAME configure -event reset-init {
+	xscale cp15   15      0x00002001  #Enable CP0 and CP13 access
+	#
+	# setup GPIO
+	#
+	mww    0x40E00018  0x00008000  #CPSR0
+	sleep   20
+	mww    0x40E0001C  0x00000002  #GPSR1
+	sleep   20
+	mww    0x40E00020  0x00000008  #GPSR2
+	sleep   20
+	mww    0x40E0000C  0x00008000  #GPDR0
+	sleep   20
+	mww    0x40E00054  0x80000000  #GAFR0_L
+	sleep   20
+	mww    0x40E00058  0x00188010  #GAFR0_H
+	sleep   20
+	mww    0x40E0005C  0x60908018  #GAFR1_L
+	sleep   20
+	mww    0x40E0000C  0x0280E000  #GPDR0
+	sleep   20
+	mww    0x40E00010  0x821C88B2  #GPDR1
+	sleep   20
+	mww    0x40E00014  0x000F03DB  #GPDR2
+	sleep   20
+	mww    0x40E00000  0x000F03DB  #GPLR0
+	sleep   20
+
+
+	mww    0x40F00004  0x00000020  #PSSR
+	sleep   20
+
+	#
+	# setup memory controller
+	#
+	mww    0x48000008  0x01111998  #MSC0
+	sleep   20
+	mww    0x48000010  0x00047ff0  #MSC2
+	sleep   20
+	mww    0x48000014  0x00000000  #MECR
+	sleep   20
+	mww    0x48000028  0x00010504  #MCMEM0
+	sleep   20
+	mww    0x4800002C  0x00010504  #MCMEM1
+	sleep   20
+	mww    0x48000030  0x00010504  #MCATT0
+	sleep   20
+	mww    0x48000034  0x00010504  #MCATT1
+	sleep   20
+	mww    0x48000038  0x00004715  #MCIO0
+	sleep   20
+	mww    0x4800003C  0x00004715  #MCIO1
+	sleep   20
+	#
+	mww    0x48000004  0x03CA4018  #MDREF
+	sleep   20
+	mww    0x48000004  0x004B4018  #MDREF
+	sleep   20
+	mww    0x48000004  0x000B4018  #MDREF
+	sleep   20
+	mww    0x48000004  0x000BC018  #MDREF
+	sleep   20
+	mww    0x48000000  0x00001AC8  #MDCNFG
+	sleep   20
+
+	sleep   20
+
+	mww    0x48000000  0x00001AC9  #MDCNFG
+	sleep   20
+	mww    0x48000040  0x00000000  #MDMRS
+	sleep   20
+}
+
+reset_config trst_and_srst
+
+
+
+#xscale debug_handler 0  0xFFFF0800      # debug handler base address
+
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -0,0 +1,39 @@
+#Marvell/Intel PXA270 Script
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME pxa270
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+#IDs for pxa270. Choose one. Are there others?#
+#set CPUTAPID 0x79265013
+#set CPUTAPID 0x49265013
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+
+# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_nsrst_delay 260
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 0
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0
--- a/tcl/target/readme.txt
+++ b/tcl/target/readme.txt
@@ -0,0 +1,41 @@
+Prerequisites:
+The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands 
+do the same thing across all the targets.
+
+Rules to follow when writing scripts:
+
+1. The configuration script should be defined such as , for example, the following sequences are working:
+	reset
+	flash info <bank>
+and
+	reset 
+	flash erase_address <start> <len>
+and
+	reset init
+	load
+	
+In most cases this can be accomplished by specifying the default startup mode as reset_init (target command 
+in the configuration file).
+ 
+2. If the target is correctly configured, flash must be writable without any other helper commands. It is 
+assumed that all write-protect mechanisms should be disabled.
+
+3. The configuration scripts should be defined such as the binary that was written to flash verifies
+(turn off remapping, checksums, etc...) 
+
+flash write_image [file] <parameters>
+verify_image [file] <parameters>
+
+4. jtag_khz sets the maximum speed (or alternatively RCLK). If invoked
+multiple times only the last setting is used.
+
+interface/xxx.cfg files are always executed *before* target/xxx.cfg
+files, so any jtag_khz in interface/xxx.cfg will be overridden by
+target/xxx.cfg. jtag_khz in interface/xxx.cfg would then, effectively,
+set the default JTAG speed.
+
+Note that a target/xxx.cfg file can invoke another target/yyy.cfg file,
+so one can create target subtype configurations where e.g. only
+amount of DRAM, oscillator speeds differ and having a single
+config file for the default/common settings.
+
--- a/tcl/target/sam7se512.cfg
+++ b/tcl/target/sam7se512.cfg
@@ -0,0 +1,39 @@
+
+# ATMEL sam7se512 
+# Example: the "Elektor Internet Radio" - EIR
+# http://www.ethernut.de/en/hardware/eir/index.html
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME sam7se512
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The target
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+
--- a/tcl/target/sam7x256.cfg
+++ b/tcl/target/sam7x256.cfg
@@ -0,0 +1,52 @@
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME sam7x256
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-init { 
+	# disable watchdog
+	mww 0xfffffd44 0x00008000	
+	# enable user reset
+	mww 0xfffffd08 0xa5000001	
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601	
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e 	
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007	
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=60)
+	mww 0xffffff60 0x003c0100	
+	sleep 100
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/samsung_s3c2410.cfg
+++ b/tcl/target/samsung_s3c2410.cfg
@@ -0,0 +1,35 @@
+# Found on the 'TinCanTools' Hammer board.
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME s3c2410
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # This config file was defaulting to big endian..
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {	
+   set  _CPUTAPID $CPUTAPID    
+} else {	 
+   set  _CPUTAPID 0xffffffff
+}
+
+#use combined on interfaces or targets that cannot set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
--- a/tcl/target/samsung_s3c2440.cfg
+++ b/tcl/target/samsung_s3c2440.cfg
@@ -0,0 +1,35 @@
+# Target configuration for the Samsung 2440 system on chip
+# Tested on a S3C2440 Evaluation board by keesj
+# Processor       : ARM920Tid(wb) rev 0 (v4l)
+# Info:   JTAG tap: s3c2440.cpu tap/device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a bigendian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0032409d
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
+
+#reset configuration
+reset_config trst_and_srst
+
--- a/tcl/target/samsung_s3c4510.cfg
+++ b/tcl/target/samsung_s3c4510.cfg
@@ -0,0 +1,25 @@
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME s3c4510
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+
+# This appears to be a "Version 1" arm7tdmi.
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME  
+
--- a/tcl/target/samsung_s3c6410.cfg
+++ b/tcl/target/samsung_s3c6410.cfg
@@ -0,0 +1,49 @@
+# -*- tcl -*-
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor       : ARM1176
+# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places]
+# [and I do not believe it to be accurate, hence the 0xffffffff below]
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME s3c6410
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a bigendian
+   set  _ENDIAN little
+}
+
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # force an error till we get a good number
+   set _BSTAPID 0x2b900f0f
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x07b76f0f
+}
+
+#jtag scan chain
+
+# I think the "unknown" is the boundry scan tap
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0xe  -expected-id $_BSTAPID
+jtag newtap $_CHIPNAME cpu     -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN  -chain-position $_TARGETNAME -variant arm1176
+
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+#reset configuration
+reset_config trst_and_srst
--- a/tcl/target/sharp_lh79532.cfg
+++ b/tcl/target/sharp_lh79532.cfg
@@ -0,0 +1,26 @@
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME lh79532
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # sharp changed the number!
+   set _CPUTAPID 0x00002061
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME  
+
+
--- a/tcl/target/smdk6410.cfg
+++ b/tcl/target/smdk6410.cfg
@@ -0,0 +1,8 @@
+# Target configuration for the Samsung s3c6410 system on chip
+# Tested on a SMDK6410
+# Processor       : ARM1176
+# Info:   JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+
+source [find target/samsung_s3c6410.cfg]
+
+flash bank cfi 0x00000000 0x00100000 2 2 0 jedec_probe
--- a/tcl/target/smp8634.cfg
+++ b/tcl/target/smp8634.cfg
@@ -0,0 +1,32 @@
+# script for Sigma Designs SMP8634 (eventually even SMP8635)
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME smp8634
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   # force an error till we get a good number
+   set _CPUTAPID 0x08630001
+}
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst separate
+
+# jtag scan chain
+# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag newtap $_CHIPNAME cpu -irlen 5  -ircapture 0x1 -irmask 0x1
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME mips_m4k -endian $_ENDIAN -variant
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32.cfg
@@ -0,0 +1,58 @@
+# script for stm32
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME stm32
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+# jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.3
+   set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+  # See STM Document RM0008
+  # Section 26.6.2
+  # Low density devices, Rev A
+  set _BSTAPID1 0x06412041
+  # Medium density devices, Rev A
+  set _BSTAPID2 0x06410041
+  # Medium density devices, Rev B and Rev Z
+  set _BSTAPID3 0x16410041
+  # High density devices, Rev A
+  set _BSTAPID4 0x06414041
+}   
+jtag newtap $_CHIPNAME bs  -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+flash bank stm32x 0 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -0,0 +1,45 @@
+#start slow, speed up after reset
+jtag_khz 10
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME str710
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {	
+   set  _CPUTAPID $CPUTAPID    
+} else {	 
+   set  _CPUTAPID 0x3f0f0f0f
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+	flash protect 1 0 1 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank str7x <base> <size> 0 0 <target#> <variant>
+flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
+flash bank str7x 0x400C0000 0x00004000 0 0 0 STR71x
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -0,0 +1,46 @@
+#STR730 CPU
+
+jtag_khz 3000
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME str730
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {	
+   set  _CPUTAPID $CPUTAPID    
+} else {	 
+   set  _CPUTAPID 0x3f0f0f0f
+}
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+#reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+#jtag nTRST and nSRST delay
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+$_TARGETNAME configure -event reset-start { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x
+
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -0,0 +1,51 @@
+#STR750 CPU
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME str750
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {	
+   set  _CPUTAPID $CPUTAPID    
+} else {	 
+   set  _CPUTAPID 0x4f1f0041
+}
+
+# jtag speed
+jtag_khz 10
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+#reset_config trst_and_srst srst_pulls_trst
+reset_config trst_and_srst srst_pulls_trst
+
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+#jtag nTRST and nSRST delay
+jtag_nsrst_delay 500
+jtag_ntrst_delay 500
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+
+$_TARGETNAME configure -event reset-start  { jtag_khz 10 }
+$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event gdb-flash-erase-start {
+	flash protect 0 0 7 off
+	flash protect 1 0 1 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x
+flash bank str7x 0x200C0000 0x00004000 0 0 0 STR75x
+
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -0,0 +1,70 @@
+# script for str9
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+# jtag speed. We need to stick to 16kHz until we've finished reset.
+jtag_rclk 16
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+if { [info exists FLASHTAPID ] } {
+   set _FLASHTAPID $FLASHTAPID
+} else {
+   set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu   -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+
+if { [info exists BSTAPID ] } {
+   set _BSTAPID $BSTAPID
+} else {
+   set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs    -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+
+$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
+
+$_TARGETNAME configure -event reset-init {
+	# We can increase speed now that we know the target is halted.
+	#jtag_rclk 3000
+	
+	# -- Enable 96K RAM
+	# PFQBC enabled / DTCM & AHB wait-states disabled
+	mww 0x5C002034 0x0191 
+
+	str9x flash_config 0 4 2 0 0x80000
+	flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank str9x <base> <size> 0 0 <target#> <variant>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
--- a/tcl/target/test_reset_syntax_error.cfg
+++ b/tcl/target/test_reset_syntax_error.cfg
@@ -0,0 +1,17 @@
+# Test script to check that syntax error in reset
+# script is reported properly.
+
+# at91eb40a target
+
+#jtag scan chain
+set _CHIPNAME syntaxtest
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf 
+
+#target configuration
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+$_TARGETNAME configure -event reset-init { 
+
+	syntax error
+}
--- a/tcl/target/test_syntax_error.cfg
+++ b/tcl/target/test_syntax_error.cfg
@@ -0,0 +1,4 @@
+# This script tests a syntax error in the startup 
+# config script
+
+syntax error here
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -0,0 +1,92 @@
+#
+# Texas Instruments DaVinci family:  TMS320DM355
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME dm355
+}
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+#
+# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
+# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
+#
+# Also note:  when running without RTCK before the PLLs are set up, you
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).
+#
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID ] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID ] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID ] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b73b02f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+
+################
+
+# various symbol definitions, to avoid hard-wiring addresses
+# and enable some sharing of DaVinci-family utility code
+global dm355
+set dm355 [ dict create ]
+
+# Physical addresses for controllers and memory
+# (Some of these are valid for many DaVinci family chips)
+dict set dm355 sram0		0x00010000
+dict set dm355 sram1		0x00014000
+dict set dm355 sysbase		0x01c40000
+dict set dm355 pllc1		0x01c40800
+dict set dm355 pllc2		0x01c40c00
+dict set dm355 psc		0x01c41000
+dict set dm355 gpio		0x01c67000
+dict set dm355 a_emif		0x01e10000
+dict set dm355 a_emif_cs0	0x02000000
+dict set dm355 a_emif_cs1	0x04000000
+dict set dm355 ddr_emif		0x20000000
+dict set dm355 ddr		0x80000000
+
+source [find target/davinci.cfg]
+
+################
+# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 16K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
+# and that the work area is used only with a kernel mmu context ...
+$_TARGETNAME configure \
+	-work-area-virt [expr 0xfffe0000 + 0x4000] \
+	-work-area-phys [dict get $dm355 sram1] \
+	-work-area-size 0x4000 \
+	-work-area-backup 0
+
+arm7_9 dbgrq enable
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -0,0 +1,66 @@
+#
+# Texas Instruments DaVinci family:  TMS320DM6446
+#
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME dm6446
+}
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+#
+# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
+# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
+#
+# Also note:  when running without RTCK before the PLLs are set up, you
+# may need to slow the JTAG clock down quite a lot (under 2 MHz).
+#
+
+# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
+if { [info exists ETB_TAPID ] } {
+   set _ETB_TAPID $ETB_TAPID
+} else {
+   set _ETB_TAPID 0x2b900f0f
+}
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+
+# Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
+if { [info exists CPU_TAPID ] } {
+   set _CPU_TAPID $CPU_TAPID
+} else {
+   set _CPU_TAPID 0x07926001
+}
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
+
+# Subsidiary TAP: C64x+ DSP ... NOT CURRENTLY INCLUDED, must add via ICEpick.
+# Documentation for DSP JTAG interfaces evidently needs NDAs.
+
+# Primary TAP: ICEpick (JTAG route controller) and boundary scan
+if { [info exists JRC_TAPID ] } {
+   set _JRC_TAPID $JRC_TAPID
+} else {
+   set _JRC_TAPID 0x0b70002f
+}
+jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+
+# GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
+# and the ETB memory (4K) are other options, while trace is unused.
+set _TARGETNAME $_CHIPNAME.arm
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x0000a000 -work-area-size 0x2000 -work-area-backup 0
+
+arm7_9 dbgrq enable
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+# trace setup
+# FIXME we ought to be able to say "... config $_TARGETNAME ..."
+# (not "config 0") facilitating additional targets (e.g. other chips)
+etm config 0 16 normal full etb
+etb config 0 $_CHIPNAME.etb
+
--- a/tcl/target/xba_revA3.cfg
+++ b/tcl/target/xba_revA3.cfg
@@ -0,0 +1,86 @@
+#Written by: Michael Schwingen <rincewind@discworld.dascon.de>
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME xba_reva3
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # default to big endian
+   set  _ENDIAN big
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0xffffffff
+}
+
+reset_config trst_and_srst separate
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
+$_TARGETNAME configure -event reset-init {
+	#############################################################################
+	# setup expansion bus CS, disable external wdt
+	#############################################################################
+	mww 0xc4000000  0xbd113842  #CS0  : Flash, write enabled @0x50000000
+	mww 0xc4000004  0x94d10013  #CS1
+	mww 0xc4000008  0x95960003  #CS2
+	mww 0xc400000c  0x00000000  #CS3
+	mww 0xc4000010  0x80900003  #CS4
+	mww 0xc4000014  0x9d520003  #CS5
+	mww 0xc4000018  0x81860001  #CS6
+	mww 0xc400001c  0x80900003  #CS7
+
+	#############################################################################
+	# init SDRAM controller: 16MB, one bank, CL3
+	#############################################################################
+	mww 0xCC000000  0x2A # SDRAM_CFG: 64MBit, CL3
+	mww 0xCC000004     0 # disable refresh
+	mww 0xCC000008     3 # NOP
+	sleep 100
+	mww 0xCC000004  2100 # set refresh counter
+	mww 0xCC000008     2 # Precharge All Banks
+	sleep 100
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     4 # Auto Refresh
+	mww 0xCC000008     1 # Mode Select CL3
+
+	#mww 0xc4000020  0xffffee # CFG0: remove expansion bus boot flash
+	#mirror at 0x00000000
+
+	#big endian
+	reg XSCALE_CTRL 0xF8
+
+	#
+	# detect flash
+	#
+	flash probe 0
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0
+
+
+flash bank cfi 0x50000000 0x400000 2 2 0
+
+init 
+reset init
+# set big endian mode
+reg XSCALE_CTRL 0xF8