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flash/stm32l4x: introduce table with register offsets

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This change is a preparation for STM32L5 support on top of L4 driver
STM32L5 flash is quite similar to L4 flash, mainly register names
and offsets and some bits are changed.

flash_regs table is introduced within stm32l4_flash_bank struct in order
to get correct register offsets, by using the driver internal function
'stm32l4_get_flash_reg_by_index'.

To use efficiently register indexes, stm32l4 _[get|read|write]_flash_reg
functions are surcharged to accept register indexes.

IMPORTANT: stm32l4_write_option is not surcharged, and they always accept
the option register offset.

tested on NUCLEO-G474RE and STM32L4R9I-DISCO

Change-Id: I739d3e97d63b831af6aa569c5629db0000209551
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-on: http://openocd.zylin.com/5509
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tarek BOCHKATI
2020-11-03 01:58:59 +01:00
committed by Tomas Vanek
parent 44cf202ef5
commit dc43ecce5a
2 changed files with 104 additions and 49 deletions
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12
src/flash/nor/stm32l4x.h
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@@ -19,18 +19,6 @@
#ifndef OPENOCD_FLASH_NOR_STM32L4X
#define OPENOCD_FLASH_NOR_STM32L4X
/* Flash registers offsets */
#define STM32_FLASH_ACR 0x00
#define STM32_FLASH_KEYR 0x08
#define STM32_FLASH_OPTKEYR 0x0c
#define STM32_FLASH_SR 0x10
#define STM32_FLASH_CR 0x14
#define STM32_FLASH_OPTR 0x20
#define STM32_FLASH_WRP1AR 0x2c
#define STM32_FLASH_WRP1BR 0x30
#define STM32_FLASH_WRP2AR 0x4c
#define STM32_FLASH_WRP2BR 0x50
/* FLASH_CR register bits */
#define FLASH_PG (1 << 0)
#define FLASH_PER (1 << 1)