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Remove whitespace that occurs before ')'.

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- Replace '[ \t]*[)]' with ')'.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2377 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch
2009-06-23 22:47:42 +00:00
parent f90d8fa45f
commit dc575dc5bf
72 changed files with 1016 additions and 1016 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/target/arm11.c
View File

@@ -709,7 +709,7 @@ int arm11_arch_state(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
R(CPSR),
R(PC));
@@ -732,7 +732,7 @@ int arm11_halt(struct target_s *target)
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (target->state == TARGET_UNKNOWN)
{
@@ -789,7 +789,7 @@ int arm11_resume(struct target_s *target, int current, uint32_t address, int han
arm11_common_t * arm11 = target->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (target->state != TARGET_HALTED)
@@ -889,7 +889,7 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
FNC_INFO;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (target->state != TARGET_HALTED)
{
@@ -1035,7 +1035,7 @@ int arm11_deassert_reset(struct target_s *target)
#if 0
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
/* deassert reset lines */
@@ -1960,7 +1960,7 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
RC_FINAL_BOOL("error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
) /* memwrite */
) /* memwrite */
RC_FINAL_BOOL("no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
@@ -1976,7 +1976,7 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
RC_FINAL("mcr", "Write Coprocessor register",
arm11_handle_mcr)
) /* arm11 */
) /* arm11 */
return ERROR_OK;
}

2
src/target/arm720t.c
View File

@@ -319,7 +319,7 @@ int arm720t_arch_state(struct target_s *target)
"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, Cache: %s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),

4
src/target/arm7_9_common.c
View File

@@ -526,7 +526,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], watchpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], watchpoint->mask);
if (watchpoint->mask != 0xffffffffu )
if (watchpoint->mask != 0xffffffffu)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_VALUE], watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));
@@ -543,7 +543,7 @@ int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_VALUE], watchpoint->address);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_ADDR_MASK], mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_MASK], watchpoint->mask);
if (watchpoint->mask != 0xffffffffu )
if (watchpoint->mask != 0xffffffffu)
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_DATA_VALUE], watchpoint->value);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_MASK], 0xff & ~EICE_W_CTRL_nOPC & ~rw_mask);
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], EICE_W_CTRL_ENABLE | EICE_W_CTRL_nOPC | (watchpoint->rw & 1));

2
src/target/arm7tdmi.c
View File

@@ -822,7 +822,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
return ERROR_OK;
}
int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp )
int arm7tdmi_target_create(struct target_s *target, Jim_Interp *interp)
{
arm7tdmi_common_t *arm7tdmi;

2
src/target/arm966e.c
View File

@@ -110,7 +110,7 @@ int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap
return ERROR_OK;
}
int arm966e_target_create(struct target_s *target, Jim_Interp *interp )
int arm966e_target_create(struct target_s *target, Jim_Interp *interp)
{
arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));

2
src/target/arm9tdmi.c
View File

@@ -39,7 +39,7 @@
int handle_arm9tdmi_catch_vectors_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
/* forward declarations */
int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp );
int arm9tdmi_target_create(struct target_s *target, Jim_Interp *interp);
int arm9tdmi_quit(void);

48
src/target/arm_adi_v5.c
View File

@@ -81,7 +81,7 @@ int adi_jtag_dp_scan(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr, uin
arm_jtag_set_instr(jtag_info, instr, NULL);
/* Add specified number of tck clocks before accessing memory bus */
if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0))
if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
fields[0].tap = jtag_info->tap;
@@ -112,7 +112,7 @@ int adi_jtag_dp_scan_u32(swjdp_common_t *swjdp, uint8_t instr, uint8_t reg_addr,
arm_jtag_set_instr(jtag_info, instr, NULL);
/* Add specified number of tck clocks before accessing memory bus */
if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0) )&& (swjdp->memaccess_tck != 0))
if ((instr == DAP_IR_APACC) && ((reg_addr == AP_REG_DRW)||((reg_addr&0xF0) == AP_REG_BD0))&& (swjdp->memaccess_tck != 0))
jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
fields[0].tap = jtag_info->tap;
@@ -374,13 +374,13 @@ int dap_setup_accessport(swjdp_common_t *swjdp, uint32_t csw, uint32_t tar)
if (csw != swjdp->ap_csw_value)
{
/* LOG_DEBUG("swjdp : Set CSW %x",csw); */
dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
swjdp->ap_csw_value = csw;
}
if (tar != swjdp->ap_tar_value)
{
/* LOG_DEBUG("swjdp : Set TAR %x",tar); */
dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
swjdp->ap_tar_value = tar;
}
if (csw & CSW_ADDRINC_MASK)
@@ -404,7 +404,7 @@ int mem_ap_read_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t *value)
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
return ERROR_OK;
}
@@ -428,7 +428,7 @@ int mem_ap_write_u32(swjdp_common_t *swjdp, uint32_t address, uint32_t value)
swjdp->trans_mode = TRANS_MODE_COMPOSITE;
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value);
return ERROR_OK;
}
@@ -467,7 +467,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint
uint32_t outvalue;
memcpy(&outvalue, pBuffer, sizeof(uint32_t));
for (i = 0; i < 4; i++ )
for (i = 0; i < 4; i++)
{
*((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
outvalue >>= 8;
@@ -492,7 +492,7 @@ int mem_ap_write_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint
for (writecount = 0; writecount < blocksize; writecount++)
{
dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
}
if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
@@ -546,7 +546,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun
{
nbytes = MIN((writecount << 1), 4);
if (nbytes < 4 )
if (nbytes < 4)
{
if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
{
@@ -561,7 +561,7 @@ int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int coun
uint32_t outvalue;
memcpy(&outvalue, buffer, sizeof(uint32_t));
for (i = 0; i < nbytes; i++ )
for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8;
@@ -602,7 +602,7 @@ int mem_ap_write_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint
uint16_t svalue;
memcpy(&svalue, buffer, sizeof(uint16_t));
uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
retval = swjdp_transaction_endcheck(swjdp);
count -= 2;
address += 2;
@@ -638,7 +638,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count
{
nbytes = MIN(writecount, 4);
if (nbytes < 4 )
if (nbytes < 4)
{
if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
{
@@ -653,7 +653,7 @@ int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count
uint32_t outvalue;
memcpy(&outvalue, buffer, sizeof(uint32_t));
for (i = 0; i < nbytes; i++ )
for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer + (address & 0x3)) = outvalue;
outvalue >>= 8;
@@ -692,7 +692,7 @@ int mem_ap_write_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
retval = swjdp_transaction_endcheck(swjdp);
count--;
address++;
@@ -770,7 +770,7 @@ int mem_ap_read_buf_u32(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3
uint32_t data;
memcpy(&data, pBuffer, sizeof(uint32_t));
for (i = 0; i < 4; i++ )
for (i = 0; i < 4; i++)
{
*((uint8_t*)pBuffer) = (data >> 8 * (adr & 0x3));
pBuffer++;
@@ -810,7 +810,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
@@ -819,7 +819,7 @@ int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count
nbytes = MIN((readcount << 1), 4);
for (i = 0; i < nbytes; i++ )
for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
@@ -847,11 +847,11 @@ int mem_ap_read_buf_u16(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint3
while (count > 0)
{
dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
retval = swjdp_transaction_endcheck(swjdp);
if (address & 0x1)
{
for (i = 0; i < 2; i++ )
for (i = 0; i < 2; i++)
{
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
@@ -902,7 +902,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count,
do
{
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
{
LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
@@ -911,7 +911,7 @@ int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count,
nbytes = MIN(readcount, 4);
for (i = 0; i < nbytes; i++ )
for (i = 0; i < nbytes; i++)
{
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
buffer++;
@@ -939,7 +939,7 @@ int mem_ap_read_buf_u8(swjdp_common_t *swjdp, uint8_t *buffer, int count, uint32
while (count > 0)
{
dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
retval = swjdp_transaction_endcheck(swjdp);
*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
count--;
@@ -1065,7 +1065,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
}
else
{
command_print(cmd_ctx, "\tROM table in legacy format" );
command_print(cmd_ctx, "\tROM table in legacy format");
}
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
@@ -1081,7 +1081,7 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
}
else
{
command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus");
}
/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */

6
src/target/arm_disassembler.c
View File

@@ -762,7 +762,7 @@ int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instr
(opcode & 0x40000) ? "s" : "",
(opcode & 0x80000) ? "f" : "",
ror(immediate, (rotate * 2))
);
);
}
else /* register variant */
{
@@ -774,7 +774,7 @@ int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instr
(opcode & 0x40000) ? "s" : "",
(opcode & 0x80000) ? "f" : "",
Rm
);
);
}
}
@@ -1200,7 +1200,7 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *in
if ((opcode & 0x0e000000) == 0x0a000000)
return evaluate_blx_imm(opcode, address, instruction);
/* Extended coprocessor opcode space (ARMv5 and higher )*/
/* Extended coprocessor opcode space (ARMv5 and higher)*/
/* Coprocessor load/store and double register transfers */
if ((opcode & 0x0e000000) == 0x0c000000)
return evaluate_ldc_stc_mcrr_mrrc(opcode, address, instruction);

2
src/target/armv4_5.c
View File

@@ -299,7 +299,7 @@ int armv4_5_arch_state(struct target_s *target)
LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));

4
src/target/armv7m.h
View File

@@ -144,7 +144,7 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
* Rd: source register
* SYSm: destination special register
*/
#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8 )) | ((0x8800 | SYSm) << 16))
#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
@@ -159,7 +159,7 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
/* Breakpoint (Thumb mode) v5 onwards
* Im: immediate value used by debugger
*/
#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im) | ((0xBE00 | Im) << 16))
/* Store register (Thumb mode)
* Rd: source register

24
src/target/cortex_m3.c
View File

@@ -109,11 +109,11 @@ int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, uint32_t *value, i
/* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum);
/* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
retval = swjdp_transaction_endcheck(swjdp);
@@ -134,11 +134,11 @@ int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, uint32_t value, i
/* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
/* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR); */
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
retval = swjdp_transaction_endcheck(swjdp);
@@ -204,7 +204,7 @@ int cortex_m3_single_step_core(target_t *target)
return ERROR_OK;
}
int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */ )
int cortex_m3_exec_opcode(target_t *target,uint32_t opcode, int len /* MODE, r0_invalue, &r0_outvalue */)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
@@ -444,7 +444,7 @@ int cortex_m3_debug_entry(target_t *target)
LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
armv7m_mode_strings[armv7m->core_mode],
*(uint32_t*)(armv7m->core_cache->reg_list[15].value),
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (armv7m->post_debug_entry)
armv7m->post_debug_entry(target);
@@ -520,7 +520,7 @@ int cortex_m3_poll(target_t *target)
#if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
#endif
return ERROR_OK;
@@ -529,7 +529,7 @@ int cortex_m3_poll(target_t *target)
int cortex_m3_halt(target_t *target)
{
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (target->state == TARGET_HALTED)
{
@@ -751,7 +751,7 @@ int cortex_m3_assert_reset(target_t *target)
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name );
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -765,7 +765,7 @@ int cortex_m3_assert_reset(target_t *target)
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
if (!target->reset_halt)
{
@@ -862,7 +862,7 @@ int cortex_m3_assert_reset(target_t *target)
int cortex_m3_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
/* deassert reset lines */
jtag_add_reset(0, 0);

4
src/target/etb.c
View File

@@ -387,10 +387,10 @@ static int handle_etb_config_command(struct command_context_s *cmd_ctx, char *cm
return ERROR_FAIL;
}
tap = jtag_tap_by_string(args[1] );
tap = jtag_tap_by_string(args[1]);
if (tap == NULL)
{
command_print(cmd_ctx, "Tap: %s does not exist", args[1] );
command_print(cmd_ctx, "Tap: %s does not exist", args[1]);
return ERROR_FAIL;
}

6
src/target/image.c
View File

@@ -533,7 +533,7 @@ static int image_mot_buffer_complete(image_t *image)
}
else if (record_type >= 1 && record_type <= 3)
{
switch (record_type )
switch (record_type)
{
case 1:
/* S1 - 16 bit address data record */
@@ -636,7 +636,7 @@ static int image_mot_buffer_complete(image_t *image)
cal_checksum += (uint8_t)checksum;
bytes_read += 2;
if (cal_checksum != 0xFF )
if (cal_checksum != 0xFF)
{
/* checksum failed */
LOG_ERROR("incorrect record checksum found in S19 file");
@@ -852,7 +852,7 @@ int image_read_section(image_t *image, int section, uint32_t offset, uint32_t si
memcpy(buffer + *size_read,
image_memory->cache + (address - image_memory->cache_address),
(size_in_cache > size) ? size : size_in_cache
);
);
*size_read += (size_in_cache > size) ? size : size_in_cache;
address += (size_in_cache > size) ? size : size_in_cache;

2
src/target/mips32.c
View File

@@ -265,7 +265,7 @@ int mips32_arch_state(struct target_s *target)
}
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
return ERROR_OK;

2
src/target/mips32_pracc.c
View File

@@ -187,7 +187,7 @@ static int mips32_pracc_exec_write(mips32_pracc_context *ctx, uint32_t address)
offset = (address - MIPS32_PRACC_PARAM_IN) / 4;
ctx->local_iparam[offset] = data;
}
else if ((address >= MIPS32_PRACC_PARAM_OUT )
else if ((address >= MIPS32_PRACC_PARAM_OUT)
&& (address <= MIPS32_PRACC_PARAM_OUT + ctx->num_oparam * 4))
{
offset = (address - MIPS32_PRACC_PARAM_OUT) / 4;

2
src/target/mips32_pracc.h
View File

@@ -35,7 +35,7 @@
#define UPPER16(uint32_t) (uint32_t >> 16)
#define LOWER16(uint32_t) (uint32_t & 0xFFFF)
#define NEG16(v) (((~(v)) + 1) & 0xFFFF)
/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF )*/
/*#define NEG18(v) (((~(v)) + 1) & 0x3FFFF)*/
extern int mips32_pracc_read_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf);
extern int mips32_pracc_write_mem(mips_ejtag_t *ejtag_info, uint32_t addr, int size, int count, void *buf);

2
src/target/mips_ejtag.c
View File

@@ -292,7 +292,7 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
ejtag_info->impcode & (1 << 14) ? " noDMA": " DMA",
ejtag_info->impcode & (1 << 0) ? " MIPS64": " MIPS32"
);
);
if ((ejtag_info->impcode & (1 << 14)) == 0)
LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");

8
src/target/mips_m4k.c
View File

@@ -148,7 +148,7 @@ int mips_m4k_debug_entry(target_t *target)
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
*(uint32_t*)(mips32->core_cache->reg_list[MIPS32_PC].value),
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
return ERROR_OK;
}
@@ -220,7 +220,7 @@ int mips_m4k_halt(struct target_s *target)
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (target->state == TARGET_HALTED)
{
@@ -265,7 +265,7 @@ int mips_m4k_assert_reset(target_t *target)
mips_ejtag_t *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
enum reset_types jtag_reset_config = jtag_get_reset_config();
if (!(jtag_reset_config & RESET_HAS_SRST))
@@ -324,7 +324,7 @@ int mips_m4k_assert_reset(target_t *target)
int mips_m4k_deassert_reset(target_t *target)
{
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
/* deassert reset lines */
jtag_add_reset(0, 0);

2
src/target/register.c
View File

@@ -119,7 +119,7 @@ static int register_set_dummy_core_reg(reg_t *reg, uint8_t *buf)
void register_init_dummy(reg_t *reg)
{
static int dummy_arch_type = -1;
if (dummy_arch_type == -1 )
if (dummy_arch_type == -1)
dummy_arch_type = register_reg_arch_type(register_get_dummy_core_reg, register_set_dummy_core_reg);
reg->arch_type = dummy_arch_type;

542
src/target/target.c
View File

File diff suppressed because it is too large Load Diff

4
src/target/target.h
View File

@@ -397,7 +397,7 @@ int target_write_u8(struct target_s *target, uint32_t address, uint8_t value);
int target_arch_state(struct target_s *target);
void target_handle_event(target_t *t, enum target_event e);
void target_all_handle_event(enum target_event e );
void target_all_handle_event(enum target_event e);
#define ERROR_TARGET_INVALID (-300)
#define ERROR_TARGET_INIT_FAILED (-301)
@@ -412,6 +412,6 @@ void target_all_handle_event(enum target_event e );
#define ERROR_TARGET_NOT_EXAMINED (-311)
extern const Jim_Nvp nvp_error_target[];
extern const char *target_strerror_safe(int err );
extern const char *target_strerror_safe(int err);
#endif /* TARGET_H */

6
src/target/target_request.c
View File

@@ -117,8 +117,8 @@ int target_request(target_t *target, uint32_t request)
{
target_req_cmd_t target_req_cmd = request & 0xff;
if (charmsg_mode ) {
target_charmsg(target, target_req_cmd );
if (charmsg_mode) {
target_charmsg(target, target_req_cmd);
return ERROR_OK;
}
switch (target_req_cmd)
@@ -295,7 +295,7 @@ static int handle_target_request_debugmsgs_command(struct command_context_s *cmd
}
command_print(cmd_ctx, "receiving debug messages from current target %s",
(receiving) ? (charmsg_mode?"charmsg":"enabled") : "disabled" );
(receiving) ? (charmsg_mode?"charmsg":"enabled") : "disabled");
return ERROR_OK;
}

6
src/target/target_type.h
View File

@@ -129,16 +129,16 @@ struct target_type_s
int (*register_commands)(struct command_context_s *cmd_ctx);
/* called when target is created */
int (*target_create)(struct target_s *target, Jim_Interp *interp );
int (*target_create)(struct target_s *target, Jim_Interp *interp);
/* called for various config parameters */
/* returns JIM_CONTINUE - if option not understood */
/* otherwise: JIM_OK, or JIM_ERR, */
int (*target_jim_configure)(struct target_s *target, Jim_GetOptInfo *goi );
int (*target_jim_configure)(struct target_s *target, Jim_GetOptInfo *goi);
/* target commands specifically handled by the target */
/* returns JIM_OK, or JIM_ERR, or JIM_CONTINUE - if option not understood */
int (*target_jim_commands)(struct target_s *target, Jim_GetOptInfo *goi );
int (*target_jim_commands)(struct target_s *target, Jim_GetOptInfo *goi);
/* invoked after JTAG chain has been examined & validated. During
* this stage the target is examined and any additional setup is

2
src/target/trace.c
View File

@@ -123,7 +123,7 @@ static int handle_trace_history_command(struct command_context_s *cmd_ctx, char
uint32_t first = 0;
uint32_t last = trace->trace_history_pos;
if (!trace->trace_history_size ) {
if (!trace->trace_history_size) {
command_print(cmd_ctx, "trace history buffer is not allocated");
return ERROR_OK;
}

6
src/target/xscale.c
View File

@@ -959,7 +959,7 @@ int xscale_arch_state(struct target_s *target)
"MMU: %s, D-Cache: %s, I-Cache: %s"
"%s",
armv4_5_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason )->name ,
Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name ,
armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
@@ -1202,7 +1202,7 @@ int xscale_halt(target_t *target)
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
if (target->state == TARGET_HALTED)
{
@@ -1568,7 +1568,7 @@ int xscale_assert_reset(target_t *target)
xscale_common_t *xscale = armv4_5->arch_info;
LOG_DEBUG("target->state: %s",
Jim_Nvp_value2name_simple(nvp_target_state, target->state )->name);
Jim_Nvp_value2name_simple(nvp_target_state, target->state)->name);
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG