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armv7m: add FPU registers support

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This patch adds the fpv4-sp-d16 registers to the armv7m register set.

The work is inspired by Mathias K but takes a different approach:
instead of having both double and single presicion registers in the
cache this patch works only with the doubles and counts on GDB to
split the data in halves whenever needed.

Tested with HLA only (on an STM32F334 disco board).

Currently this patch makes all ARMv7-M targets report an FPU-enabled
target description to GDB. It shouldn't harm if the user is not trying
to access non-existing FPU. However, the plan is to make this depend
on actual FPU presence later.

Change-Id: Ifcc72c80ef745230c42e4dc3995f792753fc4e7a
Signed-off-by: Mathias K <kesmtp@freenet.de>
[fercerpav@gmail.com: rework to fit target description framework]
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/514
Tested-by: jenkins
Reviewed-by: Peter Stuge <peter@stuge.se>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
This commit is contained in:
Paul Fertser
2012-04-01 15:18:02 +02:00
parent ecf97f7c96
commit dccbf7d88d
8 changed files with 137 additions and 45 deletions
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26
src/target/hla_target.c
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@@ -75,11 +75,6 @@ static int adapter_load_core_reg_u32(struct target *target,
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
break;
case ARMV7M_FPSID:
case ARMV7M_FPEXC:
*value = 0;
break;
case ARMV7M_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33);
@@ -88,7 +83,7 @@ static int adapter_load_core_reg_u32(struct target *target,
retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
LOG_DEBUG("load from FPSCR value 0x%" PRIx32, *value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
@@ -99,11 +94,8 @@ static int adapter_load_core_reg_u32(struct target *target,
retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "", (int)num, *value);
break;
case ARMV7M_D0 ... ARMV7M_D15:
value = 0;
LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), *value);
break;
case ARMV7M_PRIMASK:
@@ -176,10 +168,6 @@ static int adapter_store_core_reg_u32(struct target *target,
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
break;
case ARMV7M_FPSID:
case ARMV7M_FPEXC:
break;
case ARMV7M_FPSCR:
/* Floating-point Status and Registers */
retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
@@ -188,7 +176,7 @@ static int adapter_store_core_reg_u32(struct target *target,
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, 33 | (1<<16));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
LOG_DEBUG("write FPSCR value 0x%" PRIx32, value);
break;
case ARMV7M_S0 ... ARMV7M_S31:
@@ -199,10 +187,8 @@ static int adapter_store_core_reg_u32(struct target *target,
retval = target_write_u32(target, ARMV7M_SCS_DCRSR, (num-ARMV7M_S0+64) | (1<<16));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
break;
case ARMV7M_D0 ... ARMV7M_D15:
LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32,
(int)(num - ARMV7M_S0), value);
break;
case ARMV7M_PRIMASK: