diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 9539a6437..ed9cb48aa 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -613,22 +613,22 @@ static int aarch64_restore_one(struct target *target, bool current, * kill the return address */ switch (arm->core_state) { - case ARM_STATE_ARM: - resume_pc &= 0xFFFFFFFC; - break; - case ARM_STATE_AARCH64: - resume_pc &= 0xFFFFFFFFFFFFFFFCULL; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - resume_pc |= 0x1; - break; - case ARM_STATE_JAZELLE: - LOG_ERROR("How do I resume into Jazelle state??"); - return ERROR_FAIL; + case ARM_STATE_ARM: + resume_pc &= 0xFFFFFFFC; + break; + case ARM_STATE_AARCH64: + resume_pc &= 0xFFFFFFFFFFFFFFFCULL; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + resume_pc |= 0x1; + break; + case ARM_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%016" PRIx64, resume_pc); buf_set_u64(arm->pc->value, 0, 64, resume_pc); @@ -3026,14 +3026,14 @@ COMMAND_HANDLER(aarch64_handle_disassemble_command) target_addr_t address; switch (CMD_ARGC) { - case 2: - COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); - /* FALL THROUGH */ - case 1: - COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 2: + COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count); + /* FALL THROUGH */ + case 1: + COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return a64_disassemble(CMD, target, address, count); diff --git a/src/target/arc.c b/src/target/arc.c index f2482c25e..638e22099 100644 --- a/src/target/arc.c +++ b/src/target/arc.c @@ -1892,18 +1892,18 @@ static int arc_set_watchpoint(struct target *target, int enable = AP_AC_TT_DISABLE; switch (watchpoint->rw) { - case WPT_READ: - enable = AP_AC_TT_READ; - break; - case WPT_WRITE: - enable = AP_AC_TT_WRITE; - break; - case WPT_ACCESS: - enable = AP_AC_TT_READWRITE; - break; - default: - LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access"); - return ERROR_FAIL; + case WPT_READ: + enable = AP_AC_TT_READ; + break; + case WPT_WRITE: + enable = AP_AC_TT_WRITE; + break; + case WPT_ACCESS: + enable = AP_AC_TT_READWRITE; + break; + default: + LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access"); + return ERROR_FAIL; } int retval = arc_configure_actionpoint(target, wp_num, diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c index bf8a8aa28..2e42398d2 100644 --- a/src/target/arc_cmd.c +++ b/src/target/arc_cmd.c @@ -709,29 +709,29 @@ COMMAND_HANDLER(arc_handle_get_reg_field) int retval = arc_reg_get_field(target, reg_name, field_name, &value); switch (retval) { - case ERROR_OK: - break; - case ERROR_ARC_REGISTER_NOT_FOUND: - command_print(CMD, - "Register `%s' has not been found.", reg_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - case ERROR_ARC_REGISTER_IS_NOT_STRUCT: - command_print(CMD, - "Register `%s' must have 'struct' type.", reg_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - case ERROR_ARC_REGISTER_FIELD_NOT_FOUND: - command_print(CMD, - "Field `%s' has not been found in register `%s'.", - field_name, reg_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - case ERROR_ARC_FIELD_IS_NOT_BITFIELD: - command_print(CMD, - "Field `%s' is not a 'bitfield' field in a structure.", - field_name); - return ERROR_COMMAND_ARGUMENT_INVALID; - default: - /* Pass through other errors. */ - return retval; + case ERROR_OK: + break; + case ERROR_ARC_REGISTER_NOT_FOUND: + command_print(CMD, + "Register `%s' has not been found.", reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + case ERROR_ARC_REGISTER_IS_NOT_STRUCT: + command_print(CMD, + "Register `%s' must have 'struct' type.", reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + case ERROR_ARC_REGISTER_FIELD_NOT_FOUND: + command_print(CMD, + "Field `%s' has not been found in register `%s'.", + field_name, reg_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + case ERROR_ARC_FIELD_IS_NOT_BITFIELD: + command_print(CMD, + "Field `%s' is not a 'bitfield' field in a structure.", + field_name); + return ERROR_COMMAND_ARGUMENT_INVALID; + default: + /* Pass through other errors. */ + return retval; } command_print(CMD, "0x%" PRIx32, value); diff --git a/src/target/arm11.c b/src/target/arm11.c index a3e3ef843..81026c68c 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -414,19 +414,19 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, bool current, * kill the return address */ switch (arm11->arm.core_state) { - case ARM_STATE_ARM: - address &= 0xFFFFFFFC; - break; - case ARM_STATE_THUMB: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - address |= 0x1; - break; + case ARM_STATE_ARM: + address &= 0xFFFFFFFC; + break; + case ARM_STATE_THUMB: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + address |= 0x1; + break; - /* catch-all for JAZELLE and THUMB_EE */ - default: - break; + /* catch-all for JAZELLE and THUMB_EE */ + default: + break; } buf_set_u32(value, 0, 32, address); @@ -819,44 +819,44 @@ static int arm11_read_memory_inner(struct target *target, return retval; switch (size) { - case 1: - arm11->arm.core_cache->reg_list[1].dirty = true; + case 1: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) { - /* ldrb r1, [r0], #1 */ - /* ldrb r1, [r0] */ - CHECK_RETVAL(arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); + for (size_t i = 0; i < count; i++) { + /* ldrb r1, [r0], #1 */ + /* ldrb r1, [r0] */ + CHECK_RETVAL(arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe4d01001 : 0xe5d01000)); - uint32_t res; - /* MCR p14,0,R1,c0,c5,0 */ - CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); + uint32_t res; + /* MCR p14,0,R1,c0,c5,0 */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); - *buffer++ = res; - } + *buffer++ = res; + } - break; + break; - case 2: - arm11->arm.core_cache->reg_list[1].dirty = true; + case 2: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) { - /* ldrh r1, [r0], #2 */ - CHECK_RETVAL(arm11_run_instr_no_data1(arm11, - !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); + for (size_t i = 0; i < count; i++) { + /* ldrh r1, [r0], #2 */ + CHECK_RETVAL(arm11_run_instr_no_data1(arm11, + !arm11_config_memrw_no_increment ? 0xe0d010b2 : 0xe1d010b0)); - uint32_t res; + uint32_t res; - /* MCR p14,0,R1,c0,c5,0 */ - CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); + /* MCR p14,0,R1,c0,c5,0 */ + CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1)); - uint16_t svalue = res; - memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); - } + uint16_t svalue = res; + memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t)); + } - break; + break; - case 4: + case 4: { uint32_t instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00; /** \todo TODO: buffer cast to uint32_t* causes alignment warnings */ @@ -925,52 +925,52 @@ static int arm11_write_memory_inner(struct target *target, bool burst = arm11->memwrite_burst && (count > 1); switch (size) { - case 1: - arm11->arm.core_cache->reg_list[1].dirty = true; + case 1: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) { - /* load r1 from DCC with byte data */ - /* MRC p14,0,r1,c0,c5,0 */ - retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); - if (retval != ERROR_OK) - return retval; + for (size_t i = 0; i < count; i++) { + /* load r1 from DCC with byte data */ + /* MRC p14,0,r1,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++); + if (retval != ERROR_OK) + return retval; - /* write r1 to memory */ - /* strb r1, [r0], #1 */ - /* strb r1, [r0] */ - retval = arm11_run_instr_no_data1(arm11, - !no_increment ? 0xe4c01001 : 0xe5c01000); - if (retval != ERROR_OK) - return retval; - } + /* write r1 to memory */ + /* strb r1, [r0], #1 */ + /* strb r1, [r0] */ + retval = arm11_run_instr_no_data1(arm11, + !no_increment ? 0xe4c01001 : 0xe5c01000); + if (retval != ERROR_OK) + return retval; + } - break; + break; - case 2: - arm11->arm.core_cache->reg_list[1].dirty = true; + case 2: + arm11->arm.core_cache->reg_list[1].dirty = true; - for (size_t i = 0; i < count; i++) { - uint16_t value; - memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); + for (size_t i = 0; i < count; i++) { + uint16_t value; + memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t)); - /* load r1 from DCC with halfword data */ - /* MRC p14,0,r1,c0,c5,0 */ - retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); - if (retval != ERROR_OK) - return retval; + /* load r1 from DCC with halfword data */ + /* MRC p14,0,r1,c0,c5,0 */ + retval = arm11_run_instr_data_to_core1(arm11, 0xee101e15, value); + if (retval != ERROR_OK) + return retval; - /* write r1 to memory */ - /* strh r1, [r0], #2 */ - /* strh r1, [r0] */ - retval = arm11_run_instr_no_data1(arm11, - !no_increment ? 0xe0c010b2 : 0xe1c010b0); - if (retval != ERROR_OK) - return retval; - } + /* write r1 to memory */ + /* strh r1, [r0], #2 */ + /* strh r1, [r0] */ + retval = arm11_run_instr_no_data1(arm11, + !no_increment ? 0xe0c010b2 : 0xe1c010b0); + if (retval != ERROR_OK) + return retval; + } - break; + break; - case 4: + case 4: { /* stream word data through DCC directly to memory */ /* increment: STC p14,c5,[R0],#4 */ @@ -1159,34 +1159,34 @@ static int arm11_examine(struct target *target) /* assume the manufacturer id is ok; check the part # */ switch ((device_id >> 12) & 0xFFFF) { - case 0x7B36: - type = "ARM1136"; - break; - case 0x7B37: - type = "ARM11 MPCore"; - break; - case 0x7B56: - type = "ARM1156"; - break; - case 0x7B76: - arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT; - /* NOTE: could default arm11->hardware_step to true */ - type = "ARM1176"; - break; - default: - LOG_ERROR("unexpected ARM11 ID code"); - return ERROR_FAIL; + case 0x7B36: + type = "ARM1136"; + break; + case 0x7B37: + type = "ARM11 MPCore"; + break; + case 0x7B56: + type = "ARM1156"; + break; + case 0x7B76: + arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT; + /* NOTE: could default arm11->hardware_step to true */ + type = "ARM1176"; + break; + default: + LOG_ERROR("unexpected ARM11 ID code"); + return ERROR_FAIL; } LOG_INFO("found %s", type); /* unlikely this could ever fail, but ... */ switch ((didr >> 16) & 0x0F) { - case ARM11_DEBUG_V6: - case ARM11_DEBUG_V61: /* supports security extensions */ - break; - default: - LOG_ERROR("Only ARM v6 and v6.1 debug supported."); - return ERROR_FAIL; + case ARM11_DEBUG_V6: + case ARM11_DEBUG_V61: /* supports security extensions */ + break; + default: + LOG_ERROR("Only ARM v6 and v6.1 debug supported."); + return ERROR_FAIL; } arm11->brp = ((didr >> 24) & 0x0F) + 1; @@ -1250,13 +1250,13 @@ COMMAND_HANDLER(arm11_handle_vcr) struct arm11_common *arm11 = target_to_arm11(target); switch (CMD_ARGC) { - case 0: - break; - case 1: - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + break; + case 1: + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], arm11->vcr); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } LOG_INFO("VCR 0x%08" PRIx32, arm11->vcr); diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 4c7211365..4c2fedaeb 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -85,30 +85,30 @@ static const char *arm11_ir_to_string(uint8_t ir) const char *s = "unknown"; switch (ir) { - case ARM11_EXTEST: - s = "EXTEST"; - break; - case ARM11_SCAN_N: - s = "SCAN_N"; - break; - case ARM11_RESTART: - s = "RESTART"; - break; - case ARM11_HALT: - s = "HALT"; - break; - case ARM11_INTEST: - s = "INTEST"; - break; - case ARM11_ITRSEL: - s = "ITRSEL"; - break; - case ARM11_IDCODE: - s = "IDCODE"; - break; - case ARM11_BYPASS: - s = "BYPASS"; - break; + case ARM11_EXTEST: + s = "EXTEST"; + break; + case ARM11_SCAN_N: + s = "SCAN_N"; + break; + case ARM11_RESTART: + s = "RESTART"; + break; + case ARM11_HALT: + s = "HALT"; + break; + case ARM11_INTEST: + s = "INTEST"; + break; + case ARM11_ITRSEL: + s = "ITRSEL"; + break; + case ARM11_IDCODE: + s = "IDCODE"; + break; + case ARM11_BYPASS: + s = "BYPASS"; + break; } return s; } @@ -1061,17 +1061,17 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, action[1].value = control; switch (index_t) { - case 0 ... 15: - action[0].address = ARM11_SC7_BVR0 + index_t; - action[1].address = ARM11_SC7_BCR0 + index_t; - break; - case 16 ... 32: - index_t -= 16; - action[0].address = ARM11_SC7_WVR0 + index_t; - action[1].address = ARM11_SC7_WCR0 + index_t; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + action[0].address = ARM11_SC7_BVR0 + index_t; + action[1].address = ARM11_SC7_BCR0 + index_t; + break; + case 16 ... 32: + index_t -= 16; + action[0].address = ARM11_SC7_WVR0 + index_t; + action[1].address = ARM11_SC7_WCR0 + index_t; + break; + default: + return ERROR_FAIL; } arm11->bpwp_n += 2; @@ -1090,15 +1090,15 @@ static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) action[0].value = 0; switch (index_t) { - case 0 ... 15: - action[0].address = ARM11_SC7_BCR0 + index_t; - break; - case 16 ... 32: - index_t -= 16; - action[0].address = ARM11_SC7_WCR0 + index_t; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + action[0].address = ARM11_SC7_BCR0 + index_t; + break; + case 16 ... 32: + index_t -= 16; + action[0].address = ARM11_SC7_WCR0 + index_t; + break; + default: + return ERROR_FAIL; } arm11->bpwp_n += 1; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index 3a066e07d..c4bedcd85 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2136,18 +2136,48 @@ int arm7_9_read_memory(struct target *target, arm7_9->write_core_regs(target, 0x1, reg); switch (size) { - case 4: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + case 4: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - if (last_reg <= thisrun_accesses) - last_reg = thisrun_accesses; + if (last_reg <= thisrun_accesses) + last_reg = thisrun_accesses; - arm7_9->load_word_regs(target, reg_list); + arm7_9->load_word_regs(target, reg_list); + /* fast memory reads are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) + retval = arm7_9_execute_fast_sys_speed(target); + else + retval = arm7_9_execute_sys_speed(target); + if (retval != ERROR_OK) + return retval; + + arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4); + + /* advance buffer, count number of accesses */ + buffer += thisrun_accesses * 4; + num_accesses += thisrun_accesses; + + keep_alive(); + } + break; + case 2: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + arm7_9->load_hword_reg(target, i); /* fast memory reads are only safe when the target is running * from a sufficiently high clock (32 kHz is usually too slow) */ @@ -2158,78 +2188,48 @@ int arm7_9_read_memory(struct target *target, if (retval != ERROR_OK) return retval; - arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 4); - - /* advance buffer, count number of accesses */ - buffer += thisrun_accesses * 4; - num_accesses += thisrun_accesses; - - keep_alive(); } - break; - case 2: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - arm7_9->load_hword_reg(target, i); - /* fast memory reads are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) - */ - if (arm7_9->fast_memory_access) - retval = arm7_9_execute_fast_sys_speed(target); - else - retval = arm7_9_execute_sys_speed(target); - if (retval != ERROR_OK) - return retval; + arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); - } + /* advance buffer, count number of accesses */ + buffer += thisrun_accesses * 2; + num_accesses += thisrun_accesses; - arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 2); + keep_alive(); + } + break; + case 1: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - /* advance buffer, count number of accesses */ - buffer += thisrun_accesses * 2; - num_accesses += thisrun_accesses; - - keep_alive(); + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + arm7_9->load_byte_reg(target, i); + /* fast memory reads are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) + retval = arm7_9_execute_fast_sys_speed(target); + else + retval = arm7_9_execute_sys_speed(target); + if (retval != ERROR_OK) + return retval; } - break; - case 1: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - arm7_9->load_byte_reg(target, i); - /* fast memory reads are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) - */ - if (arm7_9->fast_memory_access) - retval = arm7_9_execute_fast_sys_speed(target); - else - retval = arm7_9_execute_sys_speed(target); - if (retval != ERROR_OK) - return retval; - } + arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); - arm7_9->read_core_regs_target_buffer(target, reg_list, buffer, 1); + /* advance buffer, count number of accesses */ + buffer += thisrun_accesses * 1; + num_accesses += thisrun_accesses; - /* advance buffer, count number of accesses */ - buffer += thisrun_accesses * 1; - num_accesses += thisrun_accesses; - - keep_alive(); - } - break; + keep_alive(); + } + break; } if (!is_arm_mode(arm->core_mode)) @@ -2308,23 +2308,67 @@ int arm7_9_write_memory(struct target *target, embeddedice_store_reg(dbg_ctrl); switch (size) { - case 4: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + case 4: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - reg[i] = target_buffer_get_u32(target, buffer); - buffer += 4; - } + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + reg[i] = target_buffer_get_u32(target, buffer); + buffer += 4; + } - arm7_9->write_core_regs(target, reg_list, reg); + arm7_9->write_core_regs(target, reg_list, reg); - arm7_9->store_word_regs(target, reg_list); + arm7_9->store_word_regs(target, reg_list); + + /* fast memory writes are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) { + retval = arm7_9_execute_fast_sys_speed(target); + } else { + retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. + */ + + keep_alive(); + } + + if (retval != ERROR_OK) + return retval; + + num_accesses += thisrun_accesses; + } + break; + case 2: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; + + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + reg[i] = target_buffer_get_u16(target, buffer) & 0xffff; + buffer += 2; + } + + arm7_9->write_core_regs(target, reg_list, reg); + + for (i = 1; i <= thisrun_accesses; i++) { + arm7_9->store_hword_reg(target, i); /* fast memory writes are only safe when the target is running * from a sufficiently high clock (32 kHz is usually too slow) @@ -2347,99 +2391,55 @@ int arm7_9_write_memory(struct target *target, if (retval != ERROR_OK) return retval; - - num_accesses += thisrun_accesses; } - break; - case 2: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - reg[i] = target_buffer_get_u16(target, buffer) & 0xffff; - buffer += 2; - } + num_accesses += thisrun_accesses; + } + break; + case 1: + while (num_accesses < count) { + uint32_t reg_list; + thisrun_accesses = + ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); + reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - arm7_9->write_core_regs(target, reg_list, reg); + for (i = 1; i <= thisrun_accesses; i++) { + if (i > last_reg) + last_reg = i; + reg[i] = *buffer++ & 0xff; + } - for (i = 1; i <= thisrun_accesses; i++) { - arm7_9->store_hword_reg(target, i); + arm7_9->write_core_regs(target, reg_list, reg); - /* fast memory writes are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) + for (i = 1; i <= thisrun_accesses; i++) { + arm7_9->store_byte_reg(target, i); + /* fast memory writes are only safe when the target is running + * from a sufficiently high clock (32 kHz is usually too slow) + */ + if (arm7_9->fast_memory_access) { + retval = arm7_9_execute_fast_sys_speed(target); + } else { + retval = arm7_9_execute_sys_speed(target); + + /* + * if memory writes are made when the clock is running slow + * (i.e. 32 kHz) which is necessary in some scripts to reconfigure + * processor operations after a "reset halt" or "reset init", + * need to immediately stroke the keep alive or will end up with + * gdb "keep alive not sent error message" problem. */ - if (arm7_9->fast_memory_access) { - retval = arm7_9_execute_fast_sys_speed(target); - } else { - retval = arm7_9_execute_sys_speed(target); - /* - * if memory writes are made when the clock is running slow - * (i.e. 32 kHz) which is necessary in some scripts to reconfigure - * processor operations after a "reset halt" or "reset init", - * need to immediately stroke the keep alive or will end up with - * gdb "keep alive not sent error message" problem. - */ - - keep_alive(); - } - - if (retval != ERROR_OK) - return retval; + keep_alive(); } - num_accesses += thisrun_accesses; + if (retval != ERROR_OK) + return retval; + } - break; - case 1: - while (num_accesses < count) { - uint32_t reg_list; - thisrun_accesses = - ((count - num_accesses) >= 14) ? 14 : (count - num_accesses); - reg_list = (0xffff >> (15 - thisrun_accesses)) & 0xfffe; - for (i = 1; i <= thisrun_accesses; i++) { - if (i > last_reg) - last_reg = i; - reg[i] = *buffer++ & 0xff; - } - - arm7_9->write_core_regs(target, reg_list, reg); - - for (i = 1; i <= thisrun_accesses; i++) { - arm7_9->store_byte_reg(target, i); - /* fast memory writes are only safe when the target is running - * from a sufficiently high clock (32 kHz is usually too slow) - */ - if (arm7_9->fast_memory_access) { - retval = arm7_9_execute_fast_sys_speed(target); - } else { - retval = arm7_9_execute_sys_speed(target); - - /* - * if memory writes are made when the clock is running slow - * (i.e. 32 kHz) which is necessary in some scripts to reconfigure - * processor operations after a "reset halt" or "reset init", - * need to immediately stroke the keep alive or will end up with - * gdb "keep alive not sent error message" problem. - */ - - keep_alive(); - } - - if (retval != ERROR_OK) - return retval; - - } - - num_accesses += thisrun_accesses; - } - break; + num_accesses += thisrun_accesses; + } + break; } /* Re-Set DBGACK */ diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c index 2f59254af..fea6a3ff2 100644 --- a/src/target/arm7tdmi.c +++ b/src/target/arm7tdmi.c @@ -327,15 +327,15 @@ static void arm7tdmi_read_core_regs_target_buffer(struct target *target, /* nothing fetched, STM still in EXECUTE (1 + i cycle), read databus */ if (mask & (1 << i)) { switch (size) { - case 4: - arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); - break; - case 2: - arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); - break; - case 1: - arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); - break; + case 4: + arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); + break; + case 2: + arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); + break; + case 1: + arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); + break; } } } diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 55ddb6313..0b77981ae 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -221,88 +221,88 @@ static int arm926ejs_examine_debug_reason(struct target *target) debug_reason = buf_get_u32(dbg_stat->value, 6, 4); switch (debug_reason) { - case 0: - LOG_DEBUG("no *NEW* debug entry (?missed one?)"); - /* ... since last restart or debug reset ... */ - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 1: - LOG_DEBUG("breakpoint from EICE unit 0"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 2: - LOG_DEBUG("breakpoint from EICE unit 1"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 3: - LOG_DEBUG("soft breakpoint (BKPT instruction)"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 4: - LOG_DEBUG("vector catch breakpoint"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 5: - LOG_DEBUG("external breakpoint"); - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case 6: - LOG_DEBUG("watchpoint from EICE unit 0"); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case 7: - LOG_DEBUG("watchpoint from EICE unit 1"); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case 8: - LOG_DEBUG("external watchpoint"); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case 9: - LOG_DEBUG("internal debug request"); - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 10: - LOG_DEBUG("external debug request"); - target->debug_reason = DBG_REASON_DBGRQ; - break; - case 11: - LOG_DEBUG("debug re-entry from system speed access"); - /* This is normal when connecting to something that's - * already halted, or in some related code paths, but - * otherwise is surprising (and presumably wrong). - */ - switch (target->debug_reason) { - case DBG_REASON_DBGRQ: - break; - default: - LOG_ERROR("unexpected -- debug re-entry"); - /* FALLTHROUGH */ - case DBG_REASON_UNDEFINED: - target->debug_reason = DBG_REASON_DBGRQ; - break; - } - break; - case 12: - /* FIX!!!! here be dragons!!! We need to fail here so - * the target will interpreted as halted but we won't - * try to talk to it right now... a resume + halt seems - * to sync things up again. Please send an email to - * openocd development mailing list if you have hardware - * to donate to look into this problem.... - */ - LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt."); - target->debug_reason = DBG_REASON_DBGRQ; + case 0: + LOG_DEBUG("no *NEW* debug entry (?missed one?)"); + /* ... since last restart or debug reset ... */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 1: + LOG_DEBUG("breakpoint from EICE unit 0"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 2: + LOG_DEBUG("breakpoint from EICE unit 1"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 3: + LOG_DEBUG("soft breakpoint (BKPT instruction)"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 4: + LOG_DEBUG("vector catch breakpoint"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 5: + LOG_DEBUG("external breakpoint"); + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case 6: + LOG_DEBUG("watchpoint from EICE unit 0"); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case 7: + LOG_DEBUG("watchpoint from EICE unit 1"); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case 8: + LOG_DEBUG("external watchpoint"); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case 9: + LOG_DEBUG("internal debug request"); + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 10: + LOG_DEBUG("external debug request"); + target->debug_reason = DBG_REASON_DBGRQ; + break; + case 11: + LOG_DEBUG("debug re-entry from system speed access"); + /* This is normal when connecting to something that's + * already halted, or in some related code paths, but + * otherwise is surprising (and presumably wrong). + */ + switch (target->debug_reason) { + case DBG_REASON_DBGRQ: break; default: - LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); - /* Oh agony! should we interpret this as a halt request or - * that the target stopped on it's own accord? - */ + LOG_ERROR("unexpected -- debug re-entry"); + /* FALLTHROUGH */ + case DBG_REASON_UNDEFINED: target->debug_reason = DBG_REASON_DBGRQ; - /* if we fail here, we won't talk to the target and it will - * be reported to be in the halted state */ break; + } + break; + case 12: + /* FIX!!!! here be dragons!!! We need to fail here so + * the target will interpreted as halted but we won't + * try to talk to it right now... a resume + halt seems + * to sync things up again. Please send an email to + * openocd development mailing list if you have hardware + * to donate to look into this problem.... + */ + LOG_WARNING("WARNING: mystery debug reason MOE = 0xc. Try issuing a resume + halt."); + target->debug_reason = DBG_REASON_DBGRQ; + break; + default: + LOG_WARNING("WARNING: unknown debug reason: 0x%x", debug_reason); + /* Oh agony! should we interpret this as a halt request or + * that the target stopped on it's own accord? + */ + target->debug_reason = DBG_REASON_DBGRQ; + /* if we fail here, we won't talk to the target and it will + * be reported to be in the halted state */ + break; } return ERROR_OK; diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c index 8ab12de32..34b4ba2ce 100644 --- a/src/target/arm9tdmi.c +++ b/src/target/arm9tdmi.c @@ -398,15 +398,15 @@ static void arm9tdmi_read_core_regs_target_buffer(struct target *target, if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ switch (size) { - case 4: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); - break; - case 2: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); - break; - case 1: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); - break; + case 4: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); + break; + case 2: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); + break; + case 1: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); + break; } } } diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c index be5e63c7c..5ba5e1c38 100644 --- a/src/target/arm_dap.c +++ b/src/target/arm_dap.c @@ -442,28 +442,28 @@ COMMAND_HANDLER(handle_dap_info_command) } switch (CMD_ARGC) { - case 0: - apsel = dap->apsel; - break; - case 1: - if (!strcmp(CMD_ARGV[0], "root")) { - if (!is_adiv6(dap)) { - command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP"); - return ERROR_COMMAND_ARGUMENT_INVALID; - } - int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel); - if (retval != ERROR_OK) { - command_print(CMD, "Failed reading DAP baseptr"); - return retval; - } - break; + case 0: + apsel = dap->apsel; + break; + case 1: + if (!strcmp(CMD_ARGV[0], "root")) { + if (!is_adiv6(dap)) { + command_print(CMD, "Option \"root\" not allowed with ADIv5 DAP"); + return ERROR_COMMAND_ARGUMENT_INVALID; + } + int retval = adiv6_dap_read_baseptr(CMD, dap, &apsel); + if (retval != ERROR_OK) { + command_print(CMD, "Failed reading DAP baseptr"); + return retval; } - COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel); - if (!is_ap_num_valid(dap, apsel)) - return ERROR_COMMAND_SYNTAX_ERROR; break; - default: + } + COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], apsel); + if (!is_ap_num_valid(dap, apsel)) return ERROR_COMMAND_SYNTAX_ERROR; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } struct adiv5_ap *ap = dap_get_ap(dap, apsel); diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 820b2c02b..6dea19f93 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -248,39 +248,39 @@ static int evaluate_srs(uint32_t opcode, const char *mode = ""; switch ((opcode >> 23) & 0x3) { - case 0: - mode = "DA"; - break; - case 1: - /* "IA" is default */ - break; - case 2: - mode = "DB"; - break; - case 3: - mode = "IB"; - break; + case 0: + mode = "DA"; + break; + case 1: + /* "IA" is default */ + break; + case 2: + mode = "DB"; + break; + case 3: + mode = "IB"; + break; } switch (opcode & 0x0e500000) { - case 0x08400000: - snprintf(instruction->text, 128, "0x%8.8" PRIx32 - "\t0x%8.8" PRIx32 - "\tSRS%s\tSP%s, #%" PRIu32, - address, opcode, - mode, wback, - opcode & 0x1f); - break; - case 0x08100000: - snprintf(instruction->text, 128, "0x%8.8" PRIx32 - "\t0x%8.8" PRIx32 - "\tRFE%s\tr%" PRIu32 "%s", - address, opcode, - mode, - (opcode >> 16) & 0xf, wback); - break; - default: - return evaluate_unknown(opcode, address, instruction); + case 0x08400000: + snprintf(instruction->text, 128, "0x%8.8" PRIx32 + "\t0x%8.8" PRIx32 + "\tSRS%s\tSP%s, #%" PRIu32, + address, opcode, + mode, wback, + opcode & 0x1f); + break; + case 0x08100000: + snprintf(instruction->text, 128, "0x%8.8" PRIx32 + "\t0x%8.8" PRIx32 + "\tRFE%s\tr%" PRIu32 "%s", + address, opcode, + mode, + (opcode >> 16) & 0xf, wback); + break; + default: + return evaluate_unknown(opcode, address, instruction); } return ERROR_OK; } @@ -631,21 +631,21 @@ static int evaluate_load_store(uint32_t opcode, snprintf(offset, 32, ", %sr%i", (u) ? "" : "-", rm); else { /* +-, , # */ switch (shift) { - case 0x0: /* LSL */ - snprintf(offset, 32, ", %sr%i, LSL #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x1: /* LSR */ - snprintf(offset, 32, ", %sr%i, LSR #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x2: /* ASR */ - snprintf(offset, 32, ", %sr%i, ASR #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x3: /* ROR */ - snprintf(offset, 32, ", %sr%i, ROR #0x%x", (u) ? "" : "-", rm, shift_imm); - break; - case 0x4: /* RRX */ - snprintf(offset, 32, ", %sr%i, RRX", (u) ? "" : "-", rm); - break; + case 0x0: /* LSL */ + snprintf(offset, 32, ", %sr%i, LSL #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x1: /* LSR */ + snprintf(offset, 32, ", %sr%i, LSR #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x2: /* ASR */ + snprintf(offset, 32, ", %sr%i, ASR #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x3: /* ROR */ + snprintf(offset, 32, ", %sr%i, ROR #0x%x", (u) ? "" : "-", rm, shift_imm); + break; + case 0x4: /* RRX */ + snprintf(offset, 32, ", %sr%i, RRX", (u) ? "" : "-", rm); + break; } } } @@ -707,33 +707,33 @@ static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp) char *type, *rot; switch ((opcode >> 24) & 0x3) { - case 0: - type = "B16"; - break; - case 1: - sprintf(cp, "UNDEFINED"); - return ARM_UNDEFINED_INSTRUCTION; - case 2: - type = "B"; - break; - default: - type = "H"; - break; + case 0: + type = "B16"; + break; + case 1: + sprintf(cp, "UNDEFINED"); + return ARM_UNDEFINED_INSTRUCTION; + case 2: + type = "B"; + break; + default: + type = "H"; + break; } switch ((opcode >> 10) & 0x3) { - case 0: - rot = ""; - break; - case 1: - rot = ", ROR #8"; - break; - case 2: - rot = ", ROR #16"; - break; - default: - rot = ", ROR #24"; - break; + case 0: + rot = ""; + break; + case 1: + rot = ", ROR #8"; + break; + case 2: + rot = ", ROR #16"; + break; + default: + rot = ", ROR #24"; + break; } if (rn == 0xf) { @@ -758,55 +758,55 @@ static int evaluate_p_add_sub(uint32_t opcode, uint32_t address, char *cp) int type; switch ((opcode >> 20) & 0x7) { - case 1: - prefix = "S"; - break; - case 2: - prefix = "Q"; - break; - case 3: - prefix = "SH"; - break; - case 5: - prefix = "U"; - break; - case 6: - prefix = "UQ"; - break; - case 7: - prefix = "UH"; - break; - default: - goto undef; + case 1: + prefix = "S"; + break; + case 2: + prefix = "Q"; + break; + case 3: + prefix = "SH"; + break; + case 5: + prefix = "U"; + break; + case 6: + prefix = "UQ"; + break; + case 7: + prefix = "UH"; + break; + default: + goto undef; } switch ((opcode >> 5) & 0x7) { - case 0: - op = "ADD16"; - type = ARM_ADD; - break; - case 1: - op = "ADDSUBX"; - type = ARM_ADD; - break; - case 2: - op = "SUBADDX"; - type = ARM_SUB; - break; - case 3: - op = "SUB16"; - type = ARM_SUB; - break; - case 4: - op = "ADD8"; - type = ARM_ADD; - break; - case 7: - op = "SUB8"; - type = ARM_SUB; - break; - default: - goto undef; + case 0: + op = "ADD16"; + type = ARM_ADD; + break; + case 1: + op = "ADDSUBX"; + type = ARM_ADD; + break; + case 2: + op = "SUBADDX"; + type = ARM_SUB; + break; + case 3: + op = "SUB16"; + type = ARM_SUB; + break; + case 4: + op = "ADD8"; + type = ARM_ADD; + break; + case 7: + op = "SUB8"; + type = ARM_SUB; + break; + default: + goto undef; } sprintf(cp, "%s%s%s\tr%d, r%d, r%d", prefix, op, COND(opcode), @@ -928,14 +928,14 @@ static int evaluate_media(uint32_t opcode, uint32_t address, unsigned int rn = (opcode >> 12) & 0xf; switch (opcode & 0xc0) { - case 3: - if (rn == 0xf) - goto undef; - /* FALL THROUGH */ - case 0: - break; - default: + case 3: + if (rn == 0xf) goto undef; + /* FALL THROUGH */ + case 0: + break; + default: + goto undef; } if (rn != 0xf) @@ -959,46 +959,46 @@ static int evaluate_media(uint32_t opcode, uint32_t address, /* simple matches against the remaining decode bits */ switch (opcode & 0x01f000f0) { - case 0x00a00030: - case 0x00e00030: - /* parallel halfword saturate */ - sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d", - (opcode & (1 << 22)) ? 'U' : 'S', - COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - return ERROR_OK; - case 0x00b00030: - mnemonic = "REV"; - break; - case 0x00b000b0: - mnemonic = "REV16"; - break; - case 0x00f000b0: - mnemonic = "REVSH"; - break; - case 0x008000b0: - /* select bytes */ - sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode), - (int) (opcode >> 12) & 0xf, - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf); - return ERROR_OK; - case 0x01800010: - /* unsigned sum of absolute differences */ - if (((opcode >> 12) & 0xf) == 0xf) - sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf); - else - sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode), - (int) (opcode >> 16) & 0xf, - (int) (opcode >> 0) & 0xf, - (int) (opcode >> 8) & 0xf, - (int) (opcode >> 12) & 0xf); - return ERROR_OK; + case 0x00a00030: + case 0x00e00030: + /* parallel halfword saturate */ + sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d", + (opcode & (1 << 22)) ? 'U' : 'S', + COND(opcode), + (int)(opcode >> 12) & 0xf, + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf); + return ERROR_OK; + case 0x00b00030: + mnemonic = "REV"; + break; + case 0x00b000b0: + mnemonic = "REV16"; + break; + case 0x00f000b0: + mnemonic = "REVSH"; + break; + case 0x008000b0: + /* select bytes */ + sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode), + (int)(opcode >> 12) & 0xf, + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf); + return ERROR_OK; + case 0x01800010: + /* unsigned sum of absolute differences */ + if (((opcode >> 12) & 0xf) == 0xf) + sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode), + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf, + (int)(opcode >> 8) & 0xf); + else + sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode), + (int)(opcode >> 16) & 0xf, + (int)(opcode >> 0) & 0xf, + (int)(opcode >> 8) & 0xf, + (int)(opcode >> 12) & 0xf); + return ERROR_OK; } if (mnemonic) { unsigned int rm = (opcode >> 0) & 0xf; @@ -1280,22 +1280,22 @@ static int evaluate_mul_and_extra_ld_st(uint32_t opcode, s = (opcode & 0x00100000) >> 20; switch ((opcode & 0x00600000) >> 21) { - case 0x0: - instruction->type = ARM_UMULL; - mnemonic = "UMULL"; - break; - case 0x1: - instruction->type = ARM_UMLAL; - mnemonic = "UMLAL"; - break; - case 0x2: - instruction->type = ARM_SMULL; - mnemonic = "SMULL"; - break; - case 0x3: - instruction->type = ARM_SMLAL; - mnemonic = "SMLAL"; - break; + case 0x0: + instruction->type = ARM_UMULL; + mnemonic = "UMULL"; + break; + case 0x1: + instruction->type = ARM_UMLAL; + mnemonic = "UMLAL"; + break; + case 0x2: + instruction->type = ARM_SMULL; + mnemonic = "SMULL"; + break; + case 0x3: + instruction->type = ARM_SMLAL; + mnemonic = "SMLAL"; + break; } snprintf(instruction->text, @@ -1480,22 +1480,22 @@ static int evaluate_misc_instr(uint32_t opcode, rn = (opcode & 0xf0000) >> 16; switch ((opcode & 0x00600000) >> 21) { - case 0x0: - instruction->type = ARM_QADD; - mnemonic = "QADD"; - break; - case 0x1: - instruction->type = ARM_QSUB; - mnemonic = "QSUB"; - break; - case 0x2: - instruction->type = ARM_QDADD; - mnemonic = "QDADD"; - break; - case 0x3: - instruction->type = ARM_QDSUB; - mnemonic = "QDSUB"; - break; + case 0x0: + instruction->type = ARM_QADD; + mnemonic = "QADD"; + break; + case 0x1: + instruction->type = ARM_QSUB; + mnemonic = "QSUB"; + break; + case 0x2: + instruction->type = ARM_QDADD; + mnemonic = "QDADD"; + break; + case 0x3: + instruction->type = ARM_QDSUB; + mnemonic = "QDSUB"; + break; } snprintf(instruction->text, @@ -1527,21 +1527,21 @@ static int evaluate_misc_instr(uint32_t opcode, char *mnemonic = NULL; switch ((opcode & 0x600000) >> 21) { - case 0x1: - instruction->type = ARM_BKPT; - mnemonic = "BRKT"; - immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); - break; - case 0x2: - instruction->type = ARM_HVC; - mnemonic = "HVC"; - immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); - break; - case 0x3: - instruction->type = ARM_SMC; - mnemonic = "SMC"; - immediate = (opcode & 0xf); - break; + case 0x1: + instruction->type = ARM_BKPT; + mnemonic = "BRKT"; + immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); + break; + case 0x2: + instruction->type = ARM_HVC; + mnemonic = "HVC"; + immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf); + break; + case 0x3: + instruction->type = ARM_SMC; + mnemonic = "SMC"; + immediate = (opcode & 0xf); + break; } snprintf(instruction->text, @@ -1717,70 +1717,70 @@ static int evaluate_data_proc(uint32_t opcode, instruction->info.data_proc.s = s; switch (op) { - case 0x0: - instruction->type = ARM_AND; - mnemonic = "AND"; - break; - case 0x1: - instruction->type = ARM_EOR; - mnemonic = "EOR"; - break; - case 0x2: - instruction->type = ARM_SUB; - mnemonic = "SUB"; - break; - case 0x3: - instruction->type = ARM_RSB; - mnemonic = "RSB"; - break; - case 0x4: - instruction->type = ARM_ADD; - mnemonic = "ADD"; - break; - case 0x5: - instruction->type = ARM_ADC; - mnemonic = "ADC"; - break; - case 0x6: - instruction->type = ARM_SBC; - mnemonic = "SBC"; - break; - case 0x7: - instruction->type = ARM_RSC; - mnemonic = "RSC"; - break; - case 0x8: - instruction->type = ARM_TST; - mnemonic = "TST"; - break; - case 0x9: - instruction->type = ARM_TEQ; - mnemonic = "TEQ"; - break; - case 0xa: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - break; - case 0xb: - instruction->type = ARM_CMN; - mnemonic = "CMN"; - break; - case 0xc: - instruction->type = ARM_ORR; - mnemonic = "ORR"; - break; - case 0xd: - instruction->type = ARM_MOV; - mnemonic = "MOV"; - break; - case 0xe: - instruction->type = ARM_BIC; - mnemonic = "BIC"; - break; - case 0xf: - instruction->type = ARM_MVN; - mnemonic = "MVN"; - break; + case 0x0: + instruction->type = ARM_AND; + mnemonic = "AND"; + break; + case 0x1: + instruction->type = ARM_EOR; + mnemonic = "EOR"; + break; + case 0x2: + instruction->type = ARM_SUB; + mnemonic = "SUB"; + break; + case 0x3: + instruction->type = ARM_RSB; + mnemonic = "RSB"; + break; + case 0x4: + instruction->type = ARM_ADD; + mnemonic = "ADD"; + break; + case 0x5: + instruction->type = ARM_ADC; + mnemonic = "ADC"; + break; + case 0x6: + instruction->type = ARM_SBC; + mnemonic = "SBC"; + break; + case 0x7: + instruction->type = ARM_RSC; + mnemonic = "RSC"; + break; + case 0x8: + instruction->type = ARM_TST; + mnemonic = "TST"; + break; + case 0x9: + instruction->type = ARM_TEQ; + mnemonic = "TEQ"; + break; + case 0xa: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + break; + case 0xb: + instruction->type = ARM_CMN; + mnemonic = "CMN"; + break; + case 0xc: + instruction->type = ARM_ORR; + mnemonic = "ORR"; + break; + case 0xd: + instruction->type = ARM_MOV; + mnemonic = "MOV"; + break; + case 0xe: + instruction->type = ARM_BIC; + mnemonic = "BIC"; + break; + case 0xf: + instruction->type = ARM_MVN; + mnemonic = "MVN"; + break; } if (i) {/* immediate shifter operand (#)*/ @@ -2065,28 +2065,28 @@ static int evaluate_b_bl_blx_thumb(uint16_t opcode, target_address = address + 4 + (offset << 1); switch (opc) { - /* unconditional branch */ - case 0: - instruction->type = ARM_B; - mnemonic = "B"; - break; - /* BLX suffix */ - case 1: - instruction->type = ARM_BLX; - mnemonic = "BLX"; - target_address &= 0xfffffffc; - break; - /* BL/BLX prefix */ - case 2: - instruction->type = ARM_UNKNOWN_INSTRUCTION; - mnemonic = "prefix"; - target_address = offset << 12; - break; - /* BL suffix */ - case 3: - instruction->type = ARM_BL; - mnemonic = "BL"; - break; + /* unconditional branch */ + case 0: + instruction->type = ARM_B; + mnemonic = "B"; + break; + /* BLX suffix */ + case 1: + instruction->type = ARM_BLX; + mnemonic = "BLX"; + target_address &= 0xfffffffc; + break; + /* BL/BLX prefix */ + case 2: + instruction->type = ARM_UNKNOWN_INSTRUCTION; + mnemonic = "prefix"; + target_address = offset << 12; + break; + /* BL suffix */ + case 3: + instruction->type = ARM_BL; + mnemonic = "BL"; + break; } /* TODO: deal correctly with dual opcode (prefixed) BL/BLX; @@ -2158,21 +2158,21 @@ static int evaluate_shift_imm_thumb(uint16_t opcode, char *mnemonic = NULL; switch (opc) { - case 0: - instruction->type = ARM_MOV; - mnemonic = "LSLS"; - instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0; - break; - case 1: - instruction->type = ARM_MOV; - mnemonic = "LSRS"; - instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1; - break; - case 2: - instruction->type = ARM_MOV; - mnemonic = "ASRS"; - instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2; - break; + case 0: + instruction->type = ARM_MOV; + mnemonic = "LSLS"; + instruction->info.data_proc.shifter_operand.immediate_shift.shift = 0; + break; + case 1: + instruction->type = ARM_MOV; + mnemonic = "LSRS"; + instruction->info.data_proc.shifter_operand.immediate_shift.shift = 1; + break; + case 2: + instruction->type = ARM_MOV; + mnemonic = "ASRS"; + instruction->info.data_proc.shifter_operand.immediate_shift.shift = 2; + break; } if ((imm == 0) && (opc != 0)) @@ -2208,24 +2208,24 @@ static int evaluate_data_proc_imm_thumb(uint16_t opcode, instruction->info.data_proc.shifter_operand.immediate.immediate = imm; switch (opc) { - case 0: - instruction->type = ARM_MOV; - mnemonic = "MOVS"; - instruction->info.data_proc.rn = -1; - break; - case 1: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - instruction->info.data_proc.rd = -1; - break; - case 2: - instruction->type = ARM_ADD; - mnemonic = "ADDS"; - break; - case 3: - instruction->type = ARM_SUB; - mnemonic = "SUBS"; - break; + case 0: + instruction->type = ARM_MOV; + mnemonic = "MOVS"; + instruction->info.data_proc.rn = -1; + break; + case 1: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + instruction->info.data_proc.rd = -1; + break; + case 2: + instruction->type = ARM_ADD; + mnemonic = "ADDS"; + break; + case 3: + instruction->type = ARM_SUB; + mnemonic = "SUBS"; + break; } snprintf(instruction->text, 128, @@ -2262,131 +2262,131 @@ static int evaluate_data_proc_thumb(uint16_t opcode, op >>= 2; switch (op) { - case 0x0: - instruction->type = ARM_ADD; - mnemonic = "ADD"; - break; - case 0x1: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - break; - case 0x2: - instruction->type = ARM_MOV; - mnemonic = "MOV"; - if (rd == rm) - nop = true; - break; - case 0x3: - if ((opcode & 0x7) == 0x0) { - instruction->info.b_bl_bx_blx.reg_operand = rm; - if (h1) { - instruction->type = ARM_BLX; - snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \tBLX\tr%i", - address, opcode, rm); - } else { - instruction->type = ARM_BX; - snprintf(instruction->text, 128, - "0x%8.8" PRIx32 - " 0x%4.4x \tBX\tr%i", - address, opcode, rm); - } - } else { - instruction->type = ARM_UNDEFINED_INSTRUCTION; + case 0x0: + instruction->type = ARM_ADD; + mnemonic = "ADD"; + break; + case 0x1: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + break; + case 0x2: + instruction->type = ARM_MOV; + mnemonic = "MOV"; + if (rd == rm) + nop = true; + break; + case 0x3: + if ((opcode & 0x7) == 0x0) { + instruction->info.b_bl_bx_blx.reg_operand = rm; + if (h1) { + instruction->type = ARM_BLX; snprintf(instruction->text, 128, "0x%8.8" PRIx32 - " 0x%4.4x \t" - "UNDEFINED INSTRUCTION", - address, opcode); + " 0x%4.4x \tBLX\tr%i", + address, opcode, rm); + } else { + instruction->type = ARM_BX; + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 + " 0x%4.4x \tBX\tr%i", + address, opcode, rm); } - return ERROR_OK; + } else { + instruction->type = ARM_UNDEFINED_INSTRUCTION; + snprintf(instruction->text, 128, + "0x%8.8" PRIx32 + " 0x%4.4x \t" + "UNDEFINED INSTRUCTION", + address, opcode); + } + return ERROR_OK; } } else { switch (op) { - case 0x0: - instruction->type = ARM_AND; - mnemonic = "ANDS"; - break; - case 0x1: - instruction->type = ARM_EOR; - mnemonic = "EORS"; - break; - case 0x2: - instruction->type = ARM_MOV; - mnemonic = "LSLS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 0; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x3: - instruction->type = ARM_MOV; - mnemonic = "LSRS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 1; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x4: - instruction->type = ARM_MOV; - mnemonic = "ASRS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 2; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x5: - instruction->type = ARM_ADC; - mnemonic = "ADCS"; - break; - case 0x6: - instruction->type = ARM_SBC; - mnemonic = "SBCS"; - break; - case 0x7: - instruction->type = ARM_MOV; - mnemonic = "RORS"; - instruction->info.data_proc.variant = 2 /*register shift*/; - instruction->info.data_proc.shifter_operand.register_shift.shift = 3; - instruction->info.data_proc.shifter_operand.register_shift.rm = rd; - instruction->info.data_proc.shifter_operand.register_shift.rs = rm; - break; - case 0x8: - instruction->type = ARM_TST; - mnemonic = "TST"; - break; - case 0x9: - instruction->type = ARM_RSB; - mnemonic = "RSBS"; - instruction->info.data_proc.variant = 0 /*immediate*/; - instruction->info.data_proc.shifter_operand.immediate.immediate = 0; - instruction->info.data_proc.rn = rm; - break; - case 0xA: - instruction->type = ARM_CMP; - mnemonic = "CMP"; - break; - case 0xB: - instruction->type = ARM_CMN; - mnemonic = "CMN"; - break; - case 0xC: - instruction->type = ARM_ORR; - mnemonic = "ORRS"; - break; - case 0xD: - instruction->type = ARM_MUL; - mnemonic = "MULS"; - break; - case 0xE: - instruction->type = ARM_BIC; - mnemonic = "BICS"; - break; - case 0xF: - instruction->type = ARM_MVN; - mnemonic = "MVNS"; - break; + case 0x0: + instruction->type = ARM_AND; + mnemonic = "ANDS"; + break; + case 0x1: + instruction->type = ARM_EOR; + mnemonic = "EORS"; + break; + case 0x2: + instruction->type = ARM_MOV; + mnemonic = "LSLS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 0; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x3: + instruction->type = ARM_MOV; + mnemonic = "LSRS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 1; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x4: + instruction->type = ARM_MOV; + mnemonic = "ASRS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 2; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x5: + instruction->type = ARM_ADC; + mnemonic = "ADCS"; + break; + case 0x6: + instruction->type = ARM_SBC; + mnemonic = "SBCS"; + break; + case 0x7: + instruction->type = ARM_MOV; + mnemonic = "RORS"; + instruction->info.data_proc.variant = 2 /*register shift*/; + instruction->info.data_proc.shifter_operand.register_shift.shift = 3; + instruction->info.data_proc.shifter_operand.register_shift.rm = rd; + instruction->info.data_proc.shifter_operand.register_shift.rs = rm; + break; + case 0x8: + instruction->type = ARM_TST; + mnemonic = "TST"; + break; + case 0x9: + instruction->type = ARM_RSB; + mnemonic = "RSBS"; + instruction->info.data_proc.variant = 0 /*immediate*/; + instruction->info.data_proc.shifter_operand.immediate.immediate = 0; + instruction->info.data_proc.rn = rm; + break; + case 0xA: + instruction->type = ARM_CMP; + mnemonic = "CMP"; + break; + case 0xB: + instruction->type = ARM_CMN; + mnemonic = "CMN"; + break; + case 0xC: + instruction->type = ARM_ORR; + mnemonic = "ORRS"; + break; + case 0xD: + instruction->type = ARM_MUL; + mnemonic = "MULS"; + break; + case 0xE: + instruction->type = ARM_BIC; + mnemonic = "BICS"; + break; + case 0xF: + instruction->type = ARM_MVN; + mnemonic = "MVNS"; + break; } } @@ -2444,38 +2444,38 @@ static int evaluate_load_store_reg_thumb(uint16_t opcode, char *mnemonic = NULL; switch (opc) { - case 0: - instruction->type = ARM_STR; - mnemonic = "STR"; - break; - case 1: - instruction->type = ARM_STRH; - mnemonic = "STRH"; - break; - case 2: - instruction->type = ARM_STRB; - mnemonic = "STRB"; - break; - case 3: - instruction->type = ARM_LDRSB; - mnemonic = "LDRSB"; - break; - case 4: - instruction->type = ARM_LDR; - mnemonic = "LDR"; - break; - case 5: - instruction->type = ARM_LDRH; - mnemonic = "LDRH"; - break; - case 6: - instruction->type = ARM_LDRB; - mnemonic = "LDRB"; - break; - case 7: - instruction->type = ARM_LDRSH; - mnemonic = "LDRSH"; - break; + case 0: + instruction->type = ARM_STR; + mnemonic = "STR"; + break; + case 1: + instruction->type = ARM_STRH; + mnemonic = "STRH"; + break; + case 2: + instruction->type = ARM_STRB; + mnemonic = "STRB"; + break; + case 3: + instruction->type = ARM_LDRSB; + mnemonic = "LDRSB"; + break; + case 4: + instruction->type = ARM_LDR; + mnemonic = "LDR"; + break; + case 5: + instruction->type = ARM_LDRH; + mnemonic = "LDRH"; + break; + case 6: + instruction->type = ARM_LDRB; + mnemonic = "LDRB"; + break; + case 7: + instruction->type = ARM_LDRSH; + mnemonic = "LDRSH"; + break; } snprintf(instruction->text, 128, @@ -2804,15 +2804,15 @@ static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address, /* added in ARMv6 */ switch ((opcode >> 6) & 3) { - case 0: - suffix = ""; - break; - case 1: - suffix = "16"; - break; - default: - suffix = "SH"; - break; + case 0: + suffix = ""; + break; + case 1: + suffix = "16"; + break; + default: + suffix = "SH"; + break; } snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \tREV%s\tr%d, r%d", @@ -2828,24 +2828,24 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address, char *hint; switch ((opcode >> 4) & 0x0f) { - case 0: - hint = "NOP"; - break; - case 1: - hint = "YIELD"; - break; - case 2: - hint = "WFE"; - break; - case 3: - hint = "WFI"; - break; - case 4: - hint = "SEV"; - break; - default: - hint = "HINT (UNRECOGNIZED)"; - break; + case 0: + hint = "NOP"; + break; + case 1: + hint = "YIELD"; + break; + case 2: + hint = "WFE"; + break; + case 3: + hint = "WFI"; + break; + case 4: + hint = "SEV"; + break; + default: + hint = "HINT (UNRECOGNIZED)"; + break; } snprintf(instruction->text, 128, @@ -2928,36 +2928,36 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct /* Misc */ if ((opcode & 0xf000) == 0xb000) { switch ((opcode >> 8) & 0x0f) { - case 0x0: - return evaluate_adjust_stack_thumb(opcode, address, instruction); - case 0x1: - case 0x3: - case 0x9: - case 0xb: - return evaluate_cb_thumb(opcode, address, instruction); - case 0x2: - return evaluate_extend_thumb(opcode, address, instruction); - case 0x4: - case 0x5: - case 0xc: - case 0xd: - return evaluate_load_store_multiple_thumb(opcode, address, - instruction); - case 0x6: - return evaluate_cps_thumb(opcode, address, instruction); - case 0xa: - if ((opcode & 0x00c0) == 0x0080) - break; - return evaluate_byterev_thumb(opcode, address, instruction); - case 0xe: - return evaluate_breakpoint_thumb(opcode, address, instruction); - case 0xf: - if (opcode & 0x000f) - return evaluate_ifthen_thumb(opcode, address, - instruction); - else - return evaluate_hint_thumb(opcode, address, - instruction); + case 0x0: + return evaluate_adjust_stack_thumb(opcode, address, instruction); + case 0x1: + case 0x3: + case 0x9: + case 0xb: + return evaluate_cb_thumb(opcode, address, instruction); + case 0x2: + return evaluate_extend_thumb(opcode, address, instruction); + case 0x4: + case 0x5: + case 0xc: + case 0xd: + return evaluate_load_store_multiple_thumb(opcode, address, + instruction); + case 0x6: + return evaluate_cps_thumb(opcode, address, instruction); + case 0xa: + if ((opcode & 0x00c0) == 0x0080) + break; + return evaluate_byterev_thumb(opcode, address, instruction); + case 0xe: + return evaluate_breakpoint_thumb(opcode, address, instruction); + case 0xf: + if (opcode & 0x000f) + return evaluate_ifthen_thumb(opcode, address, + instruction); + else + return evaluate_hint_thumb(opcode, address, + instruction); } instruction->type = ARM_UNDEFINED_INSTRUCTION; diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 8ab464d0a..26e32591a 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -171,24 +171,23 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int reg uint32_t value_r0, value_r1; switch (regnum) { - case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: - /* move from double word register to r0:r1: "vmov r0, r1, vm" - * then read r0 via dcc - */ - retval = dpm->instr_read_data_r0(dpm, - ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4), - ((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0); - if (retval != ERROR_OK) - break; - - /* read r1 via dcc */ - retval = dpm->instr_read_data_dcc(dpm, - ARMV4_5_MCR(14, 0, 1, 0, 5, 0), - &value_r1); + case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: + /* move from double word register to r0:r1: "vmov r0, r1, vm" + * then read r0 via dcc + */ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_VMOV(1, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4), + ((regnum - ARM_VFP_V3_D0) & 0xf)), &value_r0); + if (retval != ERROR_OK) break; - default: - break; + /* read r1 via dcc */ + retval = dpm->instr_read_data_dcc(dpm, + ARMV4_5_MCR(14, 0, 1, 0, 5, 0), + &value_r1); + break; + default: + break; } if (retval == ERROR_OK) { @@ -210,54 +209,54 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum) int retval; switch (regnum) { - case 0 ... 14: - /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ - retval = dpm->instr_read_data_dcc(dpm, - ARMV4_5_MCR(14, 0, regnum, 0, 5, 0), - &value); - break; - case 15:/* PC - * "MOV r0, pc"; then return via DCC */ - retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value); + case 0 ... 14: + /* return via DCC: "MCR p14, 0, Rnum, c0, c5, 0" */ + retval = dpm->instr_read_data_dcc(dpm, + ARMV4_5_MCR(14, 0, regnum, 0, 5, 0), + &value); + break; + case 15:/* PC + * "MOV r0, pc"; then return via DCC */ + retval = dpm->instr_read_data_r0(dpm, 0xe1a0000f, &value); - /* NOTE: this seems like a slightly awkward place to update - * this value ... but if the PC gets written (the only way - * to change what we compute), the arch spec says subsequent - * reads return values which are "unpredictable". So this - * is always right except in those broken-by-intent cases. - */ - switch (dpm->arm->core_state) { - case ARM_STATE_ARM: - value -= 8; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - value -= 4; - break; - case ARM_STATE_JAZELLE: - /* core-specific ... ? */ - LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown"); - break; - default: - LOG_TARGET_WARNING(dpm->arm->target, "unknown core state"); - break; - } + /* NOTE: this seems like a slightly awkward place to update + * this value ... but if the PC gets written (the only way + * to change what we compute), the arch spec says subsequent + * reads return values which are "unpredictable". So this + * is always right except in those broken-by-intent cases. + */ + switch (dpm->arm->core_state) { + case ARM_STATE_ARM: + value -= 8; break; - case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: - return dpm_read_reg_u64(dpm, r, regnum); - case ARM_VFP_V3_FPSCR: - /* "VMRS r0, FPSCR"; then return via DCC */ - retval = dpm->instr_read_data_r0(dpm, - ARMV4_5_VMRS(0), &value); + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + value -= 4; + break; + case ARM_STATE_JAZELLE: + /* core-specific ... ? */ + LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown"); break; default: - /* 16: "MRS r0, CPSR"; then return via DCC - * 17: "MRS r0, SPSR"; then return via DCC - */ - retval = dpm->instr_read_data_r0(dpm, - ARMV4_5_MRS(0, regnum & 1), - &value); + LOG_TARGET_WARNING(dpm->arm->target, "unknown core state"); break; + } + break; + case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: + return dpm_read_reg_u64(dpm, r, regnum); + case ARM_VFP_V3_FPSCR: + /* "VMRS r0, FPSCR"; then return via DCC */ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_VMRS(0), &value); + break; + default: + /* 16: "MRS r0, CPSR"; then return via DCC + * 17: "MRS r0, SPSR"; then return via DCC + */ + retval = dpm->instr_read_data_r0(dpm, + ARMV4_5_MRS(0, regnum & 1), + &value); + break; } if (retval == ERROR_OK) { @@ -279,24 +278,23 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int re uint32_t value_r1 = buf_get_u32(r->value + 4, 0, 32); switch (regnum) { - case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: - /* write value_r1 to r1 via dcc */ - retval = dpm->instr_write_data_dcc(dpm, - ARMV4_5_MRC(14, 0, 1, 0, 5, 0), - value_r1); - if (retval != ERROR_OK) - break; - - /* write value_r0 to r0 via dcc then, - * move to double word register from r0:r1: "vmov vm, r0, r1" - */ - retval = dpm->instr_write_data_r0(dpm, - ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4), - ((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0); + case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: + /* write value_r1 to r1 via dcc */ + retval = dpm->instr_write_data_dcc(dpm, + ARMV4_5_MRC(14, 0, 1, 0, 5, 0), + value_r1); + if (retval != ERROR_OK) break; - default: - break; + /* write value_r0 to r0 via dcc then, + * move to double word register from r0:r1: "vmov vm, r0, r1" + */ + retval = dpm->instr_write_data_r0(dpm, + ARMV4_5_VMOV(0, 1, 0, ((regnum - ARM_VFP_V3_D0) >> 4), + ((regnum - ARM_VFP_V3_D0) & 0xf)), value_r0); + break; + default: + break; } if (retval == ERROR_OK) { @@ -315,37 +313,37 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum uint32_t value = buf_get_u32(r->value, 0, 32); switch (regnum) { - case 0 ... 14: - /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */ - retval = dpm->instr_write_data_dcc(dpm, - ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), - value); - break; - case 15:/* PC - * read r0 from DCC; then "MOV pc, r0" */ - retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value); - break; - case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: - return dpm_write_reg_u64(dpm, r, regnum); - case ARM_VFP_V3_FPSCR: - /* move to r0 from DCC, then "VMSR FPSCR, r0" */ - retval = dpm->instr_write_data_r0(dpm, - ARMV4_5_VMSR(0), value); - break; - default: - /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf" - * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf" - */ - retval = dpm->instr_write_data_r0(dpm, - ARMV4_5_MSR_GP(0, 0xf, regnum & 1), - value); - if (retval != ERROR_OK) - return retval; + case 0 ... 14: + /* load register from DCC: "MRC p14, 0, Rnum, c0, c5, 0" */ + retval = dpm->instr_write_data_dcc(dpm, + ARMV4_5_MRC(14, 0, regnum, 0, 5, 0), + value); + break; + case 15:/* PC + * read r0 from DCC; then "MOV pc, r0" */ + retval = dpm->instr_write_data_r0(dpm, 0xe1a0f000, value); + break; + case ARM_VFP_V3_D0 ... ARM_VFP_V3_D31: + return dpm_write_reg_u64(dpm, r, regnum); + case ARM_VFP_V3_FPSCR: + /* move to r0 from DCC, then "VMSR FPSCR, r0" */ + retval = dpm->instr_write_data_r0(dpm, + ARMV4_5_VMSR(0), value); + break; + default: + /* 16: read r0 from DCC, then "MSR r0, CPSR_cxsf" + * 17: read r0 from DCC, then "MSR r0, SPSR_cxsf" + */ + retval = dpm->instr_write_data_r0(dpm, + ARMV4_5_MSR_GP(0, 0xf, regnum & 1), + value); + if (retval != ERROR_OK) + return retval; - if (regnum == 16 && dpm->instr_cpsr_sync) - retval = dpm->instr_cpsr_sync(dpm); + if (regnum == 16 && dpm->instr_cpsr_sync) + retval = dpm->instr_cpsr_sync(dpm); - break; + break; } if (retval == ERROR_OK) { @@ -655,24 +653,24 @@ static enum arm_mode dpm_mapmode(struct arm *arm, return ARM_MODE_ANY; switch (num) { - /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */ - case 0 ... 7: - case 15: - case 16: - break; - /* r8..r12 aren't shadowed for anything except FIQ */ - case 8 ... 12: - if (mode == ARM_MODE_FIQ) - return mode; - break; - /* r13/sp, and r14/lr are always shadowed */ - case 13: - case 14: - case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR: + /* don't switch for non-shadowed registers (r0..r7, r15/pc, cpsr) */ + case 0 ... 7: + case 15: + case 16: + break; + /* r8..r12 aren't shadowed for anything except FIQ */ + case 8 ... 12: + if (mode == ARM_MODE_FIQ) return mode; - default: - LOG_TARGET_WARNING(arm->target, "invalid register #%u", num); - break; + break; + /* r13/sp, and r14/lr are always shadowed */ + case 13: + case 14: + case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR: + return mode; + default: + LOG_TARGET_WARNING(arm->target, "invalid register #%u", num); + break; } return ARM_MODE_ANY; } @@ -868,26 +866,26 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, * v7 hardware, unaligned 4-byte ones too. */ switch (length) { - case 1: - control |= (1 << (addr & 3)) << 5; + case 1: + control |= (1 << (addr & 3)) << 5; + break; + case 2: + /* require 2-byte alignment */ + if (!(addr & 1)) { + control |= (3 << (addr & 2)) << 5; break; - case 2: - /* require 2-byte alignment */ - if (!(addr & 1)) { - control |= (3 << (addr & 2)) << 5; - break; - } - /* FALL THROUGH */ - case 4: - /* require 4-byte alignment */ - if (!(addr & 3)) { - control |= 0xf << 5; - break; - } - /* FALL THROUGH */ - default: - LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment"); - return ERROR_COMMAND_SYNTAX_ERROR; + } + /* FALL THROUGH */ + case 4: + /* require 4-byte alignment */ + if (!(addr & 3)) { + control |= 0xf << 5; + break; + } + /* FALL THROUGH */ + default: + LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment"); + return ERROR_COMMAND_SYNTAX_ERROR; } /* other shared control bits: @@ -974,15 +972,15 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t, control = dwp->bpwp.control; switch (wp->rw) { - case WPT_READ: - control |= 1 << 3; - break; - case WPT_WRITE: - control |= 2 << 3; - break; - case WPT_ACCESS: - control |= 3 << 3; - break; + case WPT_READ: + control |= 1 << 3; + break; + case WPT_WRITE: + control |= 2 << 3; + break; + case WPT_ACCESS: + control |= 3 << 3; + break; } dwp->bpwp.control = control; @@ -1032,17 +1030,17 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp) void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) { switch (dpm->arm->core_state) { - case ARM_STATE_ARM: - addr -= 8; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - addr -= 4; - break; - case ARM_STATE_JAZELLE: - case ARM_STATE_AARCH64: - /* ?? */ - break; + case ARM_STATE_ARM: + addr -= 8; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + addr -= 4; + break; + case ARM_STATE_JAZELLE: + case ARM_STATE_AARCH64: + /* ?? */ + break; } dpm->wp_addr = addr; } @@ -1061,21 +1059,21 @@ void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) /* Examine debug reason */ switch (DSCR_ENTRY(dscr)) { - case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */ - case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */ - target->debug_reason = DBG_REASON_DBGRQ; - break; - case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */ - case DSCR_ENTRY_BKPT_INSTR: /* vector catch */ - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */ - case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */ - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - default: - target->debug_reason = DBG_REASON_UNDEFINED; - break; + case DSCR_ENTRY_HALT_REQ: /* HALT request from debugger */ + case DSCR_ENTRY_EXT_DBG_REQ: /* EDBGRQ */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case DSCR_ENTRY_BREAKPOINT: /* HW breakpoint */ + case DSCR_ENTRY_BKPT_INSTR: /* vector catch */ + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case DSCR_ENTRY_IMPRECISE_WATCHPT: /* asynch watchpoint */ + case DSCR_ENTRY_PRECISE_WATCHPT:/* precise watchpoint */ + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + default: + target->debug_reason = DBG_REASON_UNDEFINED; + break; } } diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c index 058e3d38b..e9f667116 100644 --- a/src/target/arm_simulator.c +++ b/src/target/arm_simulator.c @@ -130,86 +130,85 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim, static int pass_condition(uint32_t cpsr, uint32_t opcode) { switch ((opcode & 0xf0000000) >> 28) { - case 0x0: /* EQ */ - if (cpsr & 0x40000000) - return 1; - else - return 0; - case 0x1: /* NE */ - if (!(cpsr & 0x40000000)) - return 1; - else - return 0; - case 0x2: /* CS */ - if (cpsr & 0x20000000) - return 1; - else - return 0; - case 0x3: /* CC */ - if (!(cpsr & 0x20000000)) - return 1; - else - return 0; - case 0x4: /* MI */ - if (cpsr & 0x80000000) - return 1; - else - return 0; - case 0x5: /* PL */ - if (!(cpsr & 0x80000000)) - return 1; - else - return 0; - case 0x6: /* VS */ - if (cpsr & 0x10000000) - return 1; - else - return 0; - case 0x7: /* VC */ - if (!(cpsr & 0x10000000)) - return 1; - else - return 0; - case 0x8: /* HI */ - if ((cpsr & 0x20000000) && !(cpsr & 0x40000000)) - return 1; - else - return 0; - case 0x9: /* LS */ - if (!(cpsr & 0x20000000) || (cpsr & 0x40000000)) - return 1; - else - return 0; - case 0xa: /* GE */ - if (((cpsr & 0x80000000) && (cpsr & 0x10000000)) - || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))) - return 1; - else - return 0; - case 0xb: /* LT */ - if (((cpsr & 0x80000000) && !(cpsr & 0x10000000)) - || (!(cpsr & 0x80000000) && (cpsr & 0x10000000))) - return 1; - else - return 0; - case 0xc: /* GT */ - if (!(cpsr & 0x40000000) && - (((cpsr & 0x80000000) && (cpsr & 0x10000000)) - || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))) - return 1; - else - return 0; - case 0xd: /* LE */ - if ((cpsr & 0x40000000) || - ((cpsr & 0x80000000) && !(cpsr & 0x10000000)) - || (!(cpsr & 0x80000000) && (cpsr & 0x10000000))) - return 1; - else - return 0; - case 0xe: - case 0xf: + case 0x0: /* EQ */ + if (cpsr & 0x40000000) return 1; - + else + return 0; + case 0x1: /* NE */ + if (!(cpsr & 0x40000000)) + return 1; + else + return 0; + case 0x2: /* CS */ + if (cpsr & 0x20000000) + return 1; + else + return 0; + case 0x3: /* CC */ + if (!(cpsr & 0x20000000)) + return 1; + else + return 0; + case 0x4: /* MI */ + if (cpsr & 0x80000000) + return 1; + else + return 0; + case 0x5: /* PL */ + if (!(cpsr & 0x80000000)) + return 1; + else + return 0; + case 0x6: /* VS */ + if (cpsr & 0x10000000) + return 1; + else + return 0; + case 0x7: /* VC */ + if (!(cpsr & 0x10000000)) + return 1; + else + return 0; + case 0x8: /* HI */ + if ((cpsr & 0x20000000) && !(cpsr & 0x40000000)) + return 1; + else + return 0; + case 0x9: /* LS */ + if (!(cpsr & 0x20000000) || (cpsr & 0x40000000)) + return 1; + else + return 0; + case 0xa: /* GE */ + if (((cpsr & 0x80000000) && (cpsr & 0x10000000)) + || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000))) + return 1; + else + return 0; + case 0xb: /* LT */ + if (((cpsr & 0x80000000) && !(cpsr & 0x10000000)) + || (!(cpsr & 0x80000000) && (cpsr & 0x10000000))) + return 1; + else + return 0; + case 0xc: /* GT */ + if (!(cpsr & 0x40000000) && + (((cpsr & 0x80000000) && (cpsr & 0x10000000)) + || (!(cpsr & 0x80000000) && !(cpsr & 0x10000000)))) + return 1; + else + return 0; + case 0xd: /* LE */ + if ((cpsr & 0x40000000) || + ((cpsr & 0x80000000) && !(cpsr & 0x10000000)) + || (!(cpsr & 0x80000000) && (cpsr & 0x10000000))) + return 1; + else + return 0; + case 0xe: + case 0xf: + return 1; } LOG_ERROR("BUG: should never get here"); @@ -510,18 +509,18 @@ static int arm_simulate_step_core(struct target *target, } switch (instruction.info.load_store_multiple.addressing_mode) { - case 0: /* Increment after */ - /* rn = rn; */ - break; - case 1: /* Increment before */ - rn = rn + 4; - break; - case 2: /* Decrement after */ - rn = rn - (bits_set * 4) + 4; - break; - case 3: /* Decrement before */ - rn = rn - (bits_set * 4); - break; + case 0: /* Increment after */ + /* rn = rn; */ + break; + case 1: /* Increment before */ + rn = rn + 4; + break; + case 2: /* Decrement after */ + rn = rn - (bits_set * 4) + 4; + break; + case 3: /* Decrement before */ + rn = rn - (bits_set * 4); + break; } for (i = 0; i < 16; i++) { @@ -590,18 +589,18 @@ static int arm_simulate_step_core(struct target *target, } switch (instruction.info.load_store_multiple.addressing_mode) { - case 0: /* Increment after */ - /* rn = rn; */ - break; - case 1: /* Increment before */ - rn = rn + 4; - break; - case 2: /* Decrement after */ - rn = rn - (bits_set * 4) + 4; - break; - case 3: /* Decrement before */ - rn = rn - (bits_set * 4); - break; + case 0: /* Increment after */ + /* rn = rn; */ + break; + case 1: /* Increment before */ + rn = rn + 4; + break; + case 2: /* Decrement after */ + rn = rn - (bits_set * 4) + 4; + break; + case 3: /* Decrement before */ + rn = rn - (bits_set * 4); + break; } for (i = 0; i < 16; i++) { diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index c4d36f40e..8e03184d3 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -192,30 +192,30 @@ bool is_arm_mode(unsigned int psr_mode) int arm_mode_to_number(enum arm_mode mode) { switch (mode) { - case ARM_MODE_ANY: - /* map MODE_ANY to user mode */ - case ARM_MODE_USR: - return 0; - case ARM_MODE_FIQ: - return 1; - case ARM_MODE_IRQ: - return 2; - case ARM_MODE_SVC: - return 3; - case ARM_MODE_ABT: - return 4; - case ARM_MODE_UND: - return 5; - case ARM_MODE_SYS: - return 6; - case ARM_MODE_MON: - case ARM_MODE_1176_MON: - return 7; - case ARM_MODE_HYP: - return 8; - default: - LOG_ERROR("invalid mode value encountered %d", mode); - return -1; + case ARM_MODE_ANY: + /* map MODE_ANY to user mode */ + case ARM_MODE_USR: + return 0; + case ARM_MODE_FIQ: + return 1; + case ARM_MODE_IRQ: + return 2; + case ARM_MODE_SVC: + return 3; + case ARM_MODE_ABT: + return 4; + case ARM_MODE_UND: + return 5; + case ARM_MODE_SYS: + return 6; + case ARM_MODE_MON: + case ARM_MODE_1176_MON: + return 7; + case ARM_MODE_HYP: + return 8; + default: + LOG_ERROR("invalid mode value encountered %d", mode); + return -1; } } @@ -223,27 +223,27 @@ int arm_mode_to_number(enum arm_mode mode) enum arm_mode armv4_5_number_to_mode(int number) { switch (number) { - case 0: - return ARM_MODE_USR; - case 1: - return ARM_MODE_FIQ; - case 2: - return ARM_MODE_IRQ; - case 3: - return ARM_MODE_SVC; - case 4: - return ARM_MODE_ABT; - case 5: - return ARM_MODE_UND; - case 6: - return ARM_MODE_SYS; - case 7: - return ARM_MODE_MON; - case 8: - return ARM_MODE_HYP; - default: - LOG_ERROR("mode index out of bounds %d", number); - return ARM_MODE_ANY; + case 0: + return ARM_MODE_USR; + case 1: + return ARM_MODE_FIQ; + case 2: + return ARM_MODE_IRQ; + case 3: + return ARM_MODE_SVC; + case 4: + return ARM_MODE_ABT; + case 5: + return ARM_MODE_UND; + case 6: + return ARM_MODE_SYS; + case 7: + return ARM_MODE_MON; + case 8: + return ARM_MODE_HYP; + default: + LOG_ERROR("mode index out of bounds %d", number); + return ARM_MODE_ANY; } } @@ -864,26 +864,26 @@ COMMAND_HANDLER(handle_armv4_5_reg_command) /* label this bank of registers (or shadows) */ switch (arm_mode_data[mode].psr) { - case ARM_MODE_SYS: + case ARM_MODE_SYS: + continue; + case ARM_MODE_USR: + name = "System and User"; + sep = ""; + break; + case ARM_MODE_HYP: + if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT) continue; - case ARM_MODE_USR: - name = "System and User"; - sep = ""; - break; - case ARM_MODE_HYP: - if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT) - continue; - /* FALLTHROUGH */ - case ARM_MODE_MON: - case ARM_MODE_1176_MON: - if (arm->core_type != ARM_CORE_TYPE_SEC_EXT - && arm->core_type != ARM_CORE_TYPE_VIRT_EXT) - continue; - /* FALLTHROUGH */ - default: - name = arm_mode_data[mode].name; - shadow = "shadow "; - break; + /* FALLTHROUGH */ + case ARM_MODE_MON: + case ARM_MODE_1176_MON: + if (arm->core_type != ARM_CORE_TYPE_SEC_EXT + && arm->core_type != ARM_CORE_TYPE_VIRT_EXT) + continue; + /* FALLTHROUGH */ + default: + name = arm_mode_data[mode].name; + shadow = "shadow "; + break; } command_print(CMD, "%s%s mode %sregisters", sep, name, shadow); @@ -974,26 +974,26 @@ COMMAND_HANDLER(handle_arm_disassemble_command) } switch (CMD_ARGC) { - case 3: - if (strcmp(CMD_ARGV[2], "thumb") != 0) - return ERROR_COMMAND_SYNTAX_ERROR; - thumb = true; - /* FALL THROUGH */ - case 2: - COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count); - /* FALL THROUGH */ - case 1: - COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); - if (address & 0x01) { - if (!thumb) { - command_print(CMD, "Disassemble as Thumb"); - thumb = true; - } - address &= ~1; - } - break; - default: + case 3: + if (strcmp(CMD_ARGV[2], "thumb") != 0) return ERROR_COMMAND_SYNTAX_ERROR; + thumb = true; + /* FALL THROUGH */ + case 2: + COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count); + /* FALL THROUGH */ + case 1: + COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address); + if (address & 0x01) { + if (!thumb) { + command_print(CMD, "Disassemble as Thumb"); + thumb = true; + } + address &= ~1; + } + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return arm_disassemble(CMD, target, address, count, thumb); @@ -1314,14 +1314,14 @@ int arm_get_gdb_reg_list(struct target *target, case REG_CLASS_ALL: switch (arm->core_type) { - case ARM_CORE_TYPE_SEC_EXT: - *reg_list_size = 51; - break; - case ARM_CORE_TYPE_VIRT_EXT: - *reg_list_size = 53; - break; - default: - *reg_list_size = 48; + case ARM_CORE_TYPE_SEC_EXT: + *reg_list_size = 51; + break; + case ARM_CORE_TYPE_VIRT_EXT: + *reg_list_size = 53; + break; + default: + *reg_list_size = 48; } unsigned int list_size_core = *reg_list_size; if (arm->arm_vfp_version == ARM_VFP_V3) diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c index ee1592ae8..371e64658 100644 --- a/src/target/armv7a_mmu.c +++ b/src/target/armv7a_mmu.c @@ -73,40 +73,40 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va, NS == 1 ? "not" : "", SS == 0 ? "not" : ""); switch (OUTER) { - case 0: - LOG_INFO("outer: Non-Cacheable"); - break; - case 1: - LOG_INFO("outer: Write-Back, Write-Allocate"); - break; - case 2: - LOG_INFO("outer: Write-Through, No Write-Allocate"); - break; - case 3: - LOG_INFO("outer: Write-Back, no Write-Allocate"); - break; + case 0: + LOG_INFO("outer: Non-Cacheable"); + break; + case 1: + LOG_INFO("outer: Write-Back, Write-Allocate"); + break; + case 2: + LOG_INFO("outer: Write-Through, No Write-Allocate"); + break; + case 3: + LOG_INFO("outer: Write-Back, no Write-Allocate"); + break; } switch (INNER) { - case 0: - LOG_INFO("inner: Non-Cacheable"); - break; - case 1: - LOG_INFO("inner: Strongly-ordered"); - break; - case 3: - LOG_INFO("inner: Device"); - break; - case 5: - LOG_INFO("inner: Write-Back, Write-Allocate"); - break; - case 6: - LOG_INFO("inner: Write-Through"); - break; - case 7: - LOG_INFO("inner: Write-Back, no Write-Allocate"); - break; - default: - LOG_INFO("inner: %" PRIx32 " ???", INNER); + case 0: + LOG_INFO("inner: Non-Cacheable"); + break; + case 1: + LOG_INFO("inner: Strongly-ordered"); + break; + case 3: + LOG_INFO("inner: Device"); + break; + case 5: + LOG_INFO("inner: Write-Back, Write-Allocate"); + break; + case 6: + LOG_INFO("inner: Write-Through"); + break; + case 7: + LOG_INFO("inner: Write-Back, no Write-Allocate"); + break; + default: + LOG_INFO("inner: %" PRIx32 " ???", INNER); } } diff --git a/src/target/armv8.c b/src/target/armv8.c index 51337a5d8..47a380c9d 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -120,27 +120,27 @@ static uint8_t armv8_pa_size(uint32_t ps) { uint8_t ret = 0; switch (ps) { - case 0: - ret = 32; - break; - case 1: - ret = 36; - break; - case 2: - ret = 40; - break; - case 3: - ret = 42; - break; - case 4: - ret = 44; - break; - case 5: - ret = 48; - break; - default: - LOG_INFO("Unknown physical address size"); - break; + case 0: + ret = 32; + break; + case 1: + ret = 36; + break; + case 2: + ret = 40; + break; + case 3: + ret = 42; + break; + case 4: + ret = 44; + break; + case 5: + ret = 48; + break; + default: + LOG_INFO("Unknown physical address size"); + break; } return ret; } @@ -1070,18 +1070,18 @@ static void armv8_decode_cacheability(int attr) return; } switch (attr & 0xC) { - case 0: - LOG_USER_N("Write-Through Transient"); - break; - case 0x4: - LOG_USER_N("Write-Back Transient"); - break; - case 0x8: - LOG_USER_N("Write-Through Non-transient"); - break; - case 0xC: - LOG_USER_N("Write-Back Non-transient"); - break; + case 0: + LOG_USER_N("Write-Through Transient"); + break; + case 0x4: + LOG_USER_N("Write-Back Transient"); + break; + case 0x8: + LOG_USER_N("Write-Through Non-transient"); + break; + case 0xC: + LOG_USER_N("Write-Back Non-transient"); + break; } if (attr & 2) LOG_USER_N(" Read-Allocate"); @@ -1108,18 +1108,18 @@ static void armv8_decode_memory_attr(int attr) "Non-transient"); } else if ((attr & 0xF0) == 0) { switch (attr & 0xC) { - case 0: - LOG_USER_N("Device-nGnRnE Memory"); - break; - case 0x4: - LOG_USER_N("Device-nGnRE Memory"); - break; - case 0x8: - LOG_USER_N("Device-nGRE Memory"); - break; - case 0xC: - LOG_USER_N("Device-GRE Memory"); - break; + case 0: + LOG_USER_N("Device-nGnRnE Memory"); + break; + case 0x4: + LOG_USER_N("Device-nGnRE Memory"); + break; + case 0x8: + LOG_USER_N("Device-nGRE Memory"); + break; + case 0xC: + LOG_USER_N("Device-GRE Memory"); + break; } if (attr & 1) LOG_USER(", XS=0"); diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index 3384e82ea..508ec973e 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -426,17 +426,17 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, int retval; switch (index_t) { - case 0 ... 15: /* breakpoints */ - vr += CPUV8_DBG_BVR_BASE; - cr += CPUV8_DBG_BCR_BASE; - break; - case 16 ... 31: /* watchpoints */ - vr += CPUV8_DBG_WVR_BASE; - cr += CPUV8_DBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: /* breakpoints */ + vr += CPUV8_DBG_BVR_BASE; + cr += CPUV8_DBG_BCR_BASE; + break; + case 16 ... 31: /* watchpoints */ + vr += CPUV8_DBG_WVR_BASE; + cr += CPUV8_DBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } vr += 16 * index_t; cr += 16 * index_t; @@ -456,15 +456,15 @@ static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) uint32_t cr; switch (index_t) { - case 0 ... 15: - cr = armv8->debug_base + CPUV8_DBG_BCR_BASE; - break; - case 16 ... 31: - cr = armv8->debug_base + CPUV8_DBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + cr = armv8->debug_base + CPUV8_DBG_BCR_BASE; + break; + case 16 ... 31: + cr = armv8->debug_base + CPUV8_DBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } cr += 16 * index_t; @@ -1127,26 +1127,26 @@ static int dpmv8_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp, * v7 hardware, unaligned 4-byte ones too. */ switch (length) { - case 1: - control |= (1 << (addr & 3)) << 5; + case 1: + control |= (1 << (addr & 3)) << 5; + break; + case 2: + /* require 2-byte alignment */ + if (!(addr & 1)) { + control |= (3 << (addr & 2)) << 5; break; - case 2: - /* require 2-byte alignment */ - if (!(addr & 1)) { - control |= (3 << (addr & 2)) << 5; - break; - } - /* FALL THROUGH */ - case 4: - /* require 4-byte alignment */ - if (!(addr & 3)) { - control |= 0xf << 5; - break; - } - /* FALL THROUGH */ - default: - LOG_ERROR("unsupported {break,watch}point length/alignment"); - return ERROR_COMMAND_SYNTAX_ERROR; + } + /* FALL THROUGH */ + case 4: + /* require 4-byte alignment */ + if (!(addr & 3)) { + control |= 0xf << 5; + break; + } + /* FALL THROUGH */ + default: + LOG_ERROR("unsupported {break,watch}point length/alignment"); + return ERROR_COMMAND_SYNTAX_ERROR; } /* other shared control bits: @@ -1233,15 +1233,15 @@ static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t, control = dwp->bpwp.control; switch (wp->rw) { - case WPT_READ: - control |= 1 << 3; - break; - case WPT_WRITE: - control |= 2 << 3; - break; - case WPT_ACCESS: - control |= 3 << 3; - break; + case WPT_READ: + control |= 1 << 3; + break; + case WPT_WRITE: + control |= 2 << 3; + break; + case WPT_ACCESS: + control |= 3 << 3; + break; } dwp->bpwp.control = control; @@ -1363,31 +1363,31 @@ void armv8_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr) /* Examine debug reason */ switch (DSCR_ENTRY(dscr)) { - /* FALL THROUGH -- assume a v6 core in abort mode */ - case DSCRV8_ENTRY_EXT_DEBUG: /* EDBGRQ */ - target->debug_reason = DBG_REASON_DBGRQ; - break; - case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */ - case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/ - case DSCRV8_ENTRY_HALT_STEP: - target->debug_reason = DBG_REASON_SINGLESTEP; - break; - case DSCRV8_ENTRY_HLT: /* HLT instruction (software breakpoint) */ - case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */ - case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */ - case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/ - case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/ - target->debug_reason = DBG_REASON_BREAKPOINT; - break; - case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */ - target->debug_reason = DBG_REASON_WATCHPOINT; - break; - case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ - target->debug_reason = DBG_REASON_EXC_CATCH; - break; - default: - target->debug_reason = DBG_REASON_UNDEFINED; - break; + /* FALL THROUGH -- assume a v6 core in abort mode */ + case DSCRV8_ENTRY_EXT_DEBUG: /* EDBGRQ */ + target->debug_reason = DBG_REASON_DBGRQ; + break; + case DSCRV8_ENTRY_HALT_STEP_EXECLU: /* HALT step */ + case DSCRV8_ENTRY_HALT_STEP_NORMAL: /* Halt step*/ + case DSCRV8_ENTRY_HALT_STEP: + target->debug_reason = DBG_REASON_SINGLESTEP; + break; + case DSCRV8_ENTRY_HLT: /* HLT instruction (software breakpoint) */ + case DSCRV8_ENTRY_BKPT: /* SW BKPT (?) */ + case DSCRV8_ENTRY_RESET_CATCH: /* Reset catch */ + case DSCRV8_ENTRY_OS_UNLOCK: /*OS unlock catch*/ + case DSCRV8_ENTRY_SW_ACCESS_DBG: /*SW access dbg register*/ + target->debug_reason = DBG_REASON_BREAKPOINT; + break; + case DSCRV8_ENTRY_WATCHPOINT: /* asynch watchpoint */ + target->debug_reason = DBG_REASON_WATCHPOINT; + break; + case DSCRV8_ENTRY_EXCEPTION_CATCH: /*exception catch*/ + target->debug_reason = DBG_REASON_EXC_CATCH; + break; + default: + target->debug_reason = DBG_REASON_UNDEFINED; + break; } } diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c index c623df23d..a2da146c9 100644 --- a/src/target/avr32_ap7k.c +++ b/src/target/avr32_ap7k.c @@ -443,18 +443,18 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address, return ERROR_TARGET_UNALIGNED_ACCESS; switch (size) { - case 4: - return avr32_jtag_read_memory32(&ap7k->jtag, address, count, - (uint32_t *)(void *)buffer); - break; - case 2: - return avr32_jtag_read_memory16(&ap7k->jtag, address, count, - (uint16_t *)(void *)buffer); - break; - case 1: - return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer); - default: - break; + case 4: + return avr32_jtag_read_memory32(&ap7k->jtag, address, count, + (uint32_t *)(void *)buffer); + break; + case 2: + return avr32_jtag_read_memory16(&ap7k->jtag, address, count, + (uint16_t *)(void *)buffer); + break; + case 1: + return avr32_jtag_read_memory8(&ap7k->jtag, address, count, buffer); + default: + break; } return ERROR_OK; @@ -483,18 +483,18 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address, return ERROR_TARGET_UNALIGNED_ACCESS; switch (size) { - case 4: - return avr32_jtag_write_memory32(&ap7k->jtag, address, count, - (uint32_t *)(void *)buffer); - break; - case 2: - return avr32_jtag_write_memory16(&ap7k->jtag, address, count, - (uint16_t *)(void *)buffer); - break; - case 1: - return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer); - default: - break; + case 4: + return avr32_jtag_write_memory32(&ap7k->jtag, address, count, + (uint32_t *)(void *)buffer); + break; + case 2: + return avr32_jtag_write_memory16(&ap7k->jtag, address, count, + (uint16_t *)(void *)buffer); + break; + case 1: + return avr32_jtag_write_memory8(&ap7k->jtag, address, count, buffer); + default: + break; } return ERROR_OK; diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c index a08041629..54a6145ca 100644 --- a/src/target/breakpoints.c +++ b/src/target/breakpoints.c @@ -72,22 +72,22 @@ static int breakpoint_add_internal(struct target *target, retval = target_add_breakpoint(target, *breakpoint_p); switch (retval) { - case ERROR_OK: - break; - case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: - reason = "resource not available"; - goto fail; - case ERROR_TARGET_NOT_HALTED: - reason = "target running"; - goto fail; - default: - reason = "unknown reason"; + case ERROR_OK: + break; + case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: + reason = "resource not available"; + goto fail; + case ERROR_TARGET_NOT_HALTED: + reason = "target running"; + goto fail; + default: + reason = "unknown reason"; fail: - LOG_TARGET_ERROR(target, "can't add breakpoint: %s", reason); - free((*breakpoint_p)->orig_instr); - free(*breakpoint_p); - *breakpoint_p = NULL; - return retval; + LOG_TARGET_ERROR(target, "can't add breakpoint: %s", reason); + free((*breakpoint_p)->orig_instr); + free(*breakpoint_p); + *breakpoint_p = NULL; + return retval; } LOG_TARGET_DEBUG(target, "added %s breakpoint at " TARGET_ADDR_FMT @@ -536,23 +536,23 @@ static int watchpoint_add_internal(struct target *target, target_addr_t address, retval = target_add_watchpoint(target, *watchpoint_p); switch (retval) { - case ERROR_OK: - break; - case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: - reason = "resource not available"; - goto bye; - case ERROR_TARGET_NOT_HALTED: - reason = "target running"; - goto bye; - default: - reason = "unrecognized error"; + case ERROR_OK: + break; + case ERROR_TARGET_RESOURCE_NOT_AVAILABLE: + reason = "resource not available"; + goto bye; + case ERROR_TARGET_NOT_HALTED: + reason = "target running"; + goto bye; + default: + reason = "unrecognized error"; bye: - LOG_TARGET_ERROR(target, "can't add %s watchpoint at " TARGET_ADDR_FMT ", %s", - watchpoint_rw_strings[(*watchpoint_p)->rw], - address, reason); - free(*watchpoint_p); - *watchpoint_p = NULL; - return retval; + LOG_TARGET_ERROR(target, "can't add %s watchpoint at " TARGET_ADDR_FMT ", %s", + watchpoint_rw_strings[(*watchpoint_p)->rw], + address, reason); + free(*watchpoint_p); + *watchpoint_p = NULL; + return retval; } LOG_TARGET_DEBUG(target, "added %s watchpoint at " TARGET_ADDR_FMT diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 60527c7da..bc7550509 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -580,17 +580,17 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t, int retval; switch (index_t) { - case 0 ... 15: /* breakpoints */ - vr += CPUDBG_BVR_BASE; - cr += CPUDBG_BCR_BASE; - break; - case 16 ... 31: /* watchpoints */ - vr += CPUDBG_WVR_BASE; - cr += CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: /* breakpoints */ + vr += CPUDBG_BVR_BASE; + cr += CPUDBG_BCR_BASE; + break; + case 16 ... 31: /* watchpoints */ + vr += CPUDBG_WVR_BASE; + cr += CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } vr += 4 * index_t; cr += 4 * index_t; @@ -612,15 +612,15 @@ static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t) uint32_t cr; switch (index_t) { - case 0 ... 15: - cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE; - break; - case 16 ... 31: - cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE; - index_t -= 16; - break; - default: - return ERROR_FAIL; + case 0 ... 15: + cr = a->armv7a_common.debug_base + CPUDBG_BCR_BASE; + break; + case 16 ... 31: + cr = a->armv7a_common.debug_base + CPUDBG_WCR_BASE; + index_t -= 16; + break; + default: + return ERROR_FAIL; } cr += 4 * index_t; @@ -860,22 +860,22 @@ static int cortex_a_internal_restore(struct target *target, bool current, * kill the return address */ switch (arm->core_state) { - case ARM_STATE_ARM: - resume_pc &= 0xFFFFFFFC; - break; - case ARM_STATE_THUMB: - case ARM_STATE_THUMB_EE: - /* When the return address is loaded into PC - * bit 0 must be 1 to stay in Thumb state - */ - resume_pc |= 0x1; - break; - case ARM_STATE_JAZELLE: - LOG_ERROR("How do I resume into Jazelle state??"); - return ERROR_FAIL; - case ARM_STATE_AARCH64: - LOG_ERROR("Shouldn't be in AARCH64 state"); - return ERROR_FAIL; + case ARM_STATE_ARM: + resume_pc &= 0xFFFFFFFC; + break; + case ARM_STATE_THUMB: + case ARM_STATE_THUMB_EE: + /* When the return address is loaded into PC + * bit 0 must be 1 to stay in Thumb state + */ + resume_pc |= 0x1; + break; + case ARM_STATE_JAZELLE: + LOG_ERROR("How do I resume into Jazelle state??"); + return ERROR_FAIL; + case ARM_STATE_AARCH64: + LOG_ERROR("Shouldn't be in AARCH64 state"); + return ERROR_FAIL; } LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc); buf_set_u32(arm->pc->value, 0, 32, resume_pc); @@ -2350,20 +2350,20 @@ static int cortex_a_write_cpu_memory(struct target *target, } else { /* Use slow path. Adjust size for aligned accesses */ switch (address % 4) { - case 1: - case 3: - count *= size; - size = 1; - break; - case 2: - if (size == 4) { - count *= 2; - size = 2; - } - break; - case 0: - default: - break; + case 1: + case 3: + count *= size; + size = 1; + break; + case 2: + if (size == 4) { + count *= 2; + size = 2; + } + break; + case 0: + default: + break; } retval = cortex_a_write_cpu_memory_slow(target, size, count, buffer, &dscr); } @@ -2668,20 +2668,20 @@ static int cortex_a_read_cpu_memory(struct target *target, } else { /* Use slow path. Adjust size for aligned accesses */ switch (address % 4) { - case 1: - case 3: - count *= size; - size = 1; - break; - case 2: - if (size == 4) { - count *= 2; - size = 2; - } - break; - case 0: - default: - break; + case 1: + case 3: + count *= size; + size = 1; + break; + case 2: + if (size == 4) { + count *= 2; + size = 2; + } + break; + case 0: + default: + break; } retval = cortex_a_read_cpu_memory_slow(target, size, count, buffer, &dscr); } diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c index a90610b08..c5d668a4d 100644 --- a/src/target/cortex_m.c +++ b/src/target/cortex_m.c @@ -472,22 +472,22 @@ static int cortex_m_set_maskints_for_halt(struct target *target) { struct cortex_m_common *cortex_m = target_to_cm(target); switch (cortex_m->isrmasking_mode) { - case CORTEX_M_ISRMASK_AUTO: - /* interrupts taken at resume, whether for step or run -> no mask */ - return cortex_m_set_maskints(target, false); + case CORTEX_M_ISRMASK_AUTO: + /* interrupts taken at resume, whether for step or run -> no mask */ + return cortex_m_set_maskints(target, false); - case CORTEX_M_ISRMASK_OFF: - /* interrupts never masked */ - return cortex_m_set_maskints(target, false); + case CORTEX_M_ISRMASK_OFF: + /* interrupts never masked */ + return cortex_m_set_maskints(target, false); - case CORTEX_M_ISRMASK_ON: - /* interrupts always masked */ - return cortex_m_set_maskints(target, true); + case CORTEX_M_ISRMASK_ON: + /* interrupts always masked */ + return cortex_m_set_maskints(target, true); - case CORTEX_M_ISRMASK_STEPONLY: - /* interrupts masked for single step only -> mask now if MASKINTS - * erratum, otherwise only mask before stepping */ - return cortex_m_set_maskints(target, cortex_m->maskints_erratum); + case CORTEX_M_ISRMASK_STEPONLY: + /* interrupts masked for single step only -> mask now if MASKINTS + * erratum, otherwise only mask before stepping */ + return cortex_m_set_maskints(target, cortex_m->maskints_erratum); } return ERROR_OK; } @@ -495,21 +495,21 @@ static int cortex_m_set_maskints_for_halt(struct target *target) static int cortex_m_set_maskints_for_run(struct target *target) { switch (target_to_cm(target)->isrmasking_mode) { - case CORTEX_M_ISRMASK_AUTO: - /* interrupts taken at resume, whether for step or run -> no mask */ - return cortex_m_set_maskints(target, false); + case CORTEX_M_ISRMASK_AUTO: + /* interrupts taken at resume, whether for step or run -> no mask */ + return cortex_m_set_maskints(target, false); - case CORTEX_M_ISRMASK_OFF: - /* interrupts never masked */ - return cortex_m_set_maskints(target, false); + case CORTEX_M_ISRMASK_OFF: + /* interrupts never masked */ + return cortex_m_set_maskints(target, false); - case CORTEX_M_ISRMASK_ON: - /* interrupts always masked */ - return cortex_m_set_maskints(target, true); + case CORTEX_M_ISRMASK_ON: + /* interrupts always masked */ + return cortex_m_set_maskints(target, true); - case CORTEX_M_ISRMASK_STEPONLY: - /* interrupts masked for single step only -> no mask */ - return cortex_m_set_maskints(target, false); + case CORTEX_M_ISRMASK_STEPONLY: + /* interrupts masked for single step only -> no mask */ + return cortex_m_set_maskints(target, false); } return ERROR_OK; } @@ -517,21 +517,21 @@ static int cortex_m_set_maskints_for_run(struct target *target) static int cortex_m_set_maskints_for_step(struct target *target) { switch (target_to_cm(target)->isrmasking_mode) { - case CORTEX_M_ISRMASK_AUTO: - /* the auto-interrupt should already be done -> mask */ - return cortex_m_set_maskints(target, true); + case CORTEX_M_ISRMASK_AUTO: + /* the auto-interrupt should already be done -> mask */ + return cortex_m_set_maskints(target, true); - case CORTEX_M_ISRMASK_OFF: - /* interrupts never masked */ - return cortex_m_set_maskints(target, false); + case CORTEX_M_ISRMASK_OFF: + /* interrupts never masked */ + return cortex_m_set_maskints(target, false); - case CORTEX_M_ISRMASK_ON: - /* interrupts always masked */ - return cortex_m_set_maskints(target, true); + case CORTEX_M_ISRMASK_ON: + /* interrupts always masked */ + return cortex_m_set_maskints(target, true); - case CORTEX_M_ISRMASK_STEPONLY: - /* interrupts masked for single step only -> mask */ - return cortex_m_set_maskints(target, true); + case CORTEX_M_ISRMASK_STEPONLY: + /* interrupts masked for single step only -> mask */ + return cortex_m_set_maskints(target, true); } return ERROR_OK; } @@ -739,61 +739,61 @@ static int cortex_m_examine_exception_reason(struct target *target) if (retval != ERROR_OK) return retval; switch (armv7m->exception_number) { - case 2: /* NMI */ - break; - case 3: /* Hard Fault */ - retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr); + case 2: /* NMI */ + break; + case 3: /* Hard Fault */ + retval = mem_ap_read_atomic_u32(armv7m->debug_ap, NVIC_HFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + if (except_sr & 0x40000000) { + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr); if (retval != ERROR_OK) return retval; - if (except_sr & 0x40000000) { - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &cfsr); - if (retval != ERROR_OK) - return retval; - } - break; - case 4: /* Memory Management */ - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar); - if (retval != ERROR_OK) - return retval; - break; - case 5: /* Bus Fault */ - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar); - if (retval != ERROR_OK) - return retval; - break; - case 6: /* Usage Fault */ - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); - if (retval != ERROR_OK) - return retval; - break; - case 7: /* Secure Fault */ - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr); - if (retval != ERROR_OK) - return retval; - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar); - if (retval != ERROR_OK) - return retval; - break; - case 11: /* SVCall */ - break; - case 12: /* Debug Monitor */ - retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr); - if (retval != ERROR_OK) - return retval; - break; - case 14: /* PendSV */ - break; - case 15: /* SysTick */ - break; - default: - except_sr = 0; - break; + } + break; + case 4: /* Memory Management */ + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_MMFAR, &except_ar); + if (retval != ERROR_OK) + return retval; + break; + case 5: /* Bus Fault */ + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_BFAR, &except_ar); + if (retval != ERROR_OK) + return retval; + break; + case 6: /* Usage Fault */ + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_CFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + break; + case 7: /* Secure Fault */ + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar); + if (retval != ERROR_OK) + return retval; + break; + case 11: /* SVCall */ + break; + case 12: /* Debug Monitor */ + retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_DFSR, &except_sr); + if (retval != ERROR_OK) + return retval; + break; + case 14: /* PendSV */ + break; + case 15: /* SysTick */ + break; + default: + except_sr = 0; + break; } retval = dap_run(swjdp); if (retval == ERROR_OK) @@ -3217,17 +3217,17 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command) } switch (cortex_m->soft_reset_config) { - case CORTEX_M_RESET_SYSRESETREQ: - reset_config = "sysresetreq"; - break; + case CORTEX_M_RESET_SYSRESETREQ: + reset_config = "sysresetreq"; + break; - case CORTEX_M_RESET_VECTRESET: - reset_config = "vectreset"; - break; + case CORTEX_M_RESET_VECTRESET: + reset_config = "vectreset"; + break; - default: - reset_config = "unknown"; - break; + default: + reset_config = "unknown"; + break; } command_print(CMD, "cortex_m reset_config %s", reset_config); diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c index b44be1340..d79d54282 100644 --- a/src/target/dsp563xx.c +++ b/src/target/dsp563xx.c @@ -741,37 +741,37 @@ static int dsp563xx_read_register(struct target *target, int num, int force) arch_info = dsp563xx->core_cache->reg_list[num].arch_info; switch (arch_info->num) { - case DSP563XX_REG_IDX_SSH: - err = dsp563xx_reg_ssh_read(target); - break; - case DSP563XX_REG_IDX_SSL: - err = dsp563xx_reg_ssl_read(target); - break; - case DSP563XX_REG_IDX_PC: - err = dsp563xx_reg_pc_read(target); - break; - case DSP563XX_REG_IDX_IPRC: - case DSP563XX_REG_IDX_IPRP: - case DSP563XX_REG_IDX_BCR: - case DSP563XX_REG_IDX_DCR: - case DSP563XX_REG_IDX_AAR0: - case DSP563XX_REG_IDX_AAR1: - case DSP563XX_REG_IDX_AAR2: - case DSP563XX_REG_IDX_AAR3: - err = dsp563xx_reg_read_high_io(target, - arch_info->instr_mask, &data); - if (err == ERROR_OK) { - dsp563xx->core_regs[num] = data; - dsp563xx->read_core_reg(target, num); - } - break; - default: - err = dsp563xx_reg_read(target, arch_info->eame, &data); - if (err == ERROR_OK) { - dsp563xx->core_regs[num] = data; - dsp563xx->read_core_reg(target, num); - } - break; + case DSP563XX_REG_IDX_SSH: + err = dsp563xx_reg_ssh_read(target); + break; + case DSP563XX_REG_IDX_SSL: + err = dsp563xx_reg_ssl_read(target); + break; + case DSP563XX_REG_IDX_PC: + err = dsp563xx_reg_pc_read(target); + break; + case DSP563XX_REG_IDX_IPRC: + case DSP563XX_REG_IDX_IPRP: + case DSP563XX_REG_IDX_BCR: + case DSP563XX_REG_IDX_DCR: + case DSP563XX_REG_IDX_AAR0: + case DSP563XX_REG_IDX_AAR1: + case DSP563XX_REG_IDX_AAR2: + case DSP563XX_REG_IDX_AAR3: + err = dsp563xx_reg_read_high_io(target, + arch_info->instr_mask, &data); + if (err == ERROR_OK) { + dsp563xx->core_regs[num] = data; + dsp563xx->read_core_reg(target, num); + } + break; + default: + err = dsp563xx_reg_read(target, arch_info->eame, &data); + if (err == ERROR_OK) { + dsp563xx->core_regs[num] = data; + dsp563xx->read_core_reg(target, num); + } + break; } } @@ -793,35 +793,34 @@ static int dsp563xx_write_register(struct target *target, int num, int force) dsp563xx->write_core_reg(target, num); switch (arch_info->num) { - case DSP563XX_REG_IDX_SSH: - err = dsp563xx_reg_ssh_write(target); - break; - case DSP563XX_REG_IDX_PC: - /* pc is updated on resume, no need to write it here */ - break; - case DSP563XX_REG_IDX_IPRC: - case DSP563XX_REG_IDX_IPRP: - case DSP563XX_REG_IDX_BCR: - case DSP563XX_REG_IDX_DCR: - case DSP563XX_REG_IDX_AAR0: - case DSP563XX_REG_IDX_AAR1: - case DSP563XX_REG_IDX_AAR2: - case DSP563XX_REG_IDX_AAR3: - err = dsp563xx_reg_write_high_io(target, - arch_info->instr_mask, - dsp563xx->core_regs[num]); - break; - default: - err = dsp563xx_reg_write(target, - arch_info->instr_mask, - dsp563xx->core_regs[num]); + case DSP563XX_REG_IDX_SSH: + err = dsp563xx_reg_ssh_write(target); + break; + case DSP563XX_REG_IDX_PC: + /* pc is updated on resume, no need to write it here */ + break; + case DSP563XX_REG_IDX_IPRC: + case DSP563XX_REG_IDX_IPRP: + case DSP563XX_REG_IDX_BCR: + case DSP563XX_REG_IDX_DCR: + case DSP563XX_REG_IDX_AAR0: + case DSP563XX_REG_IDX_AAR1: + case DSP563XX_REG_IDX_AAR2: + case DSP563XX_REG_IDX_AAR3: + err = dsp563xx_reg_write_high_io(target, + arch_info->instr_mask, + dsp563xx->core_regs[num]); + break; + default: + err = dsp563xx_reg_write(target, + arch_info->instr_mask, + dsp563xx->core_regs[num]); - if (err == ERROR_OK && arch_info->num == DSP563XX_REG_IDX_SP) { - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0; - dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0; - } - - break; + if (err == ERROR_OK && arch_info->num == DSP563XX_REG_IDX_SP) { + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSH].valid = 0; + dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_SSL].valid = 0; + } + break; } } @@ -1488,14 +1487,14 @@ static int dsp563xx_get_default_memory(void) return MEM_P; switch (c[0]) { - case '1': - return MEM_X; - case '2': - return MEM_Y; - case '3': - return MEM_L; - default: - break; + case '1': + return MEM_X; + case '2': + return MEM_Y; + case '3': + return MEM_L; + default: + break; } return MEM_P; @@ -1527,18 +1526,18 @@ static int dsp563xx_read_memory_core(struct target *target, } switch (mem_type) { - case MEM_X: - /* TODO: mark effected queued registers */ - move_cmd = 0x61d800; - break; - case MEM_Y: - move_cmd = 0x69d800; - break; - case MEM_P: - move_cmd = 0x07d891; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case MEM_X: + /* TODO: mark effected queued registers */ + move_cmd = 0x61d800; + break; + case MEM_Y: + move_cmd = 0x69d800; + break; + case MEM_P: + move_cmd = 0x07d891; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } /* we use r0 to store temporary data */ @@ -1708,19 +1707,19 @@ static int dsp563xx_write_memory_core(struct target *target, } switch (mem_type) { - case MEM_X: - /* invalidate affected x registers */ - dsp563xx_invalidate_x_context(target, address, address + count - 1); - move_cmd = 0x615800; - break; - case MEM_Y: - move_cmd = 0x695800; - break; - case MEM_P: - move_cmd = 0x075891; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case MEM_X: + /* invalidate affected x registers */ + dsp563xx_invalidate_x_context(target, address, address + count - 1); + move_cmd = 0x615800; + break; + case MEM_Y: + move_cmd = 0x695800; + break; + case MEM_P: + move_cmd = 0x075891; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } /* we use r0 to store temporary data */ @@ -1894,55 +1893,55 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres if (err == ERROR_OK) { obcr_value |= OBCR_B0_OR_B1; switch (mem_type) { - case MEM_X: - obcr_value |= OBCR_BP_MEM_X; - break; - case MEM_Y: - obcr_value |= OBCR_BP_MEM_Y; - break; - case MEM_P: - obcr_value |= OBCR_BP_MEM_P; - break; - default: - LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type); - err = ERROR_TARGET_INVALID; + case MEM_X: + obcr_value |= OBCR_BP_MEM_X; + break; + case MEM_Y: + obcr_value |= OBCR_BP_MEM_Y; + break; + case MEM_P: + obcr_value |= OBCR_BP_MEM_P; + break; + default: + LOG_ERROR("Unknown mem_type parameter (%" PRIu32 ")", mem_type); + err = ERROR_TARGET_INVALID; } } if (err == ERROR_OK) { switch (rw) { - case WPT_READ: - obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ); - break; - case WPT_WRITE: - obcr_value |= OBCR_BP_0(OBCR_BP_ON_WRITE); - break; - case WPT_ACCESS: - obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ|OBCR_BP_ON_WRITE); - break; - default: - LOG_ERROR("Unsupported write mode (%d)", rw); - err = ERROR_TARGET_INVALID; + case WPT_READ: + obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ); + break; + case WPT_WRITE: + obcr_value |= OBCR_BP_0(OBCR_BP_ON_WRITE); + break; + case WPT_ACCESS: + obcr_value |= OBCR_BP_0(OBCR_BP_ON_READ | OBCR_BP_ON_WRITE); + break; + default: + LOG_ERROR("Unsupported write mode (%d)", rw); + err = ERROR_TARGET_INVALID; } } if (err == ERROR_OK) { switch (cond) { - case EQUAL: - obcr_value |= OBCR_BP_0(OBCR_BP_CC_EQUAL); - break; - case NOT_EQUAL: - obcr_value |= OBCR_BP_0(OBCR_BP_CC_NOT_EQUAL); - break; - case LESS_THAN: - obcr_value |= OBCR_BP_0(OBCR_BP_CC_LESS_THAN); - break; - case GREATER: - obcr_value |= OBCR_BP_0(OBCR_BP_CC_GREATER_THAN); - break; - default: - LOG_ERROR("Unsupported condition code (%d)", cond); - err = ERROR_TARGET_INVALID; + case EQUAL: + obcr_value |= OBCR_BP_0(OBCR_BP_CC_EQUAL); + break; + case NOT_EQUAL: + obcr_value |= OBCR_BP_0(OBCR_BP_CC_NOT_EQUAL); + break; + case LESS_THAN: + obcr_value |= OBCR_BP_0(OBCR_BP_CC_LESS_THAN); + break; + case GREATER: + obcr_value |= OBCR_BP_0(OBCR_BP_CC_GREATER_THAN); + break; + default: + LOG_ERROR("Unsupported condition code (%d)", cond); + err = ERROR_TARGET_INVALID; } } @@ -2004,17 +2003,17 @@ COMMAND_HANDLER(dsp563xx_add_watchpoint_command) uint32_t mem_type = 0; switch (CMD_NAME[2]) { - case 'x': - mem_type = MEM_X; - break; - case 'y': - mem_type = MEM_Y; - break; - case 'p': - mem_type = MEM_P; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'x': + mem_type = MEM_X; + break; + case 'y': + mem_type = MEM_Y; + break; + case 'p': + mem_type = MEM_P; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (CMD_ARGC < 2) @@ -2026,35 +2025,35 @@ COMMAND_HANDLER(dsp563xx_add_watchpoint_command) enum watchpoint_condition cond; switch (CMD_ARGV[0][0]) { - case '>': - cond = GREATER; - break; - case '<': - cond = LESS_THAN; - break; - case '=': - cond = EQUAL; - break; - case '!': - cond = NOT_EQUAL; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case '>': + cond = GREATER; + break; + case '<': + cond = LESS_THAN; + break; + case '=': + cond = EQUAL; + break; + case '!': + cond = NOT_EQUAL; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } enum watchpoint_rw rw; switch (CMD_ARGV[1][0]) { - case 'r': - rw = WPT_READ; - break; - case 'w': - rw = WPT_WRITE; - break; - case 'a': - rw = WPT_ACCESS; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'r': + rw = WPT_READ; + break; + case 'w': + rw = WPT_WRITE; + break; + case 'a': + rw = WPT_ACCESS; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } err = dsp563xx_add_custom_watchpoint(target, address, mem_type, rw, cond); @@ -2095,28 +2094,28 @@ COMMAND_HANDLER(dsp563xx_mem_command) uint8_t *buffer, *b; switch (CMD_NAME[1]) { - case 'w': - read_mem = 0; - break; - case 'd': - read_mem = 1; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'w': + read_mem = 0; + break; + case 'd': + read_mem = 1; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } switch (CMD_NAME[3]) { - case 'x': - mem_type = MEM_X; - break; - case 'y': - mem_type = MEM_Y; - break; - case 'p': - mem_type = MEM_P; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'x': + mem_type = MEM_X; + break; + case 'y': + mem_type = MEM_Y; + break; + case 'p': + mem_type = MEM_P; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } if (CMD_ARGC > 0) diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c index 7bf5c7c49..f6e330b37 100644 --- a/src/target/embeddedice.c +++ b/src/target/embeddedice.c @@ -219,69 +219,69 @@ struct reg_cache *embeddedice_build_reg_cache(struct target *target, LOG_INFO("Embedded ICE version %d", eice_version); switch (eice_version) { - case 1: - /* ARM7TDMI r3, ARM7TDMI-S r3 - * - * REVISIT docs say ARM7TDMI-S r4 uses version 1 but - * that it has 6-bit CTRL and 5-bit STAT... doc bug? - * ARM7TDMI r4 docs say EICE v4. - */ - reg_list[EICE_DBG_CTRL].size = 3; - reg_list[EICE_DBG_STAT].size = 5; + case 1: + /* ARM7TDMI r3, ARM7TDMI-S r3 + * + * REVISIT docs say ARM7TDMI-S r4 uses version 1 but + * that it has 6-bit CTRL and 5-bit STAT... doc bug? + * ARM7TDMI r4 docs say EICE v4. + */ + reg_list[EICE_DBG_CTRL].size = 3; + reg_list[EICE_DBG_STAT].size = 5; + break; + case 2: + /* ARM9TDMI */ + reg_list[EICE_DBG_CTRL].size = 4; + reg_list[EICE_DBG_STAT].size = 5; + arm7_9->has_single_step = 1; + break; + case 3: + LOG_ERROR("EmbeddedICE v%d handling might be broken", + eice_version); + reg_list[EICE_DBG_CTRL].size = 6; + reg_list[EICE_DBG_STAT].size = 5; + arm7_9->has_single_step = 1; + arm7_9->has_monitor_mode = 1; + break; + case 4: + /* ARM7TDMI r4 */ + reg_list[EICE_DBG_CTRL].size = 6; + reg_list[EICE_DBG_STAT].size = 5; + arm7_9->has_monitor_mode = 1; + break; + case 5: + /* ARM9E-S rev 1 */ + reg_list[EICE_DBG_CTRL].size = 6; + reg_list[EICE_DBG_STAT].size = 5; + arm7_9->has_single_step = 1; + arm7_9->has_monitor_mode = 1; + break; + case 6: + /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */ + reg_list[EICE_DBG_CTRL].size = 6; + reg_list[EICE_DBG_STAT].size = 10; + /* DBG_STAT has MOE bits */ + arm7_9->has_monitor_mode = 1; + break; + case 7: + LOG_ERROR("EmbeddedICE v%d handling might be broken", + eice_version); + reg_list[EICE_DBG_CTRL].size = 6; + reg_list[EICE_DBG_STAT].size = 5; + arm7_9->has_monitor_mode = 1; + break; + default: + /* + * The Feroceon implementation has the version number + * in some unusual bits. Let feroceon.c validate it + * and do the appropriate setup itself. + */ + if (strcmp(target_type_name(target), "feroceon") == 0 || + strcmp(target_type_name(target), "dragonite") == 0) break; - case 2: - /* ARM9TDMI */ - reg_list[EICE_DBG_CTRL].size = 4; - reg_list[EICE_DBG_STAT].size = 5; - arm7_9->has_single_step = 1; - break; - case 3: - LOG_ERROR("EmbeddedICE v%d handling might be broken", - eice_version); - reg_list[EICE_DBG_CTRL].size = 6; - reg_list[EICE_DBG_STAT].size = 5; - arm7_9->has_single_step = 1; - arm7_9->has_monitor_mode = 1; - break; - case 4: - /* ARM7TDMI r4 */ - reg_list[EICE_DBG_CTRL].size = 6; - reg_list[EICE_DBG_STAT].size = 5; - arm7_9->has_monitor_mode = 1; - break; - case 5: - /* ARM9E-S rev 1 */ - reg_list[EICE_DBG_CTRL].size = 6; - reg_list[EICE_DBG_STAT].size = 5; - arm7_9->has_single_step = 1; - arm7_9->has_monitor_mode = 1; - break; - case 6: - /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */ - reg_list[EICE_DBG_CTRL].size = 6; - reg_list[EICE_DBG_STAT].size = 10; - /* DBG_STAT has MOE bits */ - arm7_9->has_monitor_mode = 1; - break; - case 7: - LOG_ERROR("EmbeddedICE v%d handling might be broken", - eice_version); - reg_list[EICE_DBG_CTRL].size = 6; - reg_list[EICE_DBG_STAT].size = 5; - arm7_9->has_monitor_mode = 1; - break; - default: - /* - * The Feroceon implementation has the version number - * in some unusual bits. Let feroceon.c validate it - * and do the appropriate setup itself. - */ - if (strcmp(target_type_name(target), "feroceon") == 0 || - strcmp(target_type_name(target), "dragonite") == 0) - break; - LOG_ERROR("unknown EmbeddedICE version " - "(comms ctrl: 0x%8.8" PRIx32 ")", - buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); + LOG_ERROR("unknown EmbeddedICE version " + "(comms ctrl: 0x%8.8" PRIx32 ")", + buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32)); } /* On Feroceon and Dragonite the second unit is seemingly missing. */ diff --git a/src/target/esirisc.c b/src/target/esirisc.c index fac5dc72e..bcb0515d0 100644 --- a/src/target/esirisc.c +++ b/src/target/esirisc.c @@ -367,24 +367,24 @@ static int esirisc_read_memory(struct target *target, target_addr_t address, void *value_p; switch (size) { - case sizeof(value.word): - value_p = &value.word; - retval = esirisc_jtag_read_word(jtag_info, address, value_p); - break; + case sizeof(value.word): + value_p = &value.word; + retval = esirisc_jtag_read_word(jtag_info, address, value_p); + break; - case sizeof(value.hword): - value_p = &value.hword; - retval = esirisc_jtag_read_hword(jtag_info, address, value_p); - break; + case sizeof(value.hword): + value_p = &value.hword; + retval = esirisc_jtag_read_hword(jtag_info, address, value_p); + break; - case sizeof(value.byte): - value_p = &value.byte; - retval = esirisc_jtag_read_byte(jtag_info, address, value_p); - break; + case sizeof(value.byte): + value_p = &value.byte; + retval = esirisc_jtag_read_byte(jtag_info, address, value_p); + break; - default: - LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); - return ERROR_FAIL; + default: + LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); + return ERROR_FAIL; } if (retval != ERROR_OK) { @@ -415,24 +415,24 @@ static int esirisc_write_memory(struct target *target, target_addr_t address, union esirisc_memory value; switch (size) { - case sizeof(value.word): - value.word = buf_get_u32(buffer, 0, num_bits); - retval = esirisc_jtag_write_word(jtag_info, address, value.word); - break; + case sizeof(value.word): + value.word = buf_get_u32(buffer, 0, num_bits); + retval = esirisc_jtag_write_word(jtag_info, address, value.word); + break; - case sizeof(value.hword): - value.hword = buf_get_u32(buffer, 0, num_bits); - retval = esirisc_jtag_write_hword(jtag_info, address, value.hword); - break; + case sizeof(value.hword): + value.hword = buf_get_u32(buffer, 0, num_bits); + retval = esirisc_jtag_write_hword(jtag_info, address, value.hword); + break; - case sizeof(value.byte): - value.byte = buf_get_u32(buffer, 0, num_bits); - retval = esirisc_jtag_write_byte(jtag_info, address, value.byte); - break; + case sizeof(value.byte): + value.byte = buf_get_u32(buffer, 0, num_bits); + retval = esirisc_jtag_write_byte(jtag_info, address, value.byte); + break; - default: - LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); - return ERROR_FAIL; + default: + LOG_TARGET_ERROR(target, "unsupported size: %" PRIu32, size); + return ERROR_FAIL; } if (retval != ERROR_OK) { @@ -641,25 +641,25 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc uint32_t sn; switch (watchpoint->length) { - case sizeof(uint64_t): - sn = 0x3; - break; - case sizeof(uint32_t): - sn = 0x2; - break; + case sizeof(uint64_t): + sn = 0x3; + break; + case sizeof(uint32_t): + sn = 0x2; + break; - case sizeof(uint16_t): - sn = 0x1; - break; + case sizeof(uint16_t): + sn = 0x1; + break; - case sizeof(uint8_t): - sn = 0x0; - break; + case sizeof(uint8_t): + sn = 0x0; + break; - default: - LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32, - watchpoint->length); - return ERROR_FAIL; + default: + LOG_TARGET_ERROR(target, "unsupported length: %" PRIu32, + watchpoint->length); + return ERROR_FAIL; } dbs |= (sn << (2 * wp_index)); /* DBS.Sn */ @@ -679,21 +679,21 @@ static int esirisc_add_watchpoint(struct target *target, struct watchpoint *watc uint32_t dn; switch (watchpoint->rw) { - case WPT_READ: - dn = 0x1; - break; + case WPT_READ: + dn = 0x1; + break; - case WPT_WRITE: - dn = 0x2; - break; + case WPT_WRITE: + dn = 0x2; + break; - case WPT_ACCESS: - dn = 0x3; - break; + case WPT_ACCESS: + dn = 0x3; + break; - default: - LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw); - return ERROR_FAIL; + default: + LOG_TARGET_ERROR(target, "unsupported rw: %" PRId32, watchpoint->rw); + return ERROR_FAIL; } dbc |= (dn << (2 * wp_index)); /* DBC.Dn */ @@ -1046,33 +1046,33 @@ static int esirisc_debug_entry(struct target *target) uint32_t eid = buf_get_u32(esirisc->eid->value, 0, esirisc->eid->size); switch (eid) { - /* - * InstBreakpoint exceptions are also raised when a core is - * halted for debugging. The following is required to - * determine if a breakpoint was encountered. - */ - case EID_INST_BREAKPOINT: - breakpoint = breakpoint_find(target, - buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size)); - target->debug_reason = (breakpoint) ? - DBG_REASON_BREAKPOINT : DBG_REASON_DBGRQ; - break; + /* + * InstBreakpoint exceptions are also raised when a core is + * halted for debugging. The following is required to + * determine if a breakpoint was encountered. + */ + case EID_INST_BREAKPOINT: + breakpoint = breakpoint_find(target, + buf_get_u32(esirisc->epc->value, 0, esirisc->epc->size)); + target->debug_reason = (breakpoint) ? + DBG_REASON_BREAKPOINT : DBG_REASON_DBGRQ; + break; - /* - * eSi-RISC treats watchpoints similarly to breakpoints, - * however GDB will not request to step over the current - * instruction when a watchpoint fires. The following is - * required to resume the target. - */ - case EID_DATA_BREAKPOINT: - esirisc_remove_watchpoints(target); - esirisc_debug_step(target); - esirisc_add_watchpoints(target); - target->debug_reason = DBG_REASON_WATCHPOINT; - break; + /* + * eSi-RISC treats watchpoints similarly to breakpoints, + * however GDB will not request to step over the current + * instruction when a watchpoint fires. The following is + * required to resume the target. + */ + case EID_DATA_BREAKPOINT: + esirisc_remove_watchpoints(target); + esirisc_debug_step(target); + esirisc_add_watchpoints(target); + target->debug_reason = DBG_REASON_WATCHPOINT; + break; - default: - target->debug_reason = DBG_REASON_DBGRQ; + default: + target->debug_reason = DBG_REASON_DBGRQ; } } diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c index a1d92d1ca..2dc08e5d2 100644 --- a/src/target/esirisc_trace.c +++ b/src/target/esirisc_trace.c @@ -389,84 +389,87 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b goto fail; switch (id) { - case ESIRISC_TRACE_ID_EXECUTE: - case ESIRISC_TRACE_ID_STALL: - case ESIRISC_TRACE_ID_BRANCH: - command_print(cmd, "%s", esirisc_trace_id_strings[id]); + case ESIRISC_TRACE_ID_EXECUTE: + case ESIRISC_TRACE_ID_STALL: + case ESIRISC_TRACE_ID_BRANCH: + command_print(cmd, "%s", esirisc_trace_id_strings[id]); + break; + + case ESIRISC_TRACE_ID_EXTENDED: { + uint32_t ext_id; + + retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 4, &ext_id); + if (retval != ERROR_OK) + goto fail; + + switch (ext_id) { + case ESIRISC_TRACE_EXT_ID_STOP: + case ESIRISC_TRACE_EXT_ID_WAIT: + case ESIRISC_TRACE_EXT_ID_MULTICYCLE: + command_print(cmd, "%s", esirisc_trace_ext_id_strings[ext_id]); break; - case ESIRISC_TRACE_ID_EXTENDED: { - uint32_t ext_id; + case ESIRISC_TRACE_EXT_ID_ERET: + case ESIRISC_TRACE_EXT_ID_PC: + case ESIRISC_TRACE_EXT_ID_INDIRECT: + case ESIRISC_TRACE_EXT_ID_END_PC: { + uint32_t pc; - retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 4, &ext_id); + retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &pc); if (retval != ERROR_OK) goto fail; - switch (ext_id) { - case ESIRISC_TRACE_EXT_ID_STOP: - case ESIRISC_TRACE_EXT_ID_WAIT: - case ESIRISC_TRACE_EXT_ID_MULTICYCLE: - command_print(cmd, "%s", esirisc_trace_ext_id_strings[ext_id]); - break; + command_print(cmd, "%s PC: 0x%" PRIx32, + esirisc_trace_ext_id_strings[ext_id], pc); - case ESIRISC_TRACE_EXT_ID_ERET: - case ESIRISC_TRACE_EXT_ID_PC: - case ESIRISC_TRACE_EXT_ID_INDIRECT: - case ESIRISC_TRACE_EXT_ID_END_PC: { - uint32_t pc; - - retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &pc); - if (retval != ERROR_OK) - goto fail; - - command_print(cmd, "%s PC: 0x%" PRIx32, - esirisc_trace_ext_id_strings[ext_id], pc); - - if (ext_id == ESIRISC_TRACE_EXT_ID_END_PC) { - command_print(cmd, "--- end of trace ---"); - return ERROR_OK; - } - break; - } - case ESIRISC_TRACE_EXT_ID_EXCEPTION: { - uint32_t eid, epc; - - retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &eid); - if (retval != ERROR_OK) - goto fail; - - retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &epc); - if (retval != ERROR_OK) - goto fail; - - command_print(cmd, "%s EID: 0x%" PRIx32 ", EPC: 0x%" PRIx32, - esirisc_trace_ext_id_strings[ext_id], eid, epc); - break; - } - case ESIRISC_TRACE_EXT_ID_COUNT: { - uint32_t count; - - retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &count); - if (retval != ERROR_OK) - goto fail; - - command_print(cmd, "repeats %" PRIu32 " %s", count, - (count == 1) ? "time" : "times"); - break; - } - case ESIRISC_TRACE_EXT_ID_END: - command_print(cmd, "--- end of trace ---"); - return ERROR_OK; - - default: - command_print(cmd, "invalid extended trace ID: %" PRIu32, ext_id); - return ERROR_FAIL; + if (ext_id == ESIRISC_TRACE_EXT_ID_END_PC) { + command_print(cmd, "--- end of trace ---"); + return ERROR_OK; } break; } + + case ESIRISC_TRACE_EXT_ID_EXCEPTION: { + uint32_t eid, epc; + + retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &eid); + if (retval != ERROR_OK) + goto fail; + + retval = esirisc_trace_buf_get_pc(target, buffer, size, &pos, &epc); + if (retval != ERROR_OK) + goto fail; + + command_print(cmd, "%s EID: 0x%" PRIx32 ", EPC: 0x%" PRIx32, + esirisc_trace_ext_id_strings[ext_id], eid, epc); + break; + } + + case ESIRISC_TRACE_EXT_ID_COUNT: { + uint32_t count; + + retval = esirisc_trace_buf_get_u32(buffer, size, &pos, 6, &count); + if (retval != ERROR_OK) + goto fail; + + command_print(cmd, "repeats %" PRIu32 " %s", count, + (count == 1) ? "time" : "times"); + break; + } + + case ESIRISC_TRACE_EXT_ID_END: + command_print(cmd, "--- end of trace ---"); + return ERROR_OK; + default: - command_print(cmd, "invalid trace ID: %" PRIu32, id); + command_print(cmd, "invalid extended trace ID: %" PRIu32, ext_id); return ERROR_FAIL; + } + break; + } + default: + command_print(cmd, "invalid trace ID: %" PRIu32, id); + return ERROR_FAIL; } } @@ -511,21 +514,21 @@ static int esirisc_trace_analyze(struct command_invocation *cmd, uint8_t *buffer struct esirisc_trace *trace_info = &esirisc->trace_info; switch (trace_info->format) { - case ESIRISC_TRACE_FORMAT_FULL: - command_print(cmd, "--- full pipeline ---"); - return esirisc_trace_analyze_full(cmd, buffer, size); + case ESIRISC_TRACE_FORMAT_FULL: + command_print(cmd, "--- full pipeline ---"); + return esirisc_trace_analyze_full(cmd, buffer, size); - case ESIRISC_TRACE_FORMAT_BRANCH: - command_print(cmd, "--- branches taken ---"); - return esirisc_trace_analyze_full(cmd, buffer, size); + case ESIRISC_TRACE_FORMAT_BRANCH: + command_print(cmd, "--- branches taken ---"); + return esirisc_trace_analyze_full(cmd, buffer, size); - case ESIRISC_TRACE_FORMAT_ICACHE: - command_print(cmd, "--- icache misses ---"); - return esirisc_trace_analyze_simple(cmd, buffer, size); + case ESIRISC_TRACE_FORMAT_ICACHE: + command_print(cmd, "--- icache misses ---"); + return esirisc_trace_analyze_simple(cmd, buffer, size); - default: - command_print(cmd, "invalid trace format: %i", trace_info->format); - return ERROR_FAIL; + default: + command_print(cmd, "invalid trace format: %i", trace_info->format); + return ERROR_FAIL; } } diff --git a/src/target/etm.c b/src/target/etm.c index 90fa3fc6d..1a41d1c8b 100644 --- a/src/target/etm.c +++ b/src/target/etm.c @@ -326,24 +326,24 @@ struct reg_cache *etm_build_reg_cache(struct target *target, } else { switch (config >> 28) { - case 7: - case 5: - case 3: - bcd_vers = 0x13; - break; - case 4: - case 2: - bcd_vers = 0x12; - break; - case 1: - bcd_vers = 0x11; - break; - case 0: - bcd_vers = 0x10; - break; - default: - LOG_WARNING("Bad ETMv1 protocol %d", config >> 28); - goto fail; + case 7: + case 5: + case 3: + bcd_vers = 0x13; + break; + case 4: + case 2: + bcd_vers = 0x12; + break; + case 1: + bcd_vers = 0x11; + break; + case 0: + bcd_vers = 0x10; + break; + default: + LOG_WARNING("Bad ETMv1 protocol %d", config >> 28); + goto fail; } } etm_ctx->bcd_vers = bcd_vers; @@ -923,48 +923,48 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio ctx->pipe_index += 2; switch (ctx->last_branch_reason) { - case 0x0: /* normal PC change */ - next_pc = ctx->last_branch; - break; - case 0x1: /* tracing enabled */ + case 0x0: /* normal PC change */ + next_pc = ctx->last_branch; + break; + case 0x1: /* tracing enabled */ + command_print(cmd, + "--- tracing enabled at 0x%8.8" PRIx32 " ---", + ctx->last_branch); + ctx->current_pc = ctx->last_branch; + ctx->pipe_index++; + continue; + case 0x2: /* trace restarted after FIFO overflow */ + command_print(cmd, + "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", + ctx->last_branch); + ctx->current_pc = ctx->last_branch; + ctx->pipe_index++; + continue; + case 0x3: /* exit from debug state */ + command_print(cmd, + "--- exit from debug state at 0x%8.8" PRIx32 " ---", + ctx->last_branch); + ctx->current_pc = ctx->last_branch; + ctx->pipe_index++; + continue; + case 0x4: /* periodic synchronization point */ + next_pc = ctx->last_branch; + /* if we had no valid PC prior to this synchronization point, + * we have to move on with the next trace cycle + */ + if (!current_pc_ok) { command_print(cmd, - "--- tracing enabled at 0x%8.8" PRIx32 " ---", - ctx->last_branch); - ctx->current_pc = ctx->last_branch; + "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", + next_pc); + ctx->current_pc = next_pc; ctx->pipe_index++; continue; - case 0x2: /* trace restarted after FIFO overflow */ - command_print(cmd, - "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", - ctx->last_branch); - ctx->current_pc = ctx->last_branch; - ctx->pipe_index++; - continue; - case 0x3: /* exit from debug state */ - command_print(cmd, - "--- exit from debug state at 0x%8.8" PRIx32 " ---", - ctx->last_branch); - ctx->current_pc = ctx->last_branch; - ctx->pipe_index++; - continue; - case 0x4: /* periodic synchronization point */ - next_pc = ctx->last_branch; - /* if we had no valid PC prior to this synchronization point, - * we have to move on with the next trace cycle - */ - if (!current_pc_ok) { - command_print(cmd, - "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", - next_pc); - ctx->current_pc = next_pc; - ctx->pipe_index++; - continue; - } - break; - default: /* reserved */ - LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", - ctx->last_branch_reason); - return ERROR_FAIL; + } + break; + default: /* reserved */ + LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", + ctx->last_branch_reason); + return ERROR_FAIL; } /* if we got here the branch was a normal PC change @@ -1144,21 +1144,21 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update, uint8_t context_id; COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], context_id); switch (context_id) { - case 0: - tracemode |= ETM_CTRL_CONTEXTID_NONE; - break; - case 8: - tracemode |= ETM_CTRL_CONTEXTID_8; - break; - case 16: - tracemode |= ETM_CTRL_CONTEXTID_16; - break; - case 32: - tracemode |= ETM_CTRL_CONTEXTID_32; - break; - default: - command_print(CMD, "invalid option '%s'", CMD_ARGV[1]); - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + tracemode |= ETM_CTRL_CONTEXTID_NONE; + break; + case 8: + tracemode |= ETM_CTRL_CONTEXTID_8; + break; + case 16: + tracemode |= ETM_CTRL_CONTEXTID_16; + break; + case 32: + tracemode |= ETM_CTRL_CONTEXTID_32; + break; + default: + command_print(CMD, "invalid option '%s'", CMD_ARGV[1]); + return ERROR_COMMAND_SYNTAX_ERROR; } bool etmv1_cycle_accurate; @@ -1201,14 +1201,14 @@ COMMAND_HANDLER(handle_etm_tracemode_command) uint32_t tracemode = etm->control; switch (CMD_ARGC) { - case 0: - break; - case 4: - CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, - &tracemode); - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + break; + case 4: + CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update, + &tracemode); + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } /** @@ -1219,33 +1219,33 @@ COMMAND_HANDLER(handle_etm_tracemode_command) command_print(CMD, "current tracemode configuration:"); switch (tracemode & ETM_CTRL_TRACE_MASK) { - default: - command_print(CMD, "data tracing: none"); - break; - case ETM_CTRL_TRACE_DATA: - command_print(CMD, "data tracing: data only"); - break; - case ETM_CTRL_TRACE_ADDR: - command_print(CMD, "data tracing: address only"); - break; - case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR: - command_print(CMD, "data tracing: address and data"); - break; + default: + command_print(CMD, "data tracing: none"); + break; + case ETM_CTRL_TRACE_DATA: + command_print(CMD, "data tracing: data only"); + break; + case ETM_CTRL_TRACE_ADDR: + command_print(CMD, "data tracing: address only"); + break; + case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR: + command_print(CMD, "data tracing: address and data"); + break; } switch (tracemode & ETM_CTRL_CONTEXTID_MASK) { - case ETM_CTRL_CONTEXTID_NONE: - command_print(CMD, "contextid tracing: none"); - break; - case ETM_CTRL_CONTEXTID_8: - command_print(CMD, "contextid tracing: 8 bit"); - break; - case ETM_CTRL_CONTEXTID_16: - command_print(CMD, "contextid tracing: 16 bit"); - break; - case ETM_CTRL_CONTEXTID_32: - command_print(CMD, "contextid tracing: 32 bit"); - break; + case ETM_CTRL_CONTEXTID_NONE: + command_print(CMD, "contextid tracing: none"); + break; + case ETM_CTRL_CONTEXTID_8: + command_print(CMD, "contextid tracing: 8 bit"); + break; + case ETM_CTRL_CONTEXTID_16: + command_print(CMD, "contextid tracing: 16 bit"); + break; + case ETM_CTRL_CONTEXTID_32: + command_print(CMD, "contextid tracing: 32 bit"); + break; } if (tracemode & ETM_CTRL_CYCLE_ACCURATE) @@ -1333,39 +1333,39 @@ COMMAND_HANDLER(handle_etm_config_command) uint8_t port_width; COMMAND_PARSE_NUMBER(u8, CMD_ARGV[1], port_width); switch (port_width) { - /* before ETMv3.0 */ - case 4: - portmode |= ETM_PORT_4BIT; - break; - case 8: - portmode |= ETM_PORT_8BIT; - break; - case 16: - portmode |= ETM_PORT_16BIT; - break; - /* ETMv3.0 and later*/ - case 24: - portmode |= ETM_PORT_24BIT; - break; - case 32: - portmode |= ETM_PORT_32BIT; - break; - case 48: - portmode |= ETM_PORT_48BIT; - break; - case 64: - portmode |= ETM_PORT_64BIT; - break; - case 1: - portmode |= ETM_PORT_1BIT; - break; - case 2: - portmode |= ETM_PORT_2BIT; - break; - default: - command_print(CMD, - "unsupported ETM port width '%s'", CMD_ARGV[1]); - return ERROR_FAIL; + /* before ETMv3.0 */ + case 4: + portmode |= ETM_PORT_4BIT; + break; + case 8: + portmode |= ETM_PORT_8BIT; + break; + case 16: + portmode |= ETM_PORT_16BIT; + break; + /* ETMv3.0 and later*/ + case 24: + portmode |= ETM_PORT_24BIT; + break; + case 32: + portmode |= ETM_PORT_32BIT; + break; + case 48: + portmode |= ETM_PORT_48BIT; + break; + case 64: + portmode |= ETM_PORT_64BIT; + break; + case 1: + portmode |= ETM_PORT_1BIT; + break; + case 2: + portmode |= ETM_PORT_2BIT; + break; + default: + command_print(CMD, + "unsupported ETM port width '%s'", CMD_ARGV[1]); + return ERROR_FAIL; } if (strcmp("normal", CMD_ARGV[2]) == 0) @@ -1496,38 +1496,38 @@ COMMAND_HANDLER(handle_etm_info_command) if (etm->bcd_vers >= 0x30) max_port_size |= (config >> 6) & 0x08; switch (max_port_size) { - /* before ETMv3.0 */ - case 0: - max_port_size = 4; - break; - case 1: - max_port_size = 8; - break; - case 2: - max_port_size = 16; - break; - /* ETMv3.0 and later*/ - case 3: - max_port_size = 24; - break; - case 4: - max_port_size = 32; - break; - case 5: - max_port_size = 48; - break; - case 6: - max_port_size = 64; - break; - case 8: - max_port_size = 1; - break; - case 9: - max_port_size = 2; - break; - default: - LOG_ERROR("Illegal max_port_size"); - return ERROR_FAIL; + /* before ETMv3.0 */ + case 0: + max_port_size = 4; + break; + case 1: + max_port_size = 8; + break; + case 2: + max_port_size = 16; + break; + /* ETMv3.0 and later*/ + case 3: + max_port_size = 24; + break; + case 4: + max_port_size = 32; + break; + case 5: + max_port_size = 48; + break; + case 6: + max_port_size = 64; + break; + case 8: + max_port_size = 1; + break; + case 9: + max_port_size = 2; + break; + default: + LOG_ERROR("Illegal max_port_size"); + return ERROR_FAIL; } command_print(CMD, "max. port size: %i", max_port_size); @@ -1966,19 +1966,19 @@ COMMAND_HANDLER(handle_etm_analyze_command) if (retval != ERROR_OK) { /* FIX! error should be reported inside etmv1_analyze_trace() */ switch (retval) { - case ERROR_ETM_ANALYSIS_FAILED: - command_print(CMD, - "further analysis failed (corrupted trace data or just end of data"); - break; - case ERROR_TRACE_INSTRUCTION_UNAVAILABLE: - command_print(CMD, - "no instruction for current address available, analysis aborted"); - break; - case ERROR_TRACE_IMAGE_UNAVAILABLE: - command_print(CMD, "no image available for trace analysis"); - break; - default: - command_print(CMD, "unknown error"); + case ERROR_ETM_ANALYSIS_FAILED: + command_print(CMD, + "further analysis failed (corrupted trace data or just end of data"); + break; + case ERROR_TRACE_INSTRUCTION_UNAVAILABLE: + command_print(CMD, + "no instruction for current address available, analysis aborted"); + break; + case ERROR_TRACE_IMAGE_UNAVAILABLE: + command_print(CMD, "no image available for trace analysis"); + break; + default: + command_print(CMD, "unknown error"); } } diff --git a/src/target/fa526.c b/src/target/fa526.c index 254e5be6e..8afb1f006 100644 --- a/src/target/fa526.c +++ b/src/target/fa526.c @@ -80,15 +80,15 @@ static void fa526_read_core_regs_target_buffer(struct target *target, if (mask & (1 << i)) /* nothing fetched, STM in MEMORY (i'th cycle) */ switch (size) { - case 4: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); - break; - case 2: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); - break; - case 1: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); - break; + case 4: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); + break; + case 2: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); + break; + case 1: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); + break; } } } diff --git a/src/target/feroceon.c b/src/target/feroceon.c index fe1c39fe3..2bb7c6a3e 100644 --- a/src/target/feroceon.c +++ b/src/target/feroceon.c @@ -191,15 +191,15 @@ static void feroceon_read_core_regs_target_buffer(struct target *target, for (i = 0; i <= 15; i++) { if (mask & (1 << i)) { switch (size) { - case 4: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); - break; - case 2: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); - break; - case 1: - arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); - break; + case 4: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be); + break; + case 2: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be); + break; + case 1: + arm9tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be); + break; } } } diff --git a/src/target/image.c b/src/target/image.c index 105501fd4..9b7031b29 100644 --- a/src/target/image.c +++ b/src/target/image.c @@ -815,36 +815,35 @@ static int image_mot_buffer_complete_inner(struct image *image, } } else if (record_type >= 1 && record_type <= 3) { switch (record_type) { - case 1: - /* S1 - 16 bit address data record */ - sscanf(&lpsz_line[bytes_read], "%4" SCNx32, &address); - cal_checksum += (uint8_t)(address >> 8); - cal_checksum += (uint8_t)address; - bytes_read += 4; - count -= 2; - break; + case 1: + /* S1 - 16 bit address data record */ + sscanf(&lpsz_line[bytes_read], "%4" SCNx32, &address); + cal_checksum += (uint8_t)(address >> 8); + cal_checksum += (uint8_t)address; + bytes_read += 4; + count -= 2; + break; - case 2: - /* S2 - 24 bit address data record */ - sscanf(&lpsz_line[bytes_read], "%6" SCNx32, &address); - cal_checksum += (uint8_t)(address >> 16); - cal_checksum += (uint8_t)(address >> 8); - cal_checksum += (uint8_t)address; - bytes_read += 6; - count -= 3; - break; - - case 3: - /* S3 - 32 bit address data record */ - sscanf(&lpsz_line[bytes_read], "%8" SCNx32, &address); - cal_checksum += (uint8_t)(address >> 24); - cal_checksum += (uint8_t)(address >> 16); - cal_checksum += (uint8_t)(address >> 8); - cal_checksum += (uint8_t)address; - bytes_read += 8; - count -= 4; - break; + case 2: + /* S2 - 24 bit address data record */ + sscanf(&lpsz_line[bytes_read], "%6" SCNx32, &address); + cal_checksum += (uint8_t)(address >> 16); + cal_checksum += (uint8_t)(address >> 8); + cal_checksum += (uint8_t)address; + bytes_read += 6; + count -= 3; + break; + case 3: + /* S3 - 32 bit address data record */ + sscanf(&lpsz_line[bytes_read], "%8" SCNx32, &address); + cal_checksum += (uint8_t)(address >> 24); + cal_checksum += (uint8_t)(address >> 16); + cal_checksum += (uint8_t)(address >> 8); + cal_checksum += (uint8_t)address; + bytes_read += 8; + count -= 4; + break; } if (full_address != address) { diff --git a/src/target/mips32.c b/src/target/mips32.c index 5683a28b9..b8c61a5bf 100644 --- a/src/target/mips32.c +++ b/src/target/mips32.c @@ -1687,26 +1687,25 @@ COMMAND_HANDLER(mips32_handle_cp0_command) } switch (CMD_ARGC) { - case 0: /* No arg => print out all cp0 regs */ - retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask); - break; - case 1: /* 1 arg => get cp0 #reg/#sel value by name */ - retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask); - break; - case 2: /* 2 args => get cp0 reg/sel value or set value by name */ - tmp = *CMD_ARGV[0]; - if (isdigit(tmp)) /* starts from number then args are #reg and #sel */ - retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info); - else /* or set value by register name */ - retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info); - - break; - case 3: /* 3 args => set cp0 reg/sel value*/ - retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info); - break; - default: /* Other argc => err */ - retval = ERROR_COMMAND_SYNTAX_ERROR; - break; + case 0: /* No arg => print out all cp0 regs */ + retval = mips32_cp0_get_all_regs(CMD, ejtag_info, mips32->cp0_mask); + break; + case 1: /* 1 arg => get cp0 #reg/#sel value by name */ + retval = mips32_cp0_get_reg_by_name(CMD, ejtag_info, mips32->cp0_mask); + break; + case 2: /* 2 args => get cp0 reg/sel value or set value by name */ + tmp = *CMD_ARGV[0]; + if (isdigit(tmp)) /* starts from number then args are #reg and #sel */ + retval = mips32_cp0_get_reg_by_number(CMD, ejtag_info); + else /* or set value by register name */ + retval = mips32_cp0_set_reg_by_name(CMD, mips32, ejtag_info); + break; + case 3: /* 3 args => set cp0 reg/sel value*/ + retval = mips32_cp0_set_reg_by_number(CMD, mips32, ejtag_info); + break; + default: /* Other argc => err */ + retval = ERROR_COMMAND_SYNTAX_ERROR; + break; } return retval; @@ -2003,20 +2002,20 @@ COMMAND_HANDLER(mips32_handle_cpuinfo_command) uint32_t mmu_type = (config0 >> 7) & 7; /* MMU Type Info */ char *mmu; switch (mmu_type) { - case MIPS32_MMU_TLB: - mmu = "TLB"; + case MIPS32_MMU_TLB: + mmu = "TLB"; break; - case MIPS32_MMU_BAT: - mmu = "BAT"; + case MIPS32_MMU_BAT: + mmu = "BAT"; break; - case MIPS32_MMU_FIXED: - mmu = "FIXED"; + case MIPS32_MMU_FIXED: + mmu = "FIXED"; break; - case MIPS32_MMU_DUAL_VTLB_FTLB: - mmu = "DUAL VAR/FIXED"; + case MIPS32_MMU_DUAL_VTLB_FTLB: + mmu = "DUAL VAR/FIXED"; break; - default: - mmu = "Unknown"; + default: + mmu = "Unknown"; } command_print(CMD, "MMU Type: %s", mmu); @@ -2262,25 +2261,25 @@ COMMAND_HANDLER(mips32_handle_dsp_command) } switch (CMD_ARGC) { - case 0: - retval = mips32_dsp_get_all_regs(CMD, mips32); - break; - case 1: - retval = mips32_dsp_get_register(CMD, mips32); - break; - case 2: - tmp = *CMD_ARGV[0]; - if (isdigit(tmp)) { - command_print(CMD, "Error: invalid dsp command format"); - retval = ERROR_COMMAND_ARGUMENT_INVALID; - } else { - retval = mips32_dsp_set_register(CMD, mips32); - } - break; - default: - command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC); + case 0: + retval = mips32_dsp_get_all_regs(CMD, mips32); + break; + case 1: + retval = mips32_dsp_get_register(CMD, mips32); + break; + case 2: + tmp = *CMD_ARGV[0]; + if (isdigit(tmp)) { + command_print(CMD, "Error: invalid dsp command format"); retval = ERROR_COMMAND_ARGUMENT_INVALID; - break; + } else { + retval = mips32_dsp_set_register(CMD, mips32); + } + break; + default: + command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC); + retval = ERROR_COMMAND_ARGUMENT_INVALID; + break; } return retval; } diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c index beffbf51e..030a24a5c 100644 --- a/src/target/mips32_dmaacc.c +++ b/src/target/mips32_dmaacc.c @@ -186,18 +186,18 @@ begin_ejtag_dma_read_b: /* Handle the bigendian/littleendian */ switch (addr & 0x3) { - case 0: - *data = v & 0xff; - break; - case 1: - *data = (v >> 8) & 0xff; - break; - case 2: - *data = (v >> 16) & 0xff; - break; - case 3: - *data = (v >> 24) & 0xff; - break; + case 0: + *data = v & 0xff; + break; + case 1: + *data = (v >> 8) & 0xff; + break; + case 2: + *data = (v >> 16) & 0xff; + break; + case 3: + *data = (v >> 24) & 0xff; + break; } return ERROR_OK; @@ -341,12 +341,12 @@ begin_ejtag_dma_write_b: int mips32_dmaacc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, void *buf) { switch (size) { - case 1: - return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); - case 2: - return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); - case 4: - return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); + case 1: + return mips32_dmaacc_read_mem8(ejtag_info, addr, count, (uint8_t *)buf); + case 2: + return mips32_dmaacc_read_mem16(ejtag_info, addr, count, (uint16_t *)buf); + case 4: + return mips32_dmaacc_read_mem32(ejtag_info, addr, count, (uint32_t *)buf); } return ERROR_OK; @@ -397,12 +397,12 @@ static int mips32_dmaacc_read_mem8(struct mips_ejtag *ejtag_info, uint32_t addr, int mips32_dmaacc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size, int count, const void *buf) { switch (size) { - case 1: - return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf); - case 2: - return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf); - case 4: - return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf); + case 1: + return mips32_dmaacc_write_mem8(ejtag_info, addr, count, buf); + case 2: + return mips32_dmaacc_write_mem16(ejtag_info, addr, count, buf); + case 4: + return mips32_dmaacc_write_mem32(ejtag_info, addr, count, buf); } return ERROR_OK; diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c index ea90d6f83..9a22a5031 100644 --- a/src/target/mips32_pracc.c +++ b/src/target/mips32_pracc.c @@ -819,19 +819,19 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz mips32_cp0_read(ejtag_info, &conf, 16, 0); switch (KSEGX(addr)) { - case KUSEG: - cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; - break; - case KSEG0: - cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; - break; - case KSEG2: - case KSEG3: - cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; - break; - default: - /* what ? */ - break; + case KUSEG: + cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; + break; + case KSEG0: + cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; + break; + case KSEG2: + case KSEG3: + cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; + break; + default: + /* what ? */ + break; } /** @@ -1256,19 +1256,19 @@ static int mips32_pracc_fastdata_xfer_synchronize_cache(struct mips_ejtag *ejtag mips32_cp0_read(ejtag_info, &conf, 16, 0); switch (KSEGX(addr)) { - case KUSEG: - cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; - break; - case KSEG0: - cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; - break; - case KSEG2: - case KSEG3: - cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; - break; - default: - /* what ? */ - break; + case KUSEG: + cached = (conf & MIPS32_CONFIG0_KU_MASK) >> MIPS32_CONFIG0_KU_SHIFT; + break; + case KSEG0: + cached = (conf & MIPS32_CONFIG0_K0_MASK) >> MIPS32_CONFIG0_K0_SHIFT; + break; + case KSEG2: + case KSEG3: + cached = (conf & MIPS32_CONFIG0_K23_MASK) >> MIPS32_CONFIG0_K23_SHIFT; + break; + default: + /* what ? */ + break; } /** diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index ea27e0df3..750c53eba 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -342,18 +342,18 @@ void ejtag_main_print_imp(struct mips_ejtag *ejtag_info) EJTAG_IMP_HAS(EJTAG_IMP_MIPS64) ? " MIPS64" : " MIPS32"); switch (ejtag_info->ejtag_version) { - case EJTAG_VERSION_20: - ejtag_v20_print_imp(ejtag_info); - break; - case EJTAG_VERSION_25: - case EJTAG_VERSION_26: - case EJTAG_VERSION_31: - case EJTAG_VERSION_41: - case EJTAG_VERSION_51: - ejtag_v26_print_imp(ejtag_info); - break; - default: - break; + case EJTAG_VERSION_20: + ejtag_v20_print_imp(ejtag_info); + break; + case EJTAG_VERSION_25: + case EJTAG_VERSION_26: + case EJTAG_VERSION_31: + case EJTAG_VERSION_41: + case EJTAG_VERSION_51: + ejtag_v26_print_imp(ejtag_info); + break; + default: + break; } } @@ -369,27 +369,27 @@ int mips_ejtag_init(struct mips_ejtag *ejtag_info) ejtag_info->ejtag_version = ((ejtag_info->impcode >> 29) & 0x07); switch (ejtag_info->ejtag_version) { - case EJTAG_VERSION_20: - LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected"); - break; - case EJTAG_VERSION_25: - LOG_DEBUG("EJTAG: Version 2.5 Detected"); - break; - case EJTAG_VERSION_26: - LOG_DEBUG("EJTAG: Version 2.6 Detected"); - break; - case EJTAG_VERSION_31: - LOG_DEBUG("EJTAG: Version 3.1 Detected"); - break; - case EJTAG_VERSION_41: - LOG_DEBUG("EJTAG: Version 4.1 Detected"); - break; - case EJTAG_VERSION_51: - LOG_DEBUG("EJTAG: Version 5.1 Detected"); - break; - default: - LOG_DEBUG("EJTAG: Unknown Version Detected"); - break; + case EJTAG_VERSION_20: + LOG_DEBUG("EJTAG: Version 1 or 2.0 Detected"); + break; + case EJTAG_VERSION_25: + LOG_DEBUG("EJTAG: Version 2.5 Detected"); + break; + case EJTAG_VERSION_26: + LOG_DEBUG("EJTAG: Version 2.6 Detected"); + break; + case EJTAG_VERSION_31: + LOG_DEBUG("EJTAG: Version 3.1 Detected"); + break; + case EJTAG_VERSION_41: + LOG_DEBUG("EJTAG: Version 4.1 Detected"); + break; + case EJTAG_VERSION_51: + LOG_DEBUG("EJTAG: Version 5.1 Detected"); + break; + default: + LOG_DEBUG("EJTAG: Unknown Version Detected"); + break; } ejtag_main_print_imp(ejtag_info); diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c index 4379951a7..49658b735 100644 --- a/src/target/mips_m4k.c +++ b/src/target/mips_m4k.c @@ -893,17 +893,17 @@ static int mips_m4k_set_watchpoint(struct target *target, } switch (watchpoint->rw) { - case WPT_READ: - enable &= ~EJTAG_DBCN_NOLB; - break; - case WPT_WRITE: - enable &= ~EJTAG_DBCN_NOSB; - break; - case WPT_ACCESS: - enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB); - break; - default: - LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); + case WPT_READ: + enable &= ~EJTAG_DBCN_NOLB; + break; + case WPT_WRITE: + enable &= ~EJTAG_DBCN_NOSB; + break; + case WPT_ACCESS: + enable &= ~(EJTAG_DBCN_NOLB | EJTAG_DBCN_NOSB); + break; + default: + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } watchpoint_set(watchpoint, wp_num); diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c index 917b87200..99abcde11 100644 --- a/src/target/openrisc/jsp_server.c +++ b/src/target/openrisc/jsp_server.c @@ -118,49 +118,49 @@ static int jsp_input(struct connection *connection) buf_p = buffer; while (bytes_read) { switch (t_con->state) { - case TELNET_STATE_DATA: - if (*buf_p == 0xff) { - t_con->state = TELNET_STATE_IAC; - } else { - int out_len = 1; - int in_len; - unsigned char in_buffer[10]; - or1k_adv_jtag_jsp_xfer(jsp_service->jtag_info, - &out_len, buf_p, &in_len, - in_buffer); - if (in_len) - telnet_write(connection, in_buffer, in_len); - } + case TELNET_STATE_DATA: + if (*buf_p == 0xff) { + t_con->state = TELNET_STATE_IAC; + } else { + int out_len = 1; + int in_len; + unsigned char in_buffer[10]; + or1k_adv_jtag_jsp_xfer(jsp_service->jtag_info, + &out_len, buf_p, &in_len, + in_buffer); + if (in_len) + telnet_write(connection, in_buffer, in_len); + } + break; + case TELNET_STATE_IAC: + switch (*buf_p) { + case 0xfe: + t_con->state = TELNET_STATE_DONT; break; - case TELNET_STATE_IAC: - switch (*buf_p) { - case 0xfe: - t_con->state = TELNET_STATE_DONT; - break; - case 0xfd: - t_con->state = TELNET_STATE_DO; - break; - case 0xfc: - t_con->state = TELNET_STATE_WONT; - break; - case 0xfb: - t_con->state = TELNET_STATE_WILL; - break; - } + case 0xfd: + t_con->state = TELNET_STATE_DO; break; - case TELNET_STATE_SB: + case 0xfc: + t_con->state = TELNET_STATE_WONT; break; - case TELNET_STATE_SE: + case 0xfb: + t_con->state = TELNET_STATE_WILL; break; - case TELNET_STATE_WILL: - case TELNET_STATE_WONT: - case TELNET_STATE_DO: - case TELNET_STATE_DONT: - t_con->state = TELNET_STATE_DATA; - break; - default: - LOG_ERROR("unknown telnet state"); - exit(-1); + } + break; + case TELNET_STATE_SB: + break; + case TELNET_STATE_SE: + break; + case TELNET_STATE_WILL: + case TELNET_STATE_WONT: + case TELNET_STATE_DO: + case TELNET_STATE_DONT: + t_con->state = TELNET_STATE_DATA; + break; + default: + LOG_ERROR("unknown telnet state"); + exit(-1); } bytes_read--; diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c index 93016c66f..5f8ab1082 100644 --- a/src/target/semihosting_common.c +++ b/src/target/semihosting_common.c @@ -308,60 +308,60 @@ static char *semihosting_user_op_params; static const char *semihosting_opcode_to_str(const uint64_t opcode) { switch (opcode) { - case SEMIHOSTING_SYS_CLOSE: - return "CLOSE"; - case SEMIHOSTING_SYS_CLOCK: - return "CLOCK"; - case SEMIHOSTING_SYS_ELAPSED: - return "ELAPSED"; - case SEMIHOSTING_SYS_ERRNO: - return "ERRNO"; - case SEMIHOSTING_SYS_EXIT: - return "EXIT"; - case SEMIHOSTING_SYS_EXIT_EXTENDED: - return "EXIT_EXTENDED"; - case SEMIHOSTING_SYS_FLEN: - return "FLEN"; - case SEMIHOSTING_SYS_GET_CMDLINE: - return "GET_CMDLINE"; - case SEMIHOSTING_SYS_HEAPINFO: - return "HEAPINFO"; - case SEMIHOSTING_SYS_ISERROR: - return "ISERROR"; - case SEMIHOSTING_SYS_ISTTY: - return "ISTTY"; - case SEMIHOSTING_SYS_OPEN: - return "OPEN"; - case SEMIHOSTING_SYS_READ: - return "READ"; - case SEMIHOSTING_SYS_READC: - return "READC"; - case SEMIHOSTING_SYS_REMOVE: - return "REMOVE"; - case SEMIHOSTING_SYS_RENAME: - return "RENAME"; - case SEMIHOSTING_SYS_SEEK: - return "SEEK"; - case SEMIHOSTING_SYS_SYSTEM: - return "SYSTEM"; - case SEMIHOSTING_SYS_TICKFREQ: - return "TICKFREQ"; - case SEMIHOSTING_SYS_TIME: - return "TIME"; - case SEMIHOSTING_SYS_TMPNAM: - return "TMPNAM"; - case SEMIHOSTING_SYS_WRITE: - return "WRITE"; - case SEMIHOSTING_SYS_WRITEC: - return "WRITEC"; - case SEMIHOSTING_SYS_WRITE0: - return "WRITE0"; - case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X1FF: - return "USER_CMD"; - case SEMIHOSTING_ARM_RESERVED_START ... SEMIHOSTING_ARM_RESERVED_END: - return "ARM_RESERVED_CMD"; - default: - return ""; + case SEMIHOSTING_SYS_CLOSE: + return "CLOSE"; + case SEMIHOSTING_SYS_CLOCK: + return "CLOCK"; + case SEMIHOSTING_SYS_ELAPSED: + return "ELAPSED"; + case SEMIHOSTING_SYS_ERRNO: + return "ERRNO"; + case SEMIHOSTING_SYS_EXIT: + return "EXIT"; + case SEMIHOSTING_SYS_EXIT_EXTENDED: + return "EXIT_EXTENDED"; + case SEMIHOSTING_SYS_FLEN: + return "FLEN"; + case SEMIHOSTING_SYS_GET_CMDLINE: + return "GET_CMDLINE"; + case SEMIHOSTING_SYS_HEAPINFO: + return "HEAPINFO"; + case SEMIHOSTING_SYS_ISERROR: + return "ISERROR"; + case SEMIHOSTING_SYS_ISTTY: + return "ISTTY"; + case SEMIHOSTING_SYS_OPEN: + return "OPEN"; + case SEMIHOSTING_SYS_READ: + return "READ"; + case SEMIHOSTING_SYS_READC: + return "READC"; + case SEMIHOSTING_SYS_REMOVE: + return "REMOVE"; + case SEMIHOSTING_SYS_RENAME: + return "RENAME"; + case SEMIHOSTING_SYS_SEEK: + return "SEEK"; + case SEMIHOSTING_SYS_SYSTEM: + return "SYSTEM"; + case SEMIHOSTING_SYS_TICKFREQ: + return "TICKFREQ"; + case SEMIHOSTING_SYS_TIME: + return "TIME"; + case SEMIHOSTING_SYS_TMPNAM: + return "TMPNAM"; + case SEMIHOSTING_SYS_WRITE: + return "WRITE"; + case SEMIHOSTING_SYS_WRITEC: + return "WRITEC"; + case SEMIHOSTING_SYS_WRITE0: + return "WRITE0"; + case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X1FF: + return "USER_CMD"; + case SEMIHOSTING_ARM_RESERVED_START ... SEMIHOSTING_ARM_RESERVED_END: + return "ARM_RESERVED_CMD"; + default: + return ""; } } @@ -399,1240 +399,1239 @@ int semihosting_common(struct target *target) semihosting->param); switch (semihosting->op) { + case SEMIHOSTING_SYS_CLOCK: /* 0x10 */ + /* + * Returns the number of centiseconds (hundredths of a second) + * since the execution started. + * + * Values returned can be of limited use for some benchmarking + * purposes because of communication overhead or other + * agent-specific factors. For example, with a debug hardware + * unit the request is passed back to the host for execution. + * This can lead to unpredictable delays in transmission and + * process scheduling. + * + * Use this function to calculate time intervals, by calculating + * differences between intervals with and without the code + * sequence to be timed. + * + * Entry + * The PARAMETER REGISTER must contain 0. There are no other + * parameters. + * + * Return + * On exit, the RETURN REGISTER contains: + * - The number of centiseconds since some arbitrary start + * point, if the call is successful. + * - –1 if the call is not successful. For example, because + * of a communications error. + */ + { + clock_t delta = clock() - semihosting->setup_time; + + semihosting->result = delta / (CLOCKS_PER_SEC / 100); + } + break; + + case SEMIHOSTING_SYS_CLOSE: /* 0x02 */ + /* + * Closes a file on the host system. The handle must reference + * a file that was opened with SYS_OPEN. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field argument block: + * - field 1 Contains a handle for an open file. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the call is successful + * - –1 if the call is not successful. + */ + retval = semihosting_read_fields(target, 1, fields); + if (retval != ERROR_OK) + return retval; - case SEMIHOSTING_SYS_CLOCK: /* 0x10 */ - /* - * Returns the number of centiseconds (hundredths of a second) - * since the execution started. - * - * Values returned can be of limited use for some benchmarking - * purposes because of communication overhead or other - * agent-specific factors. For example, with a debug hardware - * unit the request is passed back to the host for execution. - * This can lead to unpredictable delays in transmission and - * process scheduling. - * - * Use this function to calculate time intervals, by calculating - * differences between intervals with and without the code - * sequence to be timed. - * - * Entry - * The PARAMETER REGISTER must contain 0. There are no other - * parameters. - * - * Return - * On exit, the RETURN REGISTER contains: - * - The number of centiseconds since some arbitrary start - * point, if the call is successful. - * - –1 if the call is not successful. For example, because - * of a communications error. - */ { - clock_t delta = clock() - semihosting->setup_time; - - semihosting->result = delta / (CLOCKS_PER_SEC / 100); + int fd = semihosting_get_field(target, 0, fields); + /* Do not allow to close OpenOCD's own standard streams */ + if (fd == 0 || fd == 1 || fd == 2) { + LOG_DEBUG("ignoring semihosting attempt to close %s", + (fd == 0) ? "stdin" : + (fd == 1) ? "stdout" : "stderr"); + /* Just pretend success */ + semihosting->result = 0; + break; + } + /* Close the descriptor */ + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "close"; + fileio_info->param_1 = fd; + } else { + semihosting->result = close(fd); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("close(%d)=%" PRId64, fd, semihosting->result); + } } break; - case SEMIHOSTING_SYS_CLOSE: /* 0x02 */ - /* - * Closes a file on the host system. The handle must reference - * a file that was opened with SYS_OPEN. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field argument block: - * - field 1 Contains a handle for an open file. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the call is successful - * - –1 if the call is not successful. - */ - retval = semihosting_read_fields(target, 1, fields); + case SEMIHOSTING_SYS_ERRNO: /* 0x13 */ + /* + * Returns the value of the C library errno variable that is + * associated with the semihosting implementation. The errno + * variable can be set by a number of C library semihosted + * functions, including: + * - SYS_REMOVE + * - SYS_OPEN + * - SYS_CLOSE + * - SYS_READ + * - SYS_WRITE + * - SYS_SEEK. + * + * Whether errno is set or not, and to what value, is entirely + * host-specific, except where the ISO C standard defines the + * behavior. + * + * Entry + * There are no parameters. The PARAMETER REGISTER must be 0. + * + * Return + * On exit, the RETURN REGISTER contains the value of the C + * library errno variable. + */ + semihosting->result = semihosting->sys_errno; + break; + + case SEMIHOSTING_SYS_EXIT: /* 0x18 */ + /* + * Note: SYS_EXIT was called angel_SWIreason_ReportException in + * previous versions of the documentation. + * + * An application calls this operation to report an exception + * to the debugger directly. The most common use is to report + * that execution has completed, using ADP_Stopped_ApplicationExit. + * + * Note: This semihosting operation provides no means for 32-bit + * callers to indicate an application exit with a specified exit + * code. Semihosting callers may prefer to check for the presence + * of the SH_EXT_EXTENDED_REPORT_EXCEPTION extension and use + * the SYS_REPORT_EXCEPTION_EXTENDED operation instead, if it + * is available. + * + * Entry (32-bit) + * On entry, the PARAMETER register is set to a reason code + * describing the cause of the trap. Not all semihosting client + * implementations will necessarily trap every corresponding + * event. Important reason codes are: + * + * - ADP_Stopped_ApplicationExit 0x20026 + * - ADP_Stopped_RunTimeErrorUnknown 0x20023 + * + * Entry (64-bit) + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 The exception type, which is one of the set of + * reason codes in the above tables. + * - field 2 A subcode, whose meaning depends on the reason + * code in field 1. + * In particular, if field 1 is ADP_Stopped_ApplicationExit + * then field 2 is an exit status code, as passed to the C + * standard library exit() function. A simulator receiving + * this request must notify a connected debugger, if present, + * and then exit with the specified status. + * + * Return + * No return is expected from these calls. However, it is + * possible for the debugger to request that the application + * continues by performing an RDI_Execute request or equivalent. + * In this case, execution continues with the registers as they + * were on entry to the operation, or as subsequently modified + * by the debugger. + */ + if (semihosting->word_size_bytes == 8) { + retval = semihosting_read_fields(target, 2, fields); if (retval != ERROR_OK) return retval; - { - int fd = semihosting_get_field(target, 0, fields); - /* Do not allow to close OpenOCD's own standard streams */ - if (fd == 0 || fd == 1 || fd == 2) { - LOG_DEBUG("ignoring semihosting attempt to close %s", - (fd == 0) ? "stdin" : - (fd == 1) ? "stdout" : "stderr"); - /* Just pretend success */ - semihosting->result = 0; - break; - } - /* Close the descriptor */ - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "close"; - fileio_info->param_1 = fd; - } else { - semihosting->result = close(fd); - if (semihosting->result == -1) - semihosting->sys_errno = errno; - LOG_DEBUG("close(%d)=%" PRId64, fd, semihosting->result); - } - } - break; + int type = semihosting_get_field(target, 0, fields); + int code = semihosting_get_field(target, 1, fields); - case SEMIHOSTING_SYS_ERRNO: /* 0x13 */ - /* - * Returns the value of the C library errno variable that is - * associated with the semihosting implementation. The errno - * variable can be set by a number of C library semihosted - * functions, including: - * - SYS_REMOVE - * - SYS_OPEN - * - SYS_CLOSE - * - SYS_READ - * - SYS_WRITE - * - SYS_SEEK. - * - * Whether errno is set or not, and to what value, is entirely - * host-specific, except where the ISO C standard defines the - * behavior. - * - * Entry - * There are no parameters. The PARAMETER REGISTER must be 0. - * - * Return - * On exit, the RETURN REGISTER contains the value of the C - * library errno variable. - */ - semihosting->result = semihosting->sys_errno; - break; + if (type == ADP_STOPPED_APPLICATION_EXIT) { + if (!gdb_get_actual_connections()) + exit(code); - case SEMIHOSTING_SYS_EXIT: /* 0x18 */ - /* - * Note: SYS_EXIT was called angel_SWIreason_ReportException in - * previous versions of the documentation. - * - * An application calls this operation to report an exception - * to the debugger directly. The most common use is to report - * that execution has completed, using ADP_Stopped_ApplicationExit. - * - * Note: This semihosting operation provides no means for 32-bit - * callers to indicate an application exit with a specified exit - * code. Semihosting callers may prefer to check for the presence - * of the SH_EXT_EXTENDED_REPORT_EXCEPTION extension and use - * the SYS_REPORT_EXCEPTION_EXTENDED operation instead, if it - * is available. - * - * Entry (32-bit) - * On entry, the PARAMETER register is set to a reason code - * describing the cause of the trap. Not all semihosting client - * implementations will necessarily trap every corresponding - * event. Important reason codes are: - * - * - ADP_Stopped_ApplicationExit 0x20026 - * - ADP_Stopped_RunTimeErrorUnknown 0x20023 - * - * Entry (64-bit) - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 The exception type, which is one of the set of - * reason codes in the above tables. - * - field 2 A subcode, whose meaning depends on the reason - * code in field 1. - * In particular, if field 1 is ADP_Stopped_ApplicationExit - * then field 2 is an exit status code, as passed to the C - * standard library exit() function. A simulator receiving - * this request must notify a connected debugger, if present, - * and then exit with the specified status. - * - * Return - * No return is expected from these calls. However, it is - * possible for the debugger to request that the application - * continues by performing an RDI_Execute request or equivalent. - * In this case, execution continues with the registers as they - * were on entry to the operation, or as subsequently modified - * by the debugger. - */ - if (semihosting->word_size_bytes == 8) { - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; - - int type = semihosting_get_field(target, 0, fields); - int code = semihosting_get_field(target, 1, fields); - - if (type == ADP_STOPPED_APPLICATION_EXIT) { - if (!gdb_get_actual_connections()) - exit(code); - - fprintf(stderr, - "semihosting: *** application exited with %d ***\n", - code); - } else { - fprintf(stderr, - "semihosting: application exception %#x\n", type); - } + fprintf(stderr, + "semihosting: *** application exited with %d ***\n", + code); } else { - if (semihosting->param == ADP_STOPPED_APPLICATION_EXIT) { - if (!gdb_get_actual_connections()) - exit(0); - - fprintf(stderr, - "semihosting: *** application exited normally ***\n"); - } else if (semihosting->param == ADP_STOPPED_RUN_TIME_ERROR) { - /* Chosen more or less arbitrarily to have a nicer message, - * otherwise all other return the same exit code 1. */ - if (!gdb_get_actual_connections()) - exit(1); - - fprintf(stderr, - "semihosting: *** application exited with error ***\n"); - } else { - if (!gdb_get_actual_connections()) - exit(1); - - fprintf(stderr, - "semihosting: application exception %#x\n", - (unsigned int)semihosting->param); - } + fprintf(stderr, + "semihosting: application exception %#x\n", type); } - if (!semihosting->has_resumable_exit) { - semihosting->is_resumable = false; - return target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } else { + if (semihosting->param == ADP_STOPPED_APPLICATION_EXIT) { + if (!gdb_get_actual_connections()) + exit(0); + + fprintf(stderr, + "semihosting: *** application exited normally ***\n"); + } else if (semihosting->param == ADP_STOPPED_RUN_TIME_ERROR) { + /* Chosen more or less arbitrarily to have a nicer message, + * otherwise all other return the same exit code 1. */ + if (!gdb_get_actual_connections()) + exit(1); + + fprintf(stderr, + "semihosting: *** application exited with error ***\n"); + } else { + if (!gdb_get_actual_connections()) + exit(1); + + fprintf(stderr, + "semihosting: application exception %#x\n", + (unsigned int)semihosting->param); } - break; + } + if (!semihosting->has_resumable_exit) { + semihosting->is_resumable = false; + return target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } + break; - case SEMIHOSTING_SYS_EXIT_EXTENDED: /* 0x20 */ - /* - * This operation is only supported if the semihosting extension - * SH_EXT_EXIT_EXTENDED is implemented. SH_EXT_EXIT_EXTENDED is - * reported using feature byte 0, bit 0. If this extension is - * supported, then the implementation provides a means to - * report a normal exit with a nonzero exit status in both 32-bit - * and 64-bit semihosting APIs. - * - * The implementation must provide the semihosting call - * SYS_EXIT_EXTENDED for both A64 and A32/T32 semihosting APIs. - * - * SYS_EXIT_EXTENDED is used by an application to report an - * exception or exit to the debugger directly. The most common - * use is to report that execution has completed, using - * ADP_Stopped_ApplicationExit. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 The exception type, which should be one of the set - * of reason codes that are documented for the SYS_EXIT - * (0x18) call. For example, ADP_Stopped_ApplicationExit. - * - field 2 A subcode, whose meaning depends on the reason - * code in field 1. In particular, if field 1 is - * ADP_Stopped_ApplicationExit then field 2 is an exit status - * code, as passed to the C standard library exit() function. - * A simulator receiving this request must notify a connected - * debugger, if present, and then exit with the specified status. - * - * Return - * No return is expected from these calls. - * - * For the A64 API, this call is identical to the behavior of - * the mandatory SYS_EXIT (0x18) call. If this extension is - * supported, then both calls must be implemented. - */ - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; + case SEMIHOSTING_SYS_EXIT_EXTENDED: /* 0x20 */ + /* + * This operation is only supported if the semihosting extension + * SH_EXT_EXIT_EXTENDED is implemented. SH_EXT_EXIT_EXTENDED is + * reported using feature byte 0, bit 0. If this extension is + * supported, then the implementation provides a means to + * report a normal exit with a nonzero exit status in both 32-bit + * and 64-bit semihosting APIs. + * + * The implementation must provide the semihosting call + * SYS_EXIT_EXTENDED for both A64 and A32/T32 semihosting APIs. + * + * SYS_EXIT_EXTENDED is used by an application to report an + * exception or exit to the debugger directly. The most common + * use is to report that execution has completed, using + * ADP_Stopped_ApplicationExit. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 The exception type, which should be one of the set + * of reason codes that are documented for the SYS_EXIT + * (0x18) call. For example, ADP_Stopped_ApplicationExit. + * - field 2 A subcode, whose meaning depends on the reason + * code in field 1. In particular, if field 1 is + * ADP_Stopped_ApplicationExit then field 2 is an exit status + * code, as passed to the C standard library exit() function. + * A simulator receiving this request must notify a connected + * debugger, if present, and then exit with the specified status. + * + * Return + * No return is expected from these calls. + * + * For the A64 API, this call is identical to the behavior of + * the mandatory SYS_EXIT (0x18) call. If this extension is + * supported, then both calls must be implemented. + */ + retval = semihosting_read_fields(target, 2, fields); + if (retval != ERROR_OK) + return retval; - { - int type = semihosting_get_field(target, 0, fields); - int code = semihosting_get_field(target, 1, fields); + { + int type = semihosting_get_field(target, 0, fields); + int code = semihosting_get_field(target, 1, fields); - if (type == ADP_STOPPED_APPLICATION_EXIT) { - if (!gdb_get_actual_connections()) - exit(code); + if (type == ADP_STOPPED_APPLICATION_EXIT) { + if (!gdb_get_actual_connections()) + exit(code); - fprintf(stderr, - "semihosting: *** application exited with %d ***\n", - code); - } else { - fprintf(stderr, "semihosting: exception %#x\n", type); - } + fprintf(stderr, + "semihosting: *** application exited with %d ***\n", + code); + } else { + fprintf(stderr, "semihosting: exception %#x\n", type); } - if (!semihosting->has_resumable_exit) { - semihosting->is_resumable = false; - return target_call_event_callbacks(target, TARGET_EVENT_HALTED); - } - break; + } + if (!semihosting->has_resumable_exit) { + semihosting->is_resumable = false; + return target_call_event_callbacks(target, TARGET_EVENT_HALTED); + } + break; - case SEMIHOSTING_SYS_FLEN: /* 0x0C */ - /* - * Returns the length of a specified file. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field argument block: - * - field 1 A handle for a previously opened, seekable file - * object. - * - * Return - * On exit, the RETURN REGISTER contains: - * - The current length of the file object, if the call is - * successful. - * - –1 if an error occurs. - */ - if (semihosting->is_fileio) { - semihosting->result = -1; - semihosting->sys_errno = EINVAL; - } - retval = semihosting_read_fields(target, 1, fields); - if (retval != ERROR_OK) - return retval; + case SEMIHOSTING_SYS_FLEN: /* 0x0C */ + /* + * Returns the length of a specified file. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field argument block: + * - field 1 A handle for a previously opened, seekable file + * object. + * + * Return + * On exit, the RETURN REGISTER contains: + * - The current length of the file object, if the call is + * successful. + * - –1 if an error occurs. + */ + if (semihosting->is_fileio) { + semihosting->result = -1; + semihosting->sys_errno = EINVAL; + } + retval = semihosting_read_fields(target, 1, fields); + if (retval != ERROR_OK) + return retval; - { - int fd = semihosting_get_field(target, 0, fields); - struct stat buf; - semihosting->result = fstat(fd, &buf); - if (semihosting->result == -1) { - semihosting->sys_errno = errno; - LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result); - break; - } + { + int fd = semihosting_get_field(target, 0, fields); + struct stat buf; + semihosting->result = fstat(fd, &buf); + if (semihosting->result == -1) { + semihosting->sys_errno = errno; LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result); - semihosting->result = buf.st_size; + break; } - break; + LOG_DEBUG("fstat(%d)=%" PRId64, fd, semihosting->result); + semihosting->result = buf.st_size; + } + break; - case SEMIHOSTING_SYS_GET_CMDLINE: /* 0x15 */ - /* - * Returns the command line that is used for the call to the - * executable, that is, argc and argv. - * - * Entry - * On entry, the PARAMETER REGISTER points to a two-field data - * block to be used for returning the command string and its length: - * - field 1 A pointer to a buffer of at least the size that is - * specified in field 2. - * - field 2 The length of the buffer in bytes. - * - * Return - * On exit: - * If the call is successful, then the RETURN REGISTER contains 0, - * the PARAMETER REGISTER is unchanged, and the data block is - * updated as follows: - * - field 1 A pointer to a null-terminated string of the command - * line. - * - field 2 The length of the string in bytes. - * If the call is not successful, then the RETURN REGISTER - * contains -1. - * - * Note: The semihosting implementation might impose limits on - * the maximum length of the string that can be transferred. - * However, the implementation must be able to support a - * command-line length of at least 80 bytes. - */ - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; + case SEMIHOSTING_SYS_GET_CMDLINE: /* 0x15 */ + /* + * Returns the command line that is used for the call to the + * executable, that is, argc and argv. + * + * Entry + * On entry, the PARAMETER REGISTER points to a two-field data + * block to be used for returning the command string and its length: + * - field 1 A pointer to a buffer of at least the size that is + * specified in field 2. + * - field 2 The length of the buffer in bytes. + * + * Return + * On exit: + * If the call is successful, then the RETURN REGISTER contains 0, + * the PARAMETER REGISTER is unchanged, and the data block is + * updated as follows: + * - field 1 A pointer to a null-terminated string of the command + * line. + * - field 2 The length of the string in bytes. + * If the call is not successful, then the RETURN REGISTER + * contains -1. + * + * Note: The semihosting implementation might impose limits on + * the maximum length of the string that can be transferred. + * However, the implementation must be able to support a + * command-line length of at least 80 bytes. + */ + retval = semihosting_read_fields(target, 2, fields); + if (retval != ERROR_OK) + return retval; - { - uint64_t addr = semihosting_get_field(target, 0, fields); - size_t size = semihosting_get_field(target, 1, fields); + { + uint64_t addr = semihosting_get_field(target, 0, fields); + size_t size = semihosting_get_field(target, 1, fields); - char *arg = semihosting->cmdline ? semihosting->cmdline : ""; - uint32_t len = strlen(arg) + 1; - if (len > size) { - semihosting->result = -1; - } else { - semihosting_set_field(target, len, 1, fields); - retval = target_write_buffer(target, addr, len, - (uint8_t *)arg); - if (retval != ERROR_OK) - return retval; - semihosting->result = 0; - - retval = semihosting_write_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; - } - LOG_DEBUG("SYS_GET_CMDLINE=[%s], %" PRId64, arg, semihosting->result); - } - break; - - case SEMIHOSTING_SYS_HEAPINFO: /* 0x16 */ - /* - * Returns the system stack and heap parameters. - * - * Entry - * On entry, the PARAMETER REGISTER contains the address of a - * pointer to a four-field data block. The contents of the data - * block are filled by the function. The following C-like - * pseudocode describes the layout of the block: - * struct block { - * void* heap_base; - * void* heap_limit; - * void* stack_base; - * void* stack_limit; - * }; - * - * Return - * On exit, the PARAMETER REGISTER is unchanged and the data - * block has been updated. - */ - retval = semihosting_read_fields(target, 1, fields); - if (retval != ERROR_OK) - return retval; - - { - uint64_t addr = semihosting_get_field(target, 0, fields); - /* tell the remote we have no idea */ - memset(fields, 0, 4 * semihosting->word_size_bytes); - retval = target_write_memory(target, addr, 4, - semihosting->word_size_bytes, - fields); + char *arg = semihosting->cmdline ? semihosting->cmdline : ""; + uint32_t len = strlen(arg) + 1; + if (len > size) { + semihosting->result = -1; + } else { + semihosting_set_field(target, len, 1, fields); + retval = target_write_buffer(target, addr, len, + (uint8_t *)arg); if (retval != ERROR_OK) return retval; semihosting->result = 0; - } - break; - case SEMIHOSTING_SYS_ISERROR: /* 0x08 */ - /* - * Determines whether the return code from another semihosting - * call is an error status or not. - * - * This call is passed a parameter block containing the error - * code to examine. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field data block: - * - field 1 The required status word to check. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the status field is not an error indication - * - A nonzero value if the status field is an error indication. - */ + retval = semihosting_write_fields(target, 2, fields); + if (retval != ERROR_OK) + return retval; + } + LOG_DEBUG("SYS_GET_CMDLINE=[%s], %" PRId64, arg, semihosting->result); + } + break; + + case SEMIHOSTING_SYS_HEAPINFO: /* 0x16 */ + /* + * Returns the system stack and heap parameters. + * + * Entry + * On entry, the PARAMETER REGISTER contains the address of a + * pointer to a four-field data block. The contents of the data + * block are filled by the function. The following C-like + * pseudocode describes the layout of the block: + * struct block { + * void* heap_base; + * void* heap_limit; + * void* stack_base; + * void* stack_limit; + * }; + * + * Return + * On exit, the PARAMETER REGISTER is unchanged and the data + * block has been updated. + */ + retval = semihosting_read_fields(target, 1, fields); + if (retval != ERROR_OK) + return retval; + + { + uint64_t addr = semihosting_get_field(target, 0, fields); + /* tell the remote we have no idea */ + memset(fields, 0, 4 * semihosting->word_size_bytes); + retval = target_write_memory(target, addr, 4, + semihosting->word_size_bytes, + fields); + if (retval != ERROR_OK) + return retval; + semihosting->result = 0; + } + break; + + case SEMIHOSTING_SYS_ISERROR: /* 0x08 */ + /* + * Determines whether the return code from another semihosting + * call is an error status or not. + * + * This call is passed a parameter block containing the error + * code to examine. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field data block: + * - field 1 The required status word to check. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the status field is not an error indication + * - A nonzero value if the status field is an error indication. + */ + retval = semihosting_read_fields(target, 1, fields); + if (retval != ERROR_OK) + return retval; + + uint64_t code = semihosting_get_field(target, 0, fields); + semihosting->result = (code != 0); + break; + + case SEMIHOSTING_SYS_ISTTY: /* 0x09 */ + /* + * Checks whether a file is connected to an interactive device. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * one-field argument block: + * field 1 A handle for a previously opened file object. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 1 if the handle identifies an interactive device. + * - 0 if the handle identifies a file. + * - A value other than 1 or 0 if an error occurs. + */ + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "isatty"; + fileio_info->param_1 = semihosting->param; + } else { retval = semihosting_read_fields(target, 1, fields); if (retval != ERROR_OK) return retval; + int fd = semihosting_get_field(target, 0, fields); + // isatty() on Windows may return any non-zero value if fd is a terminal + semihosting->result = isatty(fd) ? 1 : 0; + if (semihosting->result == 0) + semihosting->sys_errno = errno; + LOG_DEBUG("isatty(%d)=%" PRId64, fd, semihosting->result); + } + break; - uint64_t code = semihosting_get_field(target, 0, fields); - semihosting->result = (code != 0); - break; + case SEMIHOSTING_SYS_OPEN: /* 0x01 */ + /* + * Opens a file on the host system. + * + * The file path is specified either as relative to the current + * directory of the host process, or absolute, using the path + * conventions of the host operating system. + * + * Semihosting implementations must support opening the special + * path name :semihosting-features as part of the semihosting + * extensions reporting mechanism. + * + * ARM targets interpret the special path name :tt as meaning + * the console input stream, for an open-read or the console + * output stream, for an open-write. Opening these streams is + * performed as part of the standard startup code for those + * applications that reference the C stdio streams. The + * semihosting extension SH_EXT_STDOUT_STDERR allows the + * semihosting caller to open separate output streams + * corresponding to stdout and stderr. This extension is + * reported using feature byte 0, bit 1. Use SYS_OPEN with + * the special path name :semihosting-features to access the + * feature bits. + * + * If this extension is supported, the implementation must + * support the following additional semantics to SYS_OPEN: + * - If the special path name :tt is opened with an fopen + * mode requesting write access (w, wb, w+, or w+b), then + * this is a request to open stdout. + * - If the special path name :tt is opened with a mode + * requesting append access (a, ab, a+, or a+b), then this is + * a request to open stderr. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-field argument block: + * - field 1 A pointer to a null-terminated string containing + * a file or device name. + * - field 2 An integer that specifies the file opening mode. + * - field 3 An integer that gives the length of the string + * pointed to by field 1. + * + * The length does not include the terminating null character + * that must be present. + * + * Return + * On exit, the RETURN REGISTER contains: + * - A nonzero handle if the call is successful. + * - –1 if the call is not successful. + */ + retval = semihosting_read_fields(target, 3, fields); + if (retval != ERROR_OK) + return retval; - case SEMIHOSTING_SYS_ISTTY: /* 0x09 */ - /* - * Checks whether a file is connected to an interactive device. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * one-field argument block: - * field 1 A handle for a previously opened file object. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 1 if the handle identifies an interactive device. - * - 0 if the handle identifies a file. - * - A value other than 1 or 0 if an error occurs. - */ + { + uint64_t addr = semihosting_get_field(target, 0, fields); + uint32_t mode = semihosting_get_field(target, 1, fields); + size_t len = semihosting_get_field(target, 2, fields); + + if (mode > 11) { + semihosting->result = -1; + semihosting->sys_errno = EINVAL; + break; + } + size_t basedir_len = semihosting->basedir ? strlen(semihosting->basedir) : 0; + uint8_t *fn = malloc(basedir_len + len + 2); + if (!fn) { + semihosting->result = -1; + semihosting->sys_errno = ENOMEM; + } else { + if (basedir_len > 0) { + strcpy((char *)fn, semihosting->basedir); + if (fn[basedir_len - 1] != '/') + fn[basedir_len++] = '/'; + } + retval = target_read_memory(target, addr, 1, len, fn + basedir_len); + if (retval != ERROR_OK) { + free(fn); + return retval; + } + fn[basedir_len + len] = 0; + /* TODO: implement the :semihosting-features special file. + * */ + if (semihosting->is_fileio) { + if (strcmp((char *)fn, ":semihosting-features") == 0) { + semihosting->result = -1; + semihosting->sys_errno = EINVAL; + } else if (strcmp((char *)fn, ":tt") == 0) { + if (mode == 0) { + semihosting->result = 0; + } else if (mode == 4) { + semihosting->result = 1; + } else if (mode == 8) { + semihosting->result = 2; + } else { + semihosting->result = -1; + semihosting->sys_errno = EINVAL; + } + } else { + semihosting->hit_fileio = true; + fileio_info->identifier = "open"; + fileio_info->param_1 = addr; + fileio_info->param_2 = len; + fileio_info->param_3 = open_gdb_modeflags[mode]; + fileio_info->param_4 = 0644; + } + } else { + if (strcmp((char *)fn, ":tt") == 0) { + /* Mode is: + * - 0-3 ("r") for stdin, + * - 4-7 ("w") for stdout, + * - 8-11 ("a") for stderr */ + int fd; + if (mode < 4) { + fd = dup(STDIN_FILENO); + semihosting->stdin_fd = fd; + LOG_DEBUG("dup(STDIN)=%d", fd); + } else if (mode < 8) { + fd = dup(STDOUT_FILENO); + semihosting->stdout_fd = fd; + LOG_DEBUG("dup(STDOUT)=%d", fd); + } else { + fd = dup(STDERR_FILENO); + semihosting->stderr_fd = fd; + LOG_DEBUG("dup(STDERR)=%d", fd); + } + semihosting->result = fd; + if (fd == -1) + semihosting->sys_errno = errno; + } else { + /* cygwin requires the permission setting + * otherwise it will fail to reopen a previously + * written file */ + semihosting->result = open((char *)fn, + open_host_modeflags[mode], + 0644); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("open('%s')=%" PRId64, fn, semihosting->result); + } + } + free(fn); + } + } + break; + + case SEMIHOSTING_SYS_READ: /* 0x06 */ + /* + * Reads the contents of a file into a buffer. The file position + * is specified either: + * - Explicitly by a SYS_SEEK. + * - Implicitly one byte beyond the previous SYS_READ or + * SYS_WRITE request. + * + * The file position is at the start of the file when it is + * opened, and is lost when the file is closed. Perform the + * file operation as a single action whenever possible. For + * example, do not split a read of 16KB into four 4KB chunks + * unless there is no alternative. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-field data block: + * - field 1 Contains a handle for a file previously opened + * with SYS_OPEN. + * - field 2 Points to a buffer. + * - field 3 Contains the number of bytes to read to the buffer + * from the file. + * + * Return + * On exit, the RETURN REGISTER contains the number of bytes not + * filled in the buffer (buffer_length - bytes_read) as follows: + * - If the RETURN REGISTER is 0, the entire buffer was + * successfully filled. + * - If the RETURN REGISTER is the same as field 3, no bytes + * were read (EOF can be assumed). + * - If the RETURN REGISTER contains a value smaller than + * field 3, the read succeeded but the buffer was only partly + * filled. For interactive devices, this is the most common + * return value. + */ + retval = semihosting_read_fields(target, 3, fields); + if (retval != ERROR_OK) + return retval; + + { + int fd = semihosting_get_field(target, 0, fields); + uint64_t addr = semihosting_get_field(target, 1, fields); + size_t len = semihosting_get_field(target, 2, fields); if (semihosting->is_fileio) { semihosting->hit_fileio = true; - fileio_info->identifier = "isatty"; - fileio_info->param_1 = semihosting->param; + fileio_info->identifier = "read"; + fileio_info->param_1 = fd; + fileio_info->param_2 = addr; + fileio_info->param_3 = len; } else { - retval = semihosting_read_fields(target, 1, fields); - if (retval != ERROR_OK) - return retval; - int fd = semihosting_get_field(target, 0, fields); - // isatty() on Windows may return any non-zero value if fd is a terminal - semihosting->result = isatty(fd) ? 1 : 0; - if (semihosting->result == 0) - semihosting->sys_errno = errno; - LOG_DEBUG("isatty(%d)=%" PRId64, fd, semihosting->result); - } - break; - - case SEMIHOSTING_SYS_OPEN: /* 0x01 */ - /* - * Opens a file on the host system. - * - * The file path is specified either as relative to the current - * directory of the host process, or absolute, using the path - * conventions of the host operating system. - * - * Semihosting implementations must support opening the special - * path name :semihosting-features as part of the semihosting - * extensions reporting mechanism. - * - * ARM targets interpret the special path name :tt as meaning - * the console input stream, for an open-read or the console - * output stream, for an open-write. Opening these streams is - * performed as part of the standard startup code for those - * applications that reference the C stdio streams. The - * semihosting extension SH_EXT_STDOUT_STDERR allows the - * semihosting caller to open separate output streams - * corresponding to stdout and stderr. This extension is - * reported using feature byte 0, bit 1. Use SYS_OPEN with - * the special path name :semihosting-features to access the - * feature bits. - * - * If this extension is supported, the implementation must - * support the following additional semantics to SYS_OPEN: - * - If the special path name :tt is opened with an fopen - * mode requesting write access (w, wb, w+, or w+b), then - * this is a request to open stdout. - * - If the special path name :tt is opened with a mode - * requesting append access (a, ab, a+, or a+b), then this is - * a request to open stderr. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-field argument block: - * - field 1 A pointer to a null-terminated string containing - * a file or device name. - * - field 2 An integer that specifies the file opening mode. - * - field 3 An integer that gives the length of the string - * pointed to by field 1. - * - * The length does not include the terminating null character - * that must be present. - * - * Return - * On exit, the RETURN REGISTER contains: - * - A nonzero handle if the call is successful. - * - –1 if the call is not successful. - */ - retval = semihosting_read_fields(target, 3, fields); - if (retval != ERROR_OK) - return retval; - - { - uint64_t addr = semihosting_get_field(target, 0, fields); - uint32_t mode = semihosting_get_field(target, 1, fields); - size_t len = semihosting_get_field(target, 2, fields); - - if (mode > 11) { - semihosting->result = -1; - semihosting->sys_errno = EINVAL; - break; - } - size_t basedir_len = semihosting->basedir ? strlen(semihosting->basedir) : 0; - uint8_t *fn = malloc(basedir_len + len + 2); - if (!fn) { + uint8_t *buf = malloc(len); + if (!buf) { semihosting->result = -1; semihosting->sys_errno = ENOMEM; } else { - if (basedir_len > 0) { - strcpy((char *)fn, semihosting->basedir); - if (fn[basedir_len - 1] != '/') - fn[basedir_len++] = '/'; - } - retval = target_read_memory(target, addr, 1, len, fn + basedir_len); - if (retval != ERROR_OK) { - free(fn); - return retval; - } - fn[basedir_len + len] = 0; - /* TODO: implement the :semihosting-features special file. - * */ - if (semihosting->is_fileio) { - if (strcmp((char *)fn, ":semihosting-features") == 0) { - semihosting->result = -1; - semihosting->sys_errno = EINVAL; - } else if (strcmp((char *)fn, ":tt") == 0) { - if (mode == 0) { - semihosting->result = 0; - } else if (mode == 4) { - semihosting->result = 1; - } else if (mode == 8) { - semihosting->result = 2; - } else { - semihosting->result = -1; - semihosting->sys_errno = EINVAL; - } - } else { - semihosting->hit_fileio = true; - fileio_info->identifier = "open"; - fileio_info->param_1 = addr; - fileio_info->param_2 = len; - fileio_info->param_3 = open_gdb_modeflags[mode]; - fileio_info->param_4 = 0644; - } - } else { - if (strcmp((char *)fn, ":tt") == 0) { - /* Mode is: - * - 0-3 ("r") for stdin, - * - 4-7 ("w") for stdout, - * - 8-11 ("a") for stderr */ - int fd; - if (mode < 4) { - fd = dup(STDIN_FILENO); - semihosting->stdin_fd = fd; - LOG_DEBUG("dup(STDIN)=%d", fd); - } else if (mode < 8) { - fd = dup(STDOUT_FILENO); - semihosting->stdout_fd = fd; - LOG_DEBUG("dup(STDOUT)=%d", fd); - } else { - fd = dup(STDERR_FILENO); - semihosting->stderr_fd = fd; - LOG_DEBUG("dup(STDERR)=%d", fd); - } - semihosting->result = fd; - if (fd == -1) - semihosting->sys_errno = errno; - } else { - /* cygwin requires the permission setting - * otherwise it will fail to reopen a previously - * written file */ - semihosting->result = open((char *)fn, - open_host_modeflags[mode], - 0644); - if (semihosting->result == -1) - semihosting->sys_errno = errno; - LOG_DEBUG("open('%s')=%" PRId64, fn, semihosting->result); - } - } - free(fn); - } - } - break; - - case SEMIHOSTING_SYS_READ: /* 0x06 */ - /* - * Reads the contents of a file into a buffer. The file position - * is specified either: - * - Explicitly by a SYS_SEEK. - * - Implicitly one byte beyond the previous SYS_READ or - * SYS_WRITE request. - * - * The file position is at the start of the file when it is - * opened, and is lost when the file is closed. Perform the - * file operation as a single action whenever possible. For - * example, do not split a read of 16KB into four 4KB chunks - * unless there is no alternative. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-field data block: - * - field 1 Contains a handle for a file previously opened - * with SYS_OPEN. - * - field 2 Points to a buffer. - * - field 3 Contains the number of bytes to read to the buffer - * from the file. - * - * Return - * On exit, the RETURN REGISTER contains the number of bytes not - * filled in the buffer (buffer_length - bytes_read) as follows: - * - If the RETURN REGISTER is 0, the entire buffer was - * successfully filled. - * - If the RETURN REGISTER is the same as field 3, no bytes - * were read (EOF can be assumed). - * - If the RETURN REGISTER contains a value smaller than - * field 3, the read succeeded but the buffer was only partly - * filled. For interactive devices, this is the most common - * return value. - */ - retval = semihosting_read_fields(target, 3, fields); - if (retval != ERROR_OK) - return retval; - - { - int fd = semihosting_get_field(target, 0, fields); - uint64_t addr = semihosting_get_field(target, 1, fields); - size_t len = semihosting_get_field(target, 2, fields); - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "read"; - fileio_info->param_1 = fd; - fileio_info->param_2 = addr; - fileio_info->param_3 = len; - } else { - uint8_t *buf = malloc(len); - if (!buf) { - semihosting->result = -1; - semihosting->sys_errno = ENOMEM; - } else { - semihosting->result = semihosting_read(semihosting, fd, buf, len); - LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%" PRId64, - fd, - addr, - len, - semihosting->result); - if (semihosting->result >= 0) { - retval = target_write_buffer(target, addr, - semihosting->result, - buf); - if (retval != ERROR_OK) { - free(buf); - return retval; - } - /* the number of bytes NOT filled in */ - semihosting->result = len - - semihosting->result; - } - free(buf); - } - } - } - break; - - case SEMIHOSTING_SYS_READC: /* 0x07 */ - /* - * Reads a byte from the console. - * - * Entry - * The PARAMETER REGISTER must contain 0. There are no other - * parameters or values possible. - * - * Return - * On exit, the RETURN REGISTER contains the byte read from - * the console. - */ - if (semihosting->is_fileio) { - LOG_ERROR("SYS_READC not supported by semihosting fileio"); - return ERROR_FAIL; - } - semihosting->result = semihosting_getchar(semihosting, semihosting->stdin_fd); - LOG_DEBUG("getchar()=%" PRId64, semihosting->result); - break; - - case SEMIHOSTING_SYS_REMOVE: /* 0x0E */ - /* - * Deletes a specified file on the host filing system. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 Points to a null-terminated string that gives the - * path name of the file to be deleted. - * - field 2 The length of the string. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the delete is successful - * - A nonzero, host-specific error code if the delete fails. - */ - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; - - { - uint64_t addr = semihosting_get_field(target, 0, fields); - size_t len = semihosting_get_field(target, 1, fields); - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "unlink"; - fileio_info->param_1 = addr; - fileio_info->param_2 = len; - } else { - uint8_t *fn = malloc(len+1); - if (!fn) { - semihosting->result = -1; - semihosting->sys_errno = ENOMEM; - } else { - retval = target_read_memory(target, addr, 1, len, fn); - if (retval != ERROR_OK) { - free(fn); - return retval; - } - fn[len] = 0; - semihosting->result = remove((char *)fn); - if (semihosting->result == -1) - semihosting->sys_errno = errno; - LOG_DEBUG("remove('%s')=%" PRId64, fn, semihosting->result); - - free(fn); - } - } - } - break; - - case SEMIHOSTING_SYS_RENAME: /* 0x0F */ - /* - * Renames a specified file. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * four-field data block: - * - field 1 A pointer to the name of the old file. - * - field 2 The length of the old filename. - * - field 3 A pointer to the new filename. - * - field 4 The length of the new filename. Both strings are - * null-terminated. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the rename is successful. - * - A nonzero, host-specific error code if the rename fails. - */ - retval = semihosting_read_fields(target, 4, fields); - if (retval != ERROR_OK) - return retval; - - { - uint64_t addr1 = semihosting_get_field(target, 0, fields); - size_t len1 = semihosting_get_field(target, 1, fields); - uint64_t addr2 = semihosting_get_field(target, 2, fields); - size_t len2 = semihosting_get_field(target, 3, fields); - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "rename"; - fileio_info->param_1 = addr1; - fileio_info->param_2 = len1; - fileio_info->param_3 = addr2; - fileio_info->param_4 = len2; - } else { - uint8_t *fn1 = malloc(len1+1); - uint8_t *fn2 = malloc(len2+1); - if (!fn1 || !fn2) { - free(fn1); - free(fn2); - semihosting->result = -1; - semihosting->sys_errno = ENOMEM; - } else { - retval = target_read_memory(target, addr1, 1, len1, fn1); - if (retval != ERROR_OK) { - free(fn1); - free(fn2); - return retval; - } - retval = target_read_memory(target, addr2, 1, len2, fn2); - if (retval != ERROR_OK) { - free(fn1); - free(fn2); - return retval; - } - fn1[len1] = 0; - fn2[len2] = 0; - semihosting->result = rename((char *)fn1, (char *)fn2); - // rename() on Windows returns nonzero on error - if (semihosting->result != 0) - semihosting->sys_errno = errno; - LOG_DEBUG("rename('%s', '%s')=%" PRId64 " %d", fn1, fn2, semihosting->result, errno); - free(fn1); - free(fn2); - } - } - } - break; - - case SEMIHOSTING_SYS_SEEK: /* 0x0A */ - /* - * Seeks to a specified position in a file using an offset - * specified from the start of the file. The file is assumed - * to be a byte array and the offset is given in bytes. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field data block: - * - field 1 A handle for a seekable file object. - * - field 2 The absolute byte position to seek to. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the request is successful. - * - A negative value if the request is not successful. - * Use SYS_ERRNO to read the value of the host errno variable - * describing the error. - * - * Note: The effect of seeking outside the current extent of - * the file object is undefined. - */ - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; - - { - int fd = semihosting_get_field(target, 0, fields); - off_t pos = semihosting_get_field(target, 1, fields); - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "lseek"; - fileio_info->param_1 = fd; - fileio_info->param_2 = pos; - fileio_info->param_3 = SEEK_SET; - } else { - semihosting->result = lseek(fd, pos, SEEK_SET); - if (semihosting->result == -1) - semihosting->sys_errno = errno; - LOG_DEBUG("lseek(%d, %d)=%" PRId64, fd, (int)pos, semihosting->result); - if (semihosting->result == pos) - semihosting->result = 0; - } - } - break; - - case SEMIHOSTING_SYS_SYSTEM: /* 0x12 */ - /* - * Passes a command to the host command-line interpreter. - * This enables you to execute a system command such as dir, - * ls, or pwd. The terminal I/O is on the host, and is not - * visible to the target. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field argument block: - * - field 1 Points to a string to be passed to the host - * command-line interpreter. - * - field 2 The length of the string. - * - * Return - * On exit, the RETURN REGISTER contains the return status. - */ - - /* Provide SYS_SYSTEM functionality. Uses the - * libc system command, there may be a reason *NOT* - * to use this, but as I can't think of one, I - * implemented it this way. - */ - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) - return retval; - - { - uint64_t addr = semihosting_get_field(target, 0, fields); - size_t len = semihosting_get_field(target, 1, fields); - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "system"; - fileio_info->param_1 = addr; - fileio_info->param_2 = len; - } else { - uint8_t *cmd = malloc(len+1); - if (!cmd) { - semihosting->result = -1; - semihosting->sys_errno = ENOMEM; - } else { - retval = target_read_memory(target, - addr, - 1, - len, - cmd); - if (retval != ERROR_OK) { - free(cmd); - return retval; - } - cmd[len] = 0; - semihosting->result = system((const char *)cmd); - LOG_DEBUG("system('%s')=%" PRId64, cmd, semihosting->result); - - free(cmd); - } - } - } - break; - - case SEMIHOSTING_SYS_TIME: /* 0x11 */ - /* - * Returns the number of seconds since 00:00 January 1, 1970. - * This value is real-world time, regardless of any debug agent - * configuration. - * - * Entry - * There are no parameters. - * - * Return - * On exit, the RETURN REGISTER contains the number of seconds. - */ - semihosting->result = time(NULL); - break; - - case SEMIHOSTING_SYS_WRITE: /* 0x05 */ - /* - * Writes the contents of a buffer to a specified file at the - * current file position. The file position is specified either: - * - Explicitly, by a SYS_SEEK. - * - Implicitly as one byte beyond the previous SYS_READ or - * SYS_WRITE request. - * - * The file position is at the start of the file when the file - * is opened, and is lost when the file is closed. - * - * Perform the file operation as a single action whenever - * possible. For example, do not split a write of 16KB into - * four 4KB chunks unless there is no alternative. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * three-field data block: - * - field 1 Contains a handle for a file previously opened - * with SYS_OPEN. - * - field 2 Points to the memory containing the data to be written. - * - field 3 Contains the number of bytes to be written from - * the buffer to the file. - * - * Return - * On exit, the RETURN REGISTER contains: - * - 0 if the call is successful. - * - The number of bytes that are not written, if there is an error. - */ - retval = semihosting_read_fields(target, 3, fields); - if (retval != ERROR_OK) - return retval; - - { - int fd = semihosting_get_field(target, 0, fields); - uint64_t addr = semihosting_get_field(target, 1, fields); - size_t len = semihosting_get_field(target, 2, fields); - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "write"; - fileio_info->param_1 = fd; - fileio_info->param_2 = addr; - fileio_info->param_3 = len; - } else { - uint8_t *buf = malloc(len); - if (!buf) { - semihosting->result = -1; - semihosting->sys_errno = ENOMEM; - } else { - retval = target_read_buffer(target, addr, len, buf); + semihosting->result = semihosting_read(semihosting, fd, buf, len); + LOG_DEBUG("read(%d, 0x%" PRIx64 ", %zu)=%" PRId64, + fd, + addr, + len, + semihosting->result); + if (semihosting->result >= 0) { + retval = target_write_buffer(target, addr, + semihosting->result, + buf); if (retval != ERROR_OK) { free(buf); return retval; } - semihosting->result = semihosting_write(semihosting, fd, buf, len); - LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%" PRId64, - fd, - addr, - len, - semihosting->result); - if (semihosting->result >= 0) { - /* The number of bytes that are NOT written. - * */ - semihosting->result = len - - semihosting->result; - } - - free(buf); + /* the number of bytes NOT filled in */ + semihosting->result = len - + semihosting->result; } + free(buf); } } - break; + } + break; - case SEMIHOSTING_SYS_WRITEC: /* 0x03 */ - /* - * Writes a character byte, pointed to by the PARAMETER REGISTER, - * to the debug channel. When executed under a semihosting - * debugger, the character appears on the host debugger console. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to the - * character. - * - * Return - * None. The RETURN REGISTER is corrupted. - */ - if (semihosting->is_fileio) { - semihosting->hit_fileio = true; - fileio_info->identifier = "write"; - fileio_info->param_1 = 1; - fileio_info->param_2 = semihosting->param; - fileio_info->param_3 = 1; - } else { - uint64_t addr = semihosting->param; - unsigned char c; - retval = target_read_memory(target, addr, 1, 1, &c); - if (retval != ERROR_OK) - return retval; - semihosting_putchar(semihosting, semihosting->stdout_fd, c); - semihosting->result = 0; - } - break; - - case SEMIHOSTING_SYS_WRITE0: /* 0x04 */ - /* - * Writes a null-terminated string to the debug channel. - * When executed under a semihosting debugger, the characters - * appear on the host debugger console. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to the - * first byte of the string. - * - * Return - * None. The RETURN REGISTER is corrupted. - */ - if (semihosting->is_fileio) { - size_t count = 0; - uint64_t addr = semihosting->param; - for (;; addr++) { - unsigned char c; - retval = target_read_memory(target, addr, 1, 1, &c); - if (retval != ERROR_OK) - return retval; - if (c == '\0') - break; - count++; - } - semihosting->hit_fileio = true; - fileio_info->identifier = "write"; - fileio_info->param_1 = 1; - fileio_info->param_2 = semihosting->param; - fileio_info->param_3 = count; - } else { - uint64_t addr = semihosting->param; - do { - unsigned char c; - retval = target_read_memory(target, addr++, 1, 1, &c); - if (retval != ERROR_OK) - return retval; - if (!c) - break; - semihosting_putchar(semihosting, semihosting->stdout_fd, c); - } while (1); - semihosting->result = 0; - } - break; - - case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X107: - /** - * This is a user defined operation (while user cmds 0x100-0x1ff - * are possible, only 0x100-0x107 are currently implemented). - * - * Reads the user operation parameters from target, then fires the - * corresponding target event. When the target callbacks returned, - * cleans up the command parameter buffer. - * - * Entry - * On entry, the PARAMETER REGISTER contains a pointer to a - * two-field data block: - * - field 1 Contains a pointer to the bound command parameter - * string - * - field 2 Contains the command parameter string length - * - * Return - * On exit, the RETURN REGISTER contains the return status. - */ - if (semihosting->user_command_extension) { - retval = semihosting->user_command_extension(target); - if (retval != ERROR_NOT_IMPLEMENTED) - break; - /* If custom user command not handled, we are looking for the TCL handler */ - } - - assert(!semihosting_user_op_params); - retval = semihosting_read_fields(target, 2, fields); - if (retval != ERROR_OK) { - LOG_ERROR("Failed to read fields for user defined command" - " op=0x%x", semihosting->op); - return retval; - } - - uint64_t addr = semihosting_get_field(target, 0, fields); - - size_t len = semihosting_get_field(target, 1, fields); - if (len > SEMIHOSTING_MAX_TCL_COMMAND_FIELD_LENGTH) { - LOG_ERROR("The maximum length for user defined command " - "parameter is %u, received length is %zu (op=0x%x)", - SEMIHOSTING_MAX_TCL_COMMAND_FIELD_LENGTH, - len, - semihosting->op); - return ERROR_FAIL; - } - - semihosting_user_op_params = malloc(len + 1); - if (!semihosting_user_op_params) - return ERROR_FAIL; - semihosting_user_op_params[len] = 0; - - retval = target_read_buffer(target, addr, len, - (uint8_t *)(semihosting_user_op_params)); - if (retval != ERROR_OK) { - LOG_ERROR("Failed to read from target, semihosting op=0x%x (%s)", - semihosting->op, - semihosting_opcode_to_str(semihosting->op)); - free(semihosting_user_op_params); - semihosting_user_op_params = NULL; - return retval; - } - - target_handle_event(target, semihosting->op); - free(semihosting_user_op_params); - semihosting_user_op_params = NULL; - semihosting->result = 0; - break; - - case SEMIHOSTING_SYS_ELAPSED: /* 0x30 */ + case SEMIHOSTING_SYS_READC: /* 0x07 */ /* - * Returns the number of elapsed target ticks since execution - * started. - * Use SYS_TICKFREQ to determine the tick frequency. - * - * Entry (32-bit) - * On entry, the PARAMETER REGISTER points to a two-field data - * block to be used for returning the number of elapsed ticks: - * - field 1 The least significant field and is at the low address. - * - field 2 The most significant field and is at the high address. - * - * Entry (64-bit) - * On entry the PARAMETER REGISTER points to a one-field data - * block to be used for returning the number of elapsed ticks: - * - field 1 The number of elapsed ticks as a 64-bit value. - * - * Return - * On exit: - * - On success, the RETURN REGISTER contains 0, the PARAMETER - * REGISTER is unchanged, and the data block pointed to by the - * PARAMETER REGISTER is filled in with the number of elapsed - * ticks. - * - On failure, the RETURN REGISTER contains -1, and the - * PARAMETER REGISTER contains -1. - * - * Note: Some semihosting implementations might not support this - * semihosting operation, and they always return -1 in the - * RETURN REGISTER. - */ - - case SEMIHOSTING_SYS_TICKFREQ: /* 0x31 */ - /* - * Returns the tick frequency. + * Reads a byte from the console. * * Entry - * The PARAMETER REGISTER must contain 0 on entry to this routine. + * The PARAMETER REGISTER must contain 0. There are no other + * parameters or values possible. * * Return - * On exit, the RETURN REGISTER contains either: - * - The number of ticks per second. - * - –1 if the target does not know the value of one tick. - * - * Note: Some semihosting implementations might not support - * this semihosting operation, and they always return -1 in the - * RETURN REGISTER. + * On exit, the RETURN REGISTER contains the byte read from + * the console. */ + if (semihosting->is_fileio) { + LOG_ERROR("SYS_READC not supported by semihosting fileio"); + return ERROR_FAIL; + } + semihosting->result = semihosting_getchar(semihosting, semihosting->stdin_fd); + LOG_DEBUG("getchar()=%" PRId64, semihosting->result); + break; - case SEMIHOSTING_SYS_TMPNAM: /* 0x0D */ + case SEMIHOSTING_SYS_REMOVE: /* 0x0E */ /* - * Returns a temporary name for a file identified by a system - * file identifier. + * Deletes a specified file on the host filing system. * * Entry * On entry, the PARAMETER REGISTER contains a pointer to a - * three-word argument block: - * - field 1 A pointer to a buffer. - * - field 2 A target identifier for this filename. Its value - * must be an integer in the range 0-255. - * - field 3 Contains the length of the buffer. The length must - * be at least the value of L_tmpnam on the host system. + * two-field argument block: + * - field 1 Points to a null-terminated string that gives the + * path name of the file to be deleted. + * - field 2 The length of the string. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the delete is successful + * - A nonzero, host-specific error code if the delete fails. + */ + retval = semihosting_read_fields(target, 2, fields); + if (retval != ERROR_OK) + return retval; + + { + uint64_t addr = semihosting_get_field(target, 0, fields); + size_t len = semihosting_get_field(target, 1, fields); + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "unlink"; + fileio_info->param_1 = addr; + fileio_info->param_2 = len; + } else { + uint8_t *fn = malloc(len + 1); + if (!fn) { + semihosting->result = -1; + semihosting->sys_errno = ENOMEM; + } else { + retval = target_read_memory(target, addr, 1, len, fn); + if (retval != ERROR_OK) { + free(fn); + return retval; + } + fn[len] = 0; + semihosting->result = remove((char *)fn); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("remove('%s')=%" PRId64, fn, semihosting->result); + + free(fn); + } + } + } + break; + + case SEMIHOSTING_SYS_RENAME: /* 0x0F */ + /* + * Renames a specified file. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * four-field data block: + * - field 1 A pointer to the name of the old file. + * - field 2 The length of the old filename. + * - field 3 A pointer to the new filename. + * - field 4 The length of the new filename. Both strings are + * null-terminated. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the rename is successful. + * - A nonzero, host-specific error code if the rename fails. + */ + retval = semihosting_read_fields(target, 4, fields); + if (retval != ERROR_OK) + return retval; + + { + uint64_t addr1 = semihosting_get_field(target, 0, fields); + size_t len1 = semihosting_get_field(target, 1, fields); + uint64_t addr2 = semihosting_get_field(target, 2, fields); + size_t len2 = semihosting_get_field(target, 3, fields); + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "rename"; + fileio_info->param_1 = addr1; + fileio_info->param_2 = len1; + fileio_info->param_3 = addr2; + fileio_info->param_4 = len2; + } else { + uint8_t *fn1 = malloc(len1 + 1); + uint8_t *fn2 = malloc(len2 + 1); + if (!fn1 || !fn2) { + free(fn1); + free(fn2); + semihosting->result = -1; + semihosting->sys_errno = ENOMEM; + } else { + retval = target_read_memory(target, addr1, 1, len1, fn1); + if (retval != ERROR_OK) { + free(fn1); + free(fn2); + return retval; + } + retval = target_read_memory(target, addr2, 1, len2, fn2); + if (retval != ERROR_OK) { + free(fn1); + free(fn2); + return retval; + } + fn1[len1] = 0; + fn2[len2] = 0; + semihosting->result = rename((char *)fn1, (char *)fn2); + // rename() on Windows returns nonzero on error + if (semihosting->result != 0) + semihosting->sys_errno = errno; + LOG_DEBUG("rename('%s', '%s')=%" PRId64 " %d", fn1, fn2, semihosting->result, errno); + free(fn1); + free(fn2); + } + } + } + break; + + case SEMIHOSTING_SYS_SEEK: /* 0x0A */ + /* + * Seeks to a specified position in a file using an offset + * specified from the start of the file. The file is assumed + * to be a byte array and the offset is given in bytes. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field data block: + * - field 1 A handle for a seekable file object. + * - field 2 The absolute byte position to seek to. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the request is successful. + * - A negative value if the request is not successful. + * Use SYS_ERRNO to read the value of the host errno variable + * describing the error. + * + * Note: The effect of seeking outside the current extent of + * the file object is undefined. + */ + retval = semihosting_read_fields(target, 2, fields); + if (retval != ERROR_OK) + return retval; + + { + int fd = semihosting_get_field(target, 0, fields); + off_t pos = semihosting_get_field(target, 1, fields); + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "lseek"; + fileio_info->param_1 = fd; + fileio_info->param_2 = pos; + fileio_info->param_3 = SEEK_SET; + } else { + semihosting->result = lseek(fd, pos, SEEK_SET); + if (semihosting->result == -1) + semihosting->sys_errno = errno; + LOG_DEBUG("lseek(%d, %d)=%" PRId64, fd, (int)pos, semihosting->result); + if (semihosting->result == pos) + semihosting->result = 0; + } + } + break; + + case SEMIHOSTING_SYS_SYSTEM: /* 0x12 */ + /* + * Passes a command to the host command-line interpreter. + * This enables you to execute a system command such as dir, + * ls, or pwd. The terminal I/O is on the host, and is not + * visible to the target. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field argument block: + * - field 1 Points to a string to be passed to the host + * command-line interpreter. + * - field 2 The length of the string. + * + * Return + * On exit, the RETURN REGISTER contains the return status. + */ + + /* Provide SYS_SYSTEM functionality. Uses the + * libc system command, there may be a reason *NOT* + * to use this, but as I can't think of one, I + * implemented it this way. + */ + retval = semihosting_read_fields(target, 2, fields); + if (retval != ERROR_OK) + return retval; + + { + uint64_t addr = semihosting_get_field(target, 0, fields); + size_t len = semihosting_get_field(target, 1, fields); + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "system"; + fileio_info->param_1 = addr; + fileio_info->param_2 = len; + } else { + uint8_t *cmd = malloc(len + 1); + if (!cmd) { + semihosting->result = -1; + semihosting->sys_errno = ENOMEM; + } else { + retval = target_read_memory(target, + addr, + 1, + len, + cmd); + if (retval != ERROR_OK) { + free(cmd); + return retval; + } + cmd[len] = 0; + semihosting->result = system((const char *)cmd); + LOG_DEBUG("system('%s')=%" PRId64, cmd, semihosting->result); + + free(cmd); + } + } + } + break; + + case SEMIHOSTING_SYS_TIME: /* 0x11 */ + /* + * Returns the number of seconds since 00:00 January 1, 1970. + * This value is real-world time, regardless of any debug agent + * configuration. + * + * Entry + * There are no parameters. + * + * Return + * On exit, the RETURN REGISTER contains the number of seconds. + */ + semihosting->result = time(NULL); + break; + + case SEMIHOSTING_SYS_WRITE: /* 0x05 */ + /* + * Writes the contents of a buffer to a specified file at the + * current file position. The file position is specified either: + * - Explicitly, by a SYS_SEEK. + * - Implicitly as one byte beyond the previous SYS_READ or + * SYS_WRITE request. + * + * The file position is at the start of the file when the file + * is opened, and is lost when the file is closed. + * + * Perform the file operation as a single action whenever + * possible. For example, do not split a write of 16KB into + * four 4KB chunks unless there is no alternative. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-field data block: + * - field 1 Contains a handle for a file previously opened + * with SYS_OPEN. + * - field 2 Points to the memory containing the data to be written. + * - field 3 Contains the number of bytes to be written from + * the buffer to the file. * * Return * On exit, the RETURN REGISTER contains: * - 0 if the call is successful. - * - –1 if an error occurs. - * - * The buffer pointed to by the PARAMETER REGISTER contains - * the filename, prefixed with a suitable directory name. - * If you use the same target identifier again, the same - * filename is returned. - * - * Note: The returned string must be null-terminated. + * - The number of bytes that are not written, if there is an error. */ + retval = semihosting_read_fields(target, 3, fields); + if (retval != ERROR_OK) + return retval; - default: - fprintf(stderr, "semihosting: unsupported call %#x\n", - (unsigned int)semihosting->op); - semihosting->result = -1; - semihosting->sys_errno = ENOTSUP; + { + int fd = semihosting_get_field(target, 0, fields); + uint64_t addr = semihosting_get_field(target, 1, fields); + size_t len = semihosting_get_field(target, 2, fields); + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "write"; + fileio_info->param_1 = fd; + fileio_info->param_2 = addr; + fileio_info->param_3 = len; + } else { + uint8_t *buf = malloc(len); + if (!buf) { + semihosting->result = -1; + semihosting->sys_errno = ENOMEM; + } else { + retval = target_read_buffer(target, addr, len, buf); + if (retval != ERROR_OK) { + free(buf); + return retval; + } + semihosting->result = semihosting_write(semihosting, fd, buf, len); + LOG_DEBUG("write(%d, 0x%" PRIx64 ", %zu)=%" PRId64, + fd, + addr, + len, + semihosting->result); + if (semihosting->result >= 0) { + /* The number of bytes that are NOT written. + * */ + semihosting->result = len - + semihosting->result; + } + + free(buf); + } + } + } + break; + + case SEMIHOSTING_SYS_WRITEC: /* 0x03 */ + /* + * Writes a character byte, pointed to by the PARAMETER REGISTER, + * to the debug channel. When executed under a semihosting + * debugger, the character appears on the host debugger console. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to the + * character. + * + * Return + * None. The RETURN REGISTER is corrupted. + */ + if (semihosting->is_fileio) { + semihosting->hit_fileio = true; + fileio_info->identifier = "write"; + fileio_info->param_1 = 1; + fileio_info->param_2 = semihosting->param; + fileio_info->param_3 = 1; + } else { + uint64_t addr = semihosting->param; + unsigned char c; + retval = target_read_memory(target, addr, 1, 1, &c); + if (retval != ERROR_OK) + return retval; + semihosting_putchar(semihosting, semihosting->stdout_fd, c); + semihosting->result = 0; + } + break; + + case SEMIHOSTING_SYS_WRITE0: /* 0x04 */ + /* + * Writes a null-terminated string to the debug channel. + * When executed under a semihosting debugger, the characters + * appear on the host debugger console. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to the + * first byte of the string. + * + * Return + * None. The RETURN REGISTER is corrupted. + */ + if (semihosting->is_fileio) { + size_t count = 0; + uint64_t addr = semihosting->param; + for (;; addr++) { + unsigned char c; + retval = target_read_memory(target, addr, 1, 1, &c); + if (retval != ERROR_OK) + return retval; + if (c == '\0') + break; + count++; + } + semihosting->hit_fileio = true; + fileio_info->identifier = "write"; + fileio_info->param_1 = 1; + fileio_info->param_2 = semihosting->param; + fileio_info->param_3 = count; + } else { + uint64_t addr = semihosting->param; + do { + unsigned char c; + retval = target_read_memory(target, addr++, 1, 1, &c); + if (retval != ERROR_OK) + return retval; + if (!c) + break; + semihosting_putchar(semihosting, semihosting->stdout_fd, c); + } while (1); + semihosting->result = 0; + } + break; + + case SEMIHOSTING_USER_CMD_0X100 ... SEMIHOSTING_USER_CMD_0X107: + /** + * This is a user defined operation (while user cmds 0x100-0x1ff + * are possible, only 0x100-0x107 are currently implemented). + * + * Reads the user operation parameters from target, then fires the + * corresponding target event. When the target callbacks returned, + * cleans up the command parameter buffer. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * two-field data block: + * - field 1 Contains a pointer to the bound command parameter + * string + * - field 2 Contains the command parameter string length + * + * Return + * On exit, the RETURN REGISTER contains the return status. + */ + if (semihosting->user_command_extension) { + retval = semihosting->user_command_extension(target); + if (retval != ERROR_NOT_IMPLEMENTED) + break; + /* If custom user command not handled, we are looking for the TCL handler */ + } + + assert(!semihosting_user_op_params); + retval = semihosting_read_fields(target, 2, fields); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read fields for user defined command" + " op=0x%x", semihosting->op); + return retval; + } + + uint64_t addr = semihosting_get_field(target, 0, fields); + + size_t len = semihosting_get_field(target, 1, fields); + if (len > SEMIHOSTING_MAX_TCL_COMMAND_FIELD_LENGTH) { + LOG_ERROR("The maximum length for user defined command " + "parameter is %u, received length is %zu (op=0x%x)", + SEMIHOSTING_MAX_TCL_COMMAND_FIELD_LENGTH, + len, + semihosting->op); + return ERROR_FAIL; + } + + semihosting_user_op_params = malloc(len + 1); + if (!semihosting_user_op_params) + return ERROR_FAIL; + semihosting_user_op_params[len] = 0; + + retval = target_read_buffer(target, addr, len, + (uint8_t *)(semihosting_user_op_params)); + if (retval != ERROR_OK) { + LOG_ERROR("Failed to read from target, semihosting op=0x%x (%s)", + semihosting->op, + semihosting_opcode_to_str(semihosting->op)); + free(semihosting_user_op_params); + semihosting_user_op_params = NULL; + return retval; + } + + target_handle_event(target, semihosting->op); + free(semihosting_user_op_params); + semihosting_user_op_params = NULL; + semihosting->result = 0; + break; + + case SEMIHOSTING_SYS_ELAPSED: /* 0x30 */ + /* + * Returns the number of elapsed target ticks since execution + * started. + * Use SYS_TICKFREQ to determine the tick frequency. + * + * Entry (32-bit) + * On entry, the PARAMETER REGISTER points to a two-field data + * block to be used for returning the number of elapsed ticks: + * - field 1 The least significant field and is at the low address. + * - field 2 The most significant field and is at the high address. + * + * Entry (64-bit) + * On entry the PARAMETER REGISTER points to a one-field data + * block to be used for returning the number of elapsed ticks: + * - field 1 The number of elapsed ticks as a 64-bit value. + * + * Return + * On exit: + * - On success, the RETURN REGISTER contains 0, the PARAMETER + * REGISTER is unchanged, and the data block pointed to by the + * PARAMETER REGISTER is filled in with the number of elapsed + * ticks. + * - On failure, the RETURN REGISTER contains -1, and the + * PARAMETER REGISTER contains -1. + * + * Note: Some semihosting implementations might not support this + * semihosting operation, and they always return -1 in the + * RETURN REGISTER. + */ + + case SEMIHOSTING_SYS_TICKFREQ: /* 0x31 */ + /* + * Returns the tick frequency. + * + * Entry + * The PARAMETER REGISTER must contain 0 on entry to this routine. + * + * Return + * On exit, the RETURN REGISTER contains either: + * - The number of ticks per second. + * - –1 if the target does not know the value of one tick. + * + * Note: Some semihosting implementations might not support + * this semihosting operation, and they always return -1 in the + * RETURN REGISTER. + */ + + case SEMIHOSTING_SYS_TMPNAM: /* 0x0D */ + /* + * Returns a temporary name for a file identified by a system + * file identifier. + * + * Entry + * On entry, the PARAMETER REGISTER contains a pointer to a + * three-word argument block: + * - field 1 A pointer to a buffer. + * - field 2 A target identifier for this filename. Its value + * must be an integer in the range 0-255. + * - field 3 Contains the length of the buffer. The length must + * be at least the value of L_tmpnam on the host system. + * + * Return + * On exit, the RETURN REGISTER contains: + * - 0 if the call is successful. + * - –1 if an error occurs. + * + * The buffer pointed to by the PARAMETER REGISTER contains + * the filename, prefixed with a suitable directory name. + * If you use the same target identifier again, the same + * filename is returned. + * + * Note: The returned string must be null-terminated. + */ + + default: + fprintf(stderr, "semihosting: unsupported call %#x\n", + (unsigned int)semihosting->op); + semihosting->result = -1; + semihosting->sys_errno = ENOTSUP; } if (!semihosting->hit_fileio) { @@ -1686,18 +1685,18 @@ static int semihosting_common_fileio_end(struct target *target, int result, * below: */ switch (semihosting->op) { - case SEMIHOSTING_SYS_WRITE: /* 0x05 */ - case SEMIHOSTING_SYS_READ: /* 0x06 */ - if (result < 0) - semihosting->result = fileio_info->param_3; /* Zero bytes read/written. */ - else - semihosting->result = (int64_t)fileio_info->param_3 - result; - break; + case SEMIHOSTING_SYS_WRITE: /* 0x05 */ + case SEMIHOSTING_SYS_READ: /* 0x06 */ + if (result < 0) + semihosting->result = fileio_info->param_3; /* Zero bytes read/written. */ + else + semihosting->result = (int64_t)fileio_info->param_3 - result; + break; - case SEMIHOSTING_SYS_SEEK: /* 0x0a */ - if (result > 0) - semihosting->result = 0; - break; + case SEMIHOSTING_SYS_SEEK: /* 0x0a */ + if (result > 0) + semihosting->result = 0; + break; } bool fileio_failed = false; diff --git a/src/target/stm8.c b/src/target/stm8.c index bcca71caf..1fc028b4d 100644 --- a/src/target/stm8.c +++ b/src/target/stm8.c @@ -704,19 +704,19 @@ static int stm8_write_flash(struct target *target, enum mem_type type, int res; switch (type) { - case (FLASH): - stm8_unlock_flash(target); - break; - case (EEPROM): - stm8_unlock_eeprom(target); - break; - case (OPTION): - stm8_unlock_eeprom(target); - opt = OPT; - break; - default: - LOG_ERROR("BUG: wrong mem_type %d", type); - assert(0); + case (FLASH): + stm8_unlock_flash(target); + break; + case (EEPROM): + stm8_unlock_eeprom(target); + break; + case (OPTION): + stm8_unlock_eeprom(target); + opt = OPT; + break; + default: + LOG_ERROR("BUG: wrong mem_type %d", type); + assert(0); } if (size == 2) { @@ -1601,17 +1601,17 @@ static int stm8_set_watchpoint(struct target *target, enum hw_break_type enable = 0; switch (watchpoint->rw) { - case WPT_READ: - enable = HWBRK_RD; - break; - case WPT_WRITE: - enable = HWBRK_WR; - break; - case WPT_ACCESS: - enable = HWBRK_ACC; - break; - default: - LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); + case WPT_READ: + enable = HWBRK_RD; + break; + case WPT_WRITE: + enable = HWBRK_WR; + break; + case WPT_ACCESS: + enable = HWBRK_ACC; + break; + default: + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } comparator_list[wp_num].used = true; diff --git a/src/target/target.c b/src/target/target.c index ca9b90133..1bdbee19a 100644 --- a/src/target/target.c +++ b/src/target/target.c @@ -3561,20 +3561,20 @@ COMMAND_HANDLER(handle_mw_command) struct target *target = get_current_target(CMD_CTX); unsigned int wordsize; switch (CMD_NAME[2]) { - case 'd': - wordsize = 8; - break; - case 'w': - wordsize = 4; - break; - case 'h': - wordsize = 2; - break; - case 'b': - wordsize = 1; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'd': + wordsize = 8; + break; + case 'w': + wordsize = 4; + break; + case 'h': + wordsize = 2; + break; + case 'b': + wordsize = 1; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return target_fill_mem(target, address, fn, wordsize, value, count); @@ -3996,39 +3996,39 @@ COMMAND_HANDLER(handle_bp_command) int hw = BKPT_SOFT; switch (CMD_ARGC) { - case 0: - return handle_bp_command_list(CMD); + case 0: + return handle_bp_command_list(CMD); - case 2: - asid = 0; - COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); - return handle_bp_command_set(CMD, addr, asid, length, hw); + case 2: + asid = 0; + COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); + return handle_bp_command_set(CMD, addr, asid, length, hw); - case 3: - if (strcmp(CMD_ARGV[2], "hw") == 0) { - hw = BKPT_HARD; - COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); - asid = 0; - return handle_bp_command_set(CMD, addr, asid, length, hw); - } else if (strcmp(CMD_ARGV[2], "hw_ctx") == 0) { - hw = BKPT_HARD; - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], asid); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); - addr = 0; - return handle_bp_command_set(CMD, addr, asid, length, hw); - } - /* fallthrough */ - case 4: + case 3: + if (strcmp(CMD_ARGV[2], "hw") == 0) { hw = BKPT_HARD; COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], asid); - COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], length); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); + asid = 0; return handle_bp_command_set(CMD, addr, asid, length, hw); + } else if (strcmp(CMD_ARGV[2], "hw_ctx") == 0) { + hw = BKPT_HARD; + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], asid); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], length); + addr = 0; + return handle_bp_command_set(CMD, addr, asid, length, hw); + } + /* fallthrough */ + case 4: + hw = BKPT_HARD; + COMMAND_PARSE_ADDRESS(CMD_ARGV[0], addr); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], asid); + COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], length); + return handle_bp_command_set(CMD, addr, asid, length, hw); - default: - return ERROR_COMMAND_SYNTAX_ERROR; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } } @@ -6785,25 +6785,25 @@ static int target_register_user_commands(struct command_context *cmd_ctx) const char *target_debug_reason_str(enum target_debug_reason reason) { switch (reason) { - case DBG_REASON_DBGRQ: - return "DBGRQ"; - case DBG_REASON_BREAKPOINT: - return "BREAKPOINT"; - case DBG_REASON_WATCHPOINT: - return "WATCHPOINT"; - case DBG_REASON_WPTANDBKPT: - return "WPTANDBKPT"; - case DBG_REASON_SINGLESTEP: - return "SINGLESTEP"; - case DBG_REASON_NOTHALTED: - return "NOTHALTED"; - case DBG_REASON_EXIT: - return "EXIT"; - case DBG_REASON_EXC_CATCH: - return "EXC_CATCH"; - case DBG_REASON_UNDEFINED: - return "UNDEFINED"; - default: - return "UNKNOWN!"; + case DBG_REASON_DBGRQ: + return "DBGRQ"; + case DBG_REASON_BREAKPOINT: + return "BREAKPOINT"; + case DBG_REASON_WATCHPOINT: + return "WATCHPOINT"; + case DBG_REASON_WPTANDBKPT: + return "WPTANDBKPT"; + case DBG_REASON_SINGLESTEP: + return "SINGLESTEP"; + case DBG_REASON_NOTHALTED: + return "NOTHALTED"; + case DBG_REASON_EXIT: + return "EXIT"; + case DBG_REASON_EXC_CATCH: + return "EXC_CATCH"; + case DBG_REASON_UNDEFINED: + return "UNDEFINED"; + default: + return "UNKNOWN!"; } } diff --git a/src/target/target_request.c b/src/target/target_request.c index 8d51dc3d6..11586a696 100644 --- a/src/target/target_request.c +++ b/src/target/target_request.c @@ -74,15 +74,15 @@ static int target_hexmsg(struct target *target, int size, uint32_t length) line_len = 0; for (i = 0; i < length; i++) { switch (size) { - case 4: - line_len += snprintf(line + line_len, 128 - line_len, "%8.8" PRIx32 " ", le_to_h_u32(data + (4*i))); - break; - case 2: - line_len += snprintf(line + line_len, 128 - line_len, "%4.4x ", le_to_h_u16(data + (2*i))); - break; - case 1: - line_len += snprintf(line + line_len, 128 - line_len, "%2.2x ", data[i]); - break; + case 4: + line_len += snprintf(line + line_len, 128 - line_len, "%8.8" PRIx32 " ", le_to_h_u32(data + (4 * i))); + break; + case 2: + line_len += snprintf(line + line_len, 128 - line_len, "%4.4x ", le_to_h_u16(data + (2 * i))); + break; + case 1: + line_len += snprintf(line + line_len, 128 - line_len, "%2.2x ", data[i]); + break; } if ((i%8 == 7) || (i == length - 1)) { @@ -120,24 +120,24 @@ int target_request(struct target *target, uint32_t request) } switch (target_req_cmd) { - case TARGET_REQ_TRACEMSG: - trace_point(target, (request & 0xffffff00) >> 8); - break; - case TARGET_REQ_DEBUGMSG: - if (((request & 0xff00) >> 8) == 0) - target_asciimsg(target, (request & 0xffff0000) >> 16); - else - target_hexmsg(target, (request & 0xff00) >> 8, (request & 0xffff0000) >> 16); - break; - case TARGET_REQ_DEBUGCHAR: - target_charmsg(target, (request & 0x00ff0000) >> 16); - break; -/* case TARGET_REQ_SEMIHOSTING: - * break; + case TARGET_REQ_TRACEMSG: + trace_point(target, (request & 0xffffff00) >> 8); + break; + case TARGET_REQ_DEBUGMSG: + if (((request & 0xff00) >> 8) == 0) + target_asciimsg(target, (request & 0xffff0000) >> 16); + else + target_hexmsg(target, (request & 0xff00) >> 8, (request & 0xffff0000) >> 16); + break; + case TARGET_REQ_DEBUGCHAR: + target_charmsg(target, (request & 0x00ff0000) >> 16); + break; +/* case TARGET_REQ_SEMIHOSTING: + * break; */ - default: - LOG_ERROR("unknown target request: %2.2x", target_req_cmd); - break; + default: + LOG_ERROR("unknown target request: %2.2x", target_req_cmd); + break; } return ERROR_OK; diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c index a5df8b9e9..8ad9d00fe 100644 --- a/src/target/x86_32_common.c +++ b/src/target/x86_32_common.c @@ -331,27 +331,27 @@ static int read_mem(struct target *t, uint32_t size, } switch (size) { - case BYTE: - if (use32) - retval = x86_32->submit_instruction(t, MEMRDB32); - else - retval = x86_32->submit_instruction(t, MEMRDB16); - break; - case WORD: - if (use32) - retval = x86_32->submit_instruction(t, MEMRDH32); - else - retval = x86_32->submit_instruction(t, MEMRDH16); - break; - case DWORD: - if (use32) - retval = x86_32->submit_instruction(t, MEMRDW32); - else - retval = x86_32->submit_instruction(t, MEMRDW16); - break; - default: - LOG_ERROR("%s invalid read mem size", __func__); - break; + case BYTE: + if (use32) + retval = x86_32->submit_instruction(t, MEMRDB32); + else + retval = x86_32->submit_instruction(t, MEMRDB16); + break; + case WORD: + if (use32) + retval = x86_32->submit_instruction(t, MEMRDH32); + else + retval = x86_32->submit_instruction(t, MEMRDH16); + break; + case DWORD: + if (use32) + retval = x86_32->submit_instruction(t, MEMRDW32); + else + retval = x86_32->submit_instruction(t, MEMRDW16); + break; + default: + LOG_ERROR("%s invalid read mem size", __func__); + break; } if (retval != ERROR_OK) @@ -407,27 +407,27 @@ static int write_mem(struct target *t, uint32_t size, return retval; } switch (size) { - case BYTE: - if (use32) - retval = x86_32->submit_instruction(t, MEMWRB32); - else - retval = x86_32->submit_instruction(t, MEMWRB16); - break; - case WORD: - if (use32) - retval = x86_32->submit_instruction(t, MEMWRH32); - else - retval = x86_32->submit_instruction(t, MEMWRH16); - break; - case DWORD: - if (use32) - retval = x86_32->submit_instruction(t, MEMWRW32); - else - retval = x86_32->submit_instruction(t, MEMWRW16); - break; - default: - LOG_ERROR("%s invalid write mem size", __func__); - return ERROR_FAIL; + case BYTE: + if (use32) + retval = x86_32->submit_instruction(t, MEMWRB32); + else + retval = x86_32->submit_instruction(t, MEMWRB16); + break; + case WORD: + if (use32) + retval = x86_32->submit_instruction(t, MEMWRH32); + else + retval = x86_32->submit_instruction(t, MEMWRH16); + break; + case DWORD: + if (use32) + retval = x86_32->submit_instruction(t, MEMWRW32); + else + retval = x86_32->submit_instruction(t, MEMWRW16); + break; + default: + LOG_ERROR("%s invalid write mem size", __func__); + return ERROR_FAIL; } if (retval != ERROR_OK) @@ -706,27 +706,27 @@ static int x86_32_common_read_io(struct target *t, uint32_t addr, pg_disabled = true; } switch (size) { - case BYTE: - if (use32) - retval = x86_32->submit_instruction(t, IORDB32); - else - retval = x86_32->submit_instruction(t, IORDB16); - break; - case WORD: - if (use32) - retval = x86_32->submit_instruction(t, IORDH32); - else - retval = x86_32->submit_instruction(t, IORDH16); - break; - case DWORD: - if (use32) - retval = x86_32->submit_instruction(t, IORDW32); - else - retval = x86_32->submit_instruction(t, IORDW16); - break; - default: - LOG_ERROR("%s invalid read io size", __func__); - return ERROR_FAIL; + case BYTE: + if (use32) + retval = x86_32->submit_instruction(t, IORDB32); + else + retval = x86_32->submit_instruction(t, IORDB16); + break; + case WORD: + if (use32) + retval = x86_32->submit_instruction(t, IORDH32); + else + retval = x86_32->submit_instruction(t, IORDH16); + break; + case DWORD: + if (use32) + retval = x86_32->submit_instruction(t, IORDW32); + else + retval = x86_32->submit_instruction(t, IORDW16); + break; + default: + LOG_ERROR("%s invalid read io size", __func__); + return ERROR_FAIL; } /* restore CR0.PG bit if needed */ @@ -795,27 +795,27 @@ int x86_32_common_write_io(struct target *t, uint32_t addr, pg_disabled = true; } switch (size) { - case BYTE: - if (use32) - retval = x86_32->submit_instruction(t, IOWRB32); - else - retval = x86_32->submit_instruction(t, IOWRB16); - break; - case WORD: - if (use32) - retval = x86_32->submit_instruction(t, IOWRH32); - else - retval = x86_32->submit_instruction(t, IOWRH16); - break; - case DWORD: - if (use32) - retval = x86_32->submit_instruction(t, IOWRW32); - else - retval = x86_32->submit_instruction(t, IOWRW16); - break; - default: - LOG_ERROR("%s invalid write io size", __func__); - return ERROR_FAIL; + case BYTE: + if (use32) + retval = x86_32->submit_instruction(t, IOWRB32); + else + retval = x86_32->submit_instruction(t, IOWRB16); + break; + case WORD: + if (use32) + retval = x86_32->submit_instruction(t, IOWRH32); + else + retval = x86_32->submit_instruction(t, IOWRH16); + break; + case DWORD: + if (use32) + retval = x86_32->submit_instruction(t, IOWRW32); + else + retval = x86_32->submit_instruction(t, IOWRW16); + break; + default: + LOG_ERROR("%s invalid write io size", __func__); + return ERROR_FAIL; } /* restore CR0.PG bit if needed */ @@ -899,29 +899,29 @@ static int set_debug_regs(struct target *t, uint32_t address, } switch (bp_type) { - case 0: - /* 00 - only on instruction execution */ - DR7_SET_EXE(dr7, bp_num); - DR7_SET_LENGTH(dr7, bp_num, bp_length); - break; - case 1: - /* 01 - only on data writes */ - DR7_SET_WRITE(dr7, bp_num); - DR7_SET_LENGTH(dr7, bp_num, bp_length); - break; - case 2: - /* 10 UNSUPPORTED - an I/O read and I/O write */ - LOG_ERROR("%s unsupported feature bp_type=%d", __func__, bp_type); - return ERROR_FAIL; - break; - case 3: - /* on data read or data write */ - DR7_SET_ACCESS(dr7, bp_num); - DR7_SET_LENGTH(dr7, bp_num, bp_length); - break; - default: - LOG_ERROR("%s invalid request [only 0-3] bp_type=%d", __func__, bp_type); - return ERROR_FAIL; + case 0: + /* 00 - only on instruction execution */ + DR7_SET_EXE(dr7, bp_num); + DR7_SET_LENGTH(dr7, bp_num, bp_length); + break; + case 1: + /* 01 - only on data writes */ + DR7_SET_WRITE(dr7, bp_num); + DR7_SET_LENGTH(dr7, bp_num, bp_length); + break; + case 2: + /* 10 UNSUPPORTED - an I/O read and I/O write */ + LOG_ERROR("%s unsupported feature bp_type=%d", __func__, bp_type); + return ERROR_FAIL; + break; + case 3: + /* on data read or data write */ + DR7_SET_ACCESS(dr7, bp_num); + DR7_SET_LENGTH(dr7, bp_num, bp_length); + break; + default: + LOG_ERROR("%s invalid request [only 0-3] bp_type=%d", __func__, bp_type); + return ERROR_FAIL; } /* update regs in the reg cache ready to be written to hardware @@ -1206,19 +1206,19 @@ static int set_watchpoint(struct target *t, struct watchpoint *wp) } switch (wp->rw) { - case WPT_WRITE: - if (set_debug_regs(t, wp->address, wp_num, - DR7_BP_WRITE, wp->length) != ERROR_OK) - return ERROR_FAIL; - break; - case WPT_ACCESS: - if (set_debug_regs(t, wp->address, wp_num, DR7_BP_READWRITE, - wp->length) != ERROR_OK) - return ERROR_FAIL; - break; - default: - LOG_ERROR("%s only 'access' or 'write' watchpoints are supported", __func__); - break; + case WPT_WRITE: + if (set_debug_regs(t, wp->address, wp_num, + DR7_BP_WRITE, wp->length) != ERROR_OK) + return ERROR_FAIL; + break; + case WPT_ACCESS: + if (set_debug_regs(t, wp->address, wp_num, DR7_BP_READWRITE, + wp->length) != ERROR_OK) + return ERROR_FAIL; + break; + default: + LOG_ERROR("%s only 'access' or 'write' watchpoints are supported", __func__); + break; } watchpoint_set(wp, wp_num); debug_reg_list[wp_num].used = 1; @@ -1458,17 +1458,17 @@ COMMAND_HANDLER(handle_iow_command) unsigned int wordsize; switch (CMD_NAME[2]) { - case 'w': - wordsize = 4; - break; - case 'h': - wordsize = 2; - break; - case 'b': - wordsize = 1; - break; - default: - return ERROR_COMMAND_SYNTAX_ERROR; + case 'w': + wordsize = 4; + break; + case 'h': + wordsize = 2; + break; + case 'b': + wordsize = 1; + break; + default: + return ERROR_COMMAND_SYNTAX_ERROR; } return target_fill_io(target, address, wordsize, value); } diff --git a/src/target/xscale.c b/src/target/xscale.c index a6ee7a234..613c8d20a 100644 --- a/src/target/xscale.c +++ b/src/target/xscale.c @@ -517,24 +517,24 @@ static int xscale_send(struct target *target, const uint8_t *buffer, int count, uint32_t t; switch (size) { - case 4: - if (endianness == TARGET_LITTLE_ENDIAN) - t = le_to_h_u32(buffer); - else - t = be_to_h_u32(buffer); - break; - case 2: - if (endianness == TARGET_LITTLE_ENDIAN) - t = le_to_h_u16(buffer); - else - t = be_to_h_u16(buffer); - break; - case 1: - t = buffer[0]; - break; - default: - LOG_ERROR("BUG: size neither 4, 2 nor 1"); - return ERROR_COMMAND_SYNTAX_ERROR; + case 4: + if (endianness == TARGET_LITTLE_ENDIAN) + t = le_to_h_u32(buffer); + else + t = be_to_h_u32(buffer); + break; + case 2: + if (endianness == TARGET_LITTLE_ENDIAN) + t = le_to_h_u16(buffer); + else + t = be_to_h_u16(buffer); + break; + case 1: + t = buffer[0]; + break; + default: + LOG_ERROR("BUG: size neither 4, 2 nor 1"); + return ERROR_COMMAND_SYNTAX_ERROR; } buf_set_u32(t1, 0, 32, t); @@ -916,46 +916,46 @@ static int xscale_debug_entry(struct target *target) pc = buf_get_u32(arm->pc->value, 0, 32); switch (moe) { - case 0x0: /* Processor reset */ - target->debug_reason = DBG_REASON_DBGRQ; - xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET; - pc -= 4; - break; - case 0x1: /* Instruction breakpoint hit */ - target->debug_reason = DBG_REASON_BREAKPOINT; - xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; - pc -= 4; - break; - case 0x2: /* Data breakpoint hit */ - target->debug_reason = DBG_REASON_WATCHPOINT; - xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; - pc -= 4; - break; - case 0x3: /* BKPT instruction executed */ - target->debug_reason = DBG_REASON_BREAKPOINT; - xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; - pc -= 4; - break; - case 0x4: /* Ext. debug event */ - target->debug_reason = DBG_REASON_DBGRQ; - xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; - pc -= 4; - break; - case 0x5: /* Vector trap occurred */ - target->debug_reason = DBG_REASON_BREAKPOINT; - xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; - pc -= 4; - break; - case 0x6: /* Trace buffer full break */ - target->debug_reason = DBG_REASON_DBGRQ; - xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; - pc -= 4; - break; - case 0x7: /* Reserved (may flag Hot-Debug support) */ - default: - LOG_ERROR("Method of Entry is 'Reserved'"); - exit(-1); - break; + case 0x0: /* Processor reset */ + target->debug_reason = DBG_REASON_DBGRQ; + xscale->arch_debug_reason = XSCALE_DBG_REASON_RESET; + pc -= 4; + break; + case 0x1: /* Instruction breakpoint hit */ + target->debug_reason = DBG_REASON_BREAKPOINT; + xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; + pc -= 4; + break; + case 0x2: /* Data breakpoint hit */ + target->debug_reason = DBG_REASON_WATCHPOINT; + xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; + pc -= 4; + break; + case 0x3: /* BKPT instruction executed */ + target->debug_reason = DBG_REASON_BREAKPOINT; + xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; + pc -= 4; + break; + case 0x4: /* Ext. debug event */ + target->debug_reason = DBG_REASON_DBGRQ; + xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; + pc -= 4; + break; + case 0x5: /* Vector trap occurred */ + target->debug_reason = DBG_REASON_BREAKPOINT; + xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC; + pc -= 4; + break; + case 0x6: /* Trace buffer full break */ + target->debug_reason = DBG_REASON_DBGRQ; + xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL; + pc -= 4; + break; + case 0x7: /* Reserved (may flag Hot-Debug support) */ + default: + LOG_ERROR("Method of Entry is 'Reserved'"); + exit(-1); + break; } /* apply PC fixup */ @@ -1815,20 +1815,20 @@ static int xscale_read_memory(struct target *target, target_addr_t address, /* extract data from host-endian buffer into byte stream */ for (i = 0; i < count; i++) { switch (size) { - case 4: - target_buffer_set_u32(target, buffer, buf32[i]); - buffer += 4; - break; - case 2: - target_buffer_set_u16(target, buffer, buf32[i] & 0xffff); - buffer += 2; - break; - case 1: - *buffer++ = buf32[i] & 0xff; - break; - default: - LOG_ERROR("invalid read size"); - return ERROR_COMMAND_SYNTAX_ERROR; + case 4: + target_buffer_set_u32(target, buffer, buf32[i]); + buffer += 4; + break; + case 2: + target_buffer_set_u16(target, buffer, buf32[i] & 0xffff); + buffer += 2; + break; + case 1: + *buffer++ = buf32[i] & 0xff; + break; + default: + LOG_ERROR("invalid read size"); + return ERROR_COMMAND_SYNTAX_ERROR; } } @@ -1907,24 +1907,24 @@ static int xscale_write_memory(struct target *target, target_addr_t address, #if 0 for (i = 0; i < count; i++) { switch (size) { - case 4: - value = target_buffer_get_u32(target, buffer); - xscale_send_u32(target, value); - buffer += 4; - break; - case 2: - value = target_buffer_get_u16(target, buffer); - xscale_send_u32(target, value); - buffer += 2; - break; - case 1: - value = *buffer; - xscale_send_u32(target, value); - buffer += 1; - break; - default: - LOG_ERROR("should never get here"); - exit(-1); + case 4: + value = target_buffer_get_u32(target, buffer); + xscale_send_u32(target, value); + buffer += 4; + break; + case 2: + value = target_buffer_get_u16(target, buffer); + xscale_send_u32(target, value); + buffer += 2; + break; + case 1: + value = *buffer; + xscale_send_u32(target, value); + buffer += 1; + break; + default: + LOG_ERROR("should never get here"); + exit(-1); } } #endif @@ -2234,17 +2234,17 @@ static int xscale_set_watchpoint(struct target *target, } switch (watchpoint->rw) { - case WPT_READ: - enable = 0x3; - break; - case WPT_ACCESS: - enable = 0x2; - break; - case WPT_WRITE: - enable = 0x1; - break; - default: - LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); + case WPT_READ: + enable = 0x3; + break; + case WPT_ACCESS: + enable = 0x2; + break; + case WPT_WRITE: + enable = 0x1; + break; + default: + LOG_ERROR("BUG: watchpoint->rw neither read, write nor access"); } /* For watchpoint across more than one word, both DBR registers must @@ -2685,61 +2685,60 @@ static int xscale_analyze_trace(struct target *target, struct command_invocation continue; switch (trace_msg_type) { - case 0: /* Exceptions */ - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - exception = (trace_data->entries[i].data & 0x70) >> 4; + case 0: /* Exceptions */ + case 1: + case 2: + case 3: + case 4: + case 5: + case 6: + case 7: + exception = (trace_data->entries[i].data & 0x70) >> 4; - /* FIXME: vector table may be at ffff0000 */ - branch_target = (trace_data->entries[i].data & 0xf0) >> 2; - break; + /* FIXME: vector table may be at ffff0000 */ + branch_target = (trace_data->entries[i].data & 0xf0) >> 2; + break; - case 8: /* Direct Branch */ - break; + case 8: /* Direct Branch */ + break; - case 9: /* Indirect Branch */ - xscale_branch_address(trace_data, i, &branch_target); - break; + case 9: /* Indirect Branch */ + xscale_branch_address(trace_data, i, &branch_target); + break; - case 13: /* Checkpointed Indirect Branch */ - xscale_branch_address(trace_data, i, &branch_target); - if (trace_data->num_checkpoints == 2 && chkpt == 0) - chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is - *oldest */ - else - chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and - *newest */ + case 13: /* Checkpointed Indirect Branch */ + xscale_branch_address(trace_data, i, &branch_target); + if (trace_data->num_checkpoints == 2 && chkpt == 0) + chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is + *oldest */ + else + chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and + *newest */ - chkpt++; - break; + chkpt++; + break; - case 12: /* Checkpointed Direct Branch */ - if (trace_data->num_checkpoints == 2 && chkpt == 0) - chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is - *oldest */ - else - chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and - *newest */ + case 12: /* Checkpointed Direct Branch */ + if (trace_data->num_checkpoints == 2 && chkpt == 0) + chkpt_reg = trace_data->chkpt1; /* 2 chkpts, this is + *oldest */ + else + chkpt_reg = trace_data->chkpt0; /* 1 chkpt, or 2 and + *newest */ - /* if no current_pc, checkpoint will be starting point */ - if (current_pc == 0) - branch_target = chkpt_reg; + /* if no current_pc, checkpoint will be starting point */ + if (current_pc == 0) + branch_target = chkpt_reg; - chkpt++; - break; + chkpt++; + break; - case 15:/* Roll-over */ - break; - - default:/* Reserved */ - LOG_WARNING("trace is suspect: invalid trace message byte"); - continue; + case 15:/* Roll-over */ + break; + default:/* Reserved */ + LOG_WARNING("trace is suspect: invalid trace message byte"); + continue; } /* If we don't have the current_pc yet, but we did get the branch target @@ -3520,33 +3519,33 @@ COMMAND_HANDLER(xscale_handle_cp15) COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], reg_no); /*translate from xscale cp15 register no to openocd register*/ switch (reg_no) { - case 0: - reg_no = XSCALE_MAINID; - break; - case 1: - reg_no = XSCALE_CTRL; - break; - case 2: - reg_no = XSCALE_TTB; - break; - case 3: - reg_no = XSCALE_DAC; - break; - case 5: - reg_no = XSCALE_FSR; - break; - case 6: - reg_no = XSCALE_FAR; - break; - case 13: - reg_no = XSCALE_PID; - break; - case 15: - reg_no = XSCALE_CPACCESS; - break; - default: - command_print(CMD, "invalid register number"); - return ERROR_COMMAND_SYNTAX_ERROR; + case 0: + reg_no = XSCALE_MAINID; + break; + case 1: + reg_no = XSCALE_CTRL; + break; + case 2: + reg_no = XSCALE_TTB; + break; + case 3: + reg_no = XSCALE_DAC; + break; + case 5: + reg_no = XSCALE_FSR; + break; + case 6: + reg_no = XSCALE_FAR; + break; + case 13: + reg_no = XSCALE_PID; + break; + case 15: + reg_no = XSCALE_CPACCESS; + break; + default: + command_print(CMD, "invalid register number"); + return ERROR_COMMAND_SYNTAX_ERROR; } reg = &xscale->reg_cache->reg_list[reg_no];