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jtag: retire tap field

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jtag_add_dr/ir_scan() now takes the tap as the first
argument, rather than for each of the fields passed
in.

The code never exercised the path where there was
more than one tap being scanned, who knows if it even
worked.

This simplifies the implementation and reduces clutter
in the calling code.

use jtag_add_ir/dr_plain_scan() for more fancy situations.

Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This commit is contained in:
Øyvind Harboe
2010-03-01 20:00:59 +01:00
parent f7d1be714b
commit e018c7c1d2
30 changed files with 155 additions and 359 deletions
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8
src/target/arm11.c
View File

@@ -123,7 +123,7 @@ static int arm11_debug_entry(struct arm11_common *arm11)
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
@@ -317,7 +317,7 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
arm11_setup_field(arm11, 1, &Ready, NULL, chain5_fields + 1);
arm11_setup_field(arm11, 1, &Valid, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
/* now processor is ready to RESTART */
@@ -1194,7 +1194,7 @@ static int arm11_examine(struct target *target)
arm11_setup_field(arm11, 32, NULL, &device_id, &idcode_field);
arm11_add_dr_scan_vc(1, &idcode_field, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &idcode_field, TAP_DRPAUSE);
/* check DIDR */
@@ -1207,7 +1207,7 @@ static int arm11_examine(struct target *target)
arm11_setup_field(arm11, 32, NULL, &didr, chain0_fields + 0);
arm11_setup_field(arm11, 8, NULL, &implementor, chain0_fields + 1);
arm11_add_dr_scan_vc(ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain0_fields), chain0_fields, TAP_IDLE);
CHECK_RETVAL(jtag_execute_queue());

36
src/target/arm11_dbgtap.c
View File

@@ -49,13 +49,13 @@ static const tap_state_t arm11_move_pi_to_si_via_ci[] =
/* REVISIT no error handling here! */
static void arm11_add_ir_scan_vc(int num_fields, struct scan_field *fields,
static void arm11_add_ir_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields,
tap_state_t state)
{
if (cmd_queue_cur_state == TAP_IRPAUSE)
jtag_add_pathmove(ARRAY_SIZE(arm11_move_pi_to_si_via_ci), arm11_move_pi_to_si_via_ci);
jtag_add_ir_scan(num_fields, fields, state);
jtag_add_ir_scan(tap, num_fields, fields, state);
}
static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
@@ -64,13 +64,13 @@ static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
};
/* REVISIT no error handling here! */
void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields,
void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields,
tap_state_t state)
{
if (cmd_queue_cur_state == TAP_DRPAUSE)
jtag_add_pathmove(ARRAY_SIZE(arm11_move_pd_to_sd_via_cd), arm11_move_pd_to_sd_via_cd);
jtag_add_dr_scan(num_fields, fields, state);
jtag_add_dr_scan(tap, num_fields, fields, state);
}
@@ -87,7 +87,6 @@ void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields,
void arm11_setup_field(struct arm11_common *arm11, int num_bits,
void *out_data, void *in_data, struct scan_field *field)
{
field->tap = arm11->arm.target->tap;
field->num_bits = num_bits;
field->out_value = out_data;
field->in_value = in_data;
@@ -150,7 +149,7 @@ void arm11_add_IR(struct arm11_common * arm11, uint8_t instr, tap_state_t state)
arm11_setup_field(arm11, 5, &instr, NULL, &field);
arm11_add_ir_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
arm11_add_ir_scan_vc(arm11->arm.target->tap, 1, &field, state == ARM11_TAP_DEFAULT ? TAP_IRPAUSE : state);
}
/** Verify data shifted out from Scan Chain Register (SCREG). */
@@ -214,7 +213,7 @@ int arm11_add_debug_SCAN_N(struct arm11_common *arm11,
uint8_t tmp[1];
arm11_setup_field(arm11, 5, &chain, &tmp, &field);
arm11_add_dr_scan_vc(1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &field, state == ARM11_TAP_DEFAULT ? TAP_DRPAUSE : state);
jtag_execute_queue_noclear();
@@ -253,7 +252,7 @@ static void arm11_add_debug_INST(struct arm11_common * arm11,
arm11_setup_field(arm11, 32, &inst, NULL, itr + 0);
arm11_setup_field(arm11, 1, NULL, flag, itr + 1);
arm11_add_dr_scan_vc(ARRAY_SIZE(itr), itr, state);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(itr), itr, state);
}
/**
@@ -281,7 +280,7 @@ int arm11_read_DSCR(struct arm11_common *arm11)
arm11_setup_field(arm11, 32, NULL, &dscr, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &chain1_field, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
@@ -317,7 +316,7 @@ int arm11_write_DSCR(struct arm11_common * arm11, uint32_t dscr)
arm11_setup_field(arm11, 32, &dscr, NULL, &chain1_field);
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, 1, &chain1_field, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
@@ -483,7 +482,7 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
{
Data = *data;
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
CHECK_RETVAL(jtag_execute_queue());
@@ -518,7 +517,7 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
{
Data = 0;
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
@@ -577,17 +576,14 @@ int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint
{
struct scan_field chain5_fields[3];
chain5_fields[0].tap = tap;
chain5_fields[0].num_bits = 32;
chain5_fields[0].out_value = NULL; /*&Data*/
chain5_fields[0].in_value = NULL;
chain5_fields[1].tap = tap;
chain5_fields[1].num_bits = 1;
chain5_fields[1].out_value = NULL;
chain5_fields[1].in_value = NULL; /*&Ready*/
chain5_fields[2].tap = tap;
chain5_fields[2].num_bits = 1;
chain5_fields[2].out_value = NULL;
chain5_fields[2].in_value = NULL;
@@ -611,12 +607,12 @@ int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap * tap, uint
if (count > 0)
{
jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
jtag_add_pathmove(ARRAY_SIZE(arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay),
arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay);
} else
{
jtag_add_dr_scan(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
jtag_add_dr_scan(tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
}
}
@@ -697,7 +693,7 @@ int arm11_run_instr_data_to_core_noack(struct arm11_common * arm11, uint32_t opc
uint8_t ready_flag;
chain5_fields[1].in_value = &ready_flag;
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_DRPAUSE);
retval = jtag_execute_queue();
if (retval == ERROR_OK)
@@ -770,7 +766,7 @@ int arm11_run_instr_data_from_core(struct arm11_common * arm11, uint32_t opcode,
int i = 0;
do
{
arm11_add_dr_scan_vc(ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());
@@ -910,7 +906,7 @@ int arm11_sc7_run(struct arm11_common * arm11, struct arm11_sc7_action * actions
(unsigned) DataOut,
nRW ? "write" : "read");
arm11_add_dr_scan_vc(ARRAY_SIZE(chain7_fields),
arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain7_fields),
chain7_fields, TAP_DRPAUSE);
CHECK_RETVAL(jtag_execute_queue());

2
src/target/arm11_dbgtap.h
View File

@@ -30,7 +30,7 @@ int arm11_run_instr_data_from_core_via_r0(struct arm11_common *arm11,
int arm11_run_instr_data_to_core_via_r0(struct arm11_common *arm11,
uint32_t opcode, uint32_t data);
void arm11_add_dr_scan_vc(int num_fields, struct scan_field *fields,
void arm11_add_dr_scan_vc(struct jtag_tap *tap, int num_fields, struct scan_field *fields,
tap_state_t state);
/**

6
src/target/arm720t.c
View File

@@ -64,12 +64,10 @@ static int arm720t_scan_cp15(struct target *target,
return retval;
}
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &instruction_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = out_buf;
fields[1].in_value = NULL;
@@ -77,11 +75,11 @@ static int arm720t_scan_cp15(struct target *target,
if (in)
{
fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
} else
{
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
}
if (clock)

14
src/target/arm7tdmi.c
View File

@@ -58,12 +58,10 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
jtag_set_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_value = &breakpoint;
fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = databus;
@@ -74,7 +72,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, jtag_set_end_state(TAP_DRPAUSE));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
@@ -85,7 +83,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
fields[1].in_value = NULL;
fields[1].out_value = databus;
jtag_add_dr_scan(2, fields, jtag_set_end_state(TAP_DRPAUSE));
jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, jtag_set_end_state(TAP_DRPAUSE));
if (breakpoint & 1)
target->debug_reason = DBG_REASON_WATCHPOINT;
@@ -141,17 +139,15 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = (uint8_t *)in;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
@@ -228,17 +224,15 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
jtag_alloc_in_value32(&fields[1]);
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);

20
src/target/arm920t.c
View File

@@ -95,31 +95,27 @@ static int arm920t_read_cp15_physical(struct target *target,
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = NULL;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
fields[1].in_value = (uint8_t *)value;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
@@ -150,27 +146,23 @@ static int arm920t_write_cp15_physical(struct target *target,
arm_jtag_scann(jtag_info, 0xf);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = value_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
@@ -206,27 +198,23 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 1;
fields[0].out_value = &access_type_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = cp15_opcode_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 6;
fields[2].out_value = &reg_addr_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);

17
src/target/arm926ejs.c
View File

@@ -70,28 +70,23 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = (uint8_t *)value;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].in_value = &access;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
long long then = timeval_ms();
@@ -100,7 +95,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
@@ -164,27 +159,23 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 1;
fields[1].out_value = &access;
fields[1].in_value = &access;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 14;
fields[2].out_value = address_buf;
fields[2].in_value = NULL;
fields[3].tap = jtag_info->tap;
fields[3].num_bits = 1;
fields[3].out_value = &nr_w_buf;
fields[3].in_value = NULL;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
long long then = timeval_ms();
@@ -193,7 +184,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
/* rescan with NOP, to wait for the access to complete */
access = 0;
nr_w_buf = 0;
jtag_add_dr_scan(4, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;

12
src/target/arm966e.c
View File

@@ -91,7 +91,6 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
/* REVISIT: table 7-2 shows that bits 31-31 need to be
* specified for accessing BIST registers ...
@@ -99,21 +98,19 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 6;
fields[1].out_value = &reg_addr_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
fields[1].in_value = (uint8_t *)value;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
@@ -149,22 +146,19 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
}
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = value_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 6;
fields[1].out_value = &reg_addr_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = &nr_w_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
#ifdef _DEBUG_INSTRUCTION_EXECUTION_
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);

24
src/target/arm9tdmi.c
View File

@@ -89,17 +89,14 @@ int arm9tdmi_examine_debug_reason(struct target *target)
jtag_set_end_state(TAP_DRPAUSE);
fields[0].tap = arm7_9->jtag_info.tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = databus;
fields[1].tap = arm7_9->jtag_info.tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].in_value = &debug_reason;
fields[2].tap = arm7_9->jtag_info.tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].in_value = instructionbus;
@@ -110,7 +107,7 @@ int arm9tdmi_examine_debug_reason(struct target *target)
}
arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, jtag_set_end_state(TAP_DRPAUSE));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
return retval;
@@ -123,7 +120,7 @@ int arm9tdmi_examine_debug_reason(struct target *target)
fields[2].in_value = NULL;
fields[2].out_value = instructionbus;
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_DRPAUSE));
jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, jtag_set_end_state(TAP_DRPAUSE));
if (debug_reason & 0x4)
if (debug_reason & 0x2)
@@ -165,17 +162,14 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].in_value = NULL;
@@ -183,13 +177,13 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
if (in)
{
fields[0].in_value = (uint8_t *)in;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
}
else
{
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
}
jtag_add_runtest(0, jtag_get_end_state());
@@ -227,22 +221,19 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = (uint8_t *)in;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
@@ -297,22 +288,19 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
jtag_alloc_in_value32(&fields[0]);
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = NULL;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = NULL;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);

7
src/target/arm_adi_v5.c
View File

@@ -123,7 +123,6 @@ static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
/* Scan out a read or write operation using some DP or AP register.
* For APACC access with any sticky error flag set, this is discarded.
*/
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 3;
buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
fields[0].out_value = &out_addr_buf;
@@ -134,12 +133,11 @@ static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
* When overrun detect is active, STICKYORUN is set.
*/
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 32;
fields[1].out_value = outvalue;
fields[1].in_value = invalue;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
/* Add specified number of tck clocks after starting memory bus
* access, giving the hardware time to complete the access.
@@ -1132,12 +1130,11 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
if (retval != ERROR_OK)
return retval;
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = (void *) data;
jtag_add_dr_scan(1, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 1, fields, jtag_get_end_state());
retval = jtag_get_error();
if (retval != ERROR_OK)
return retval;

5
src/target/arm_jtag.c
View File

@@ -38,7 +38,6 @@ int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, vo
struct scan_field field;
uint8_t t[4];
field.tap = tap;
field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
@@ -46,13 +45,13 @@ int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr, vo
if (no_verify_capture == NULL)
{
jtag_add_ir_scan(1, &field, jtag_get_end_state());
jtag_add_ir_scan(tap, 1, &field, jtag_get_end_state());
} else
{
/* FIX!!!! this is a kludge!!! arm926ejs.c should reimplement this arm_jtag_set_instr to
* have special verification code.
*/
jtag_add_ir_scan_noverify(1, &field, jtag_get_end_state());
jtag_add_ir_scan_noverify(tap, 1, &field, jtag_get_end_state());
}
return ERROR_OK;

2
src/target/avrt.c
View File

@@ -192,7 +192,6 @@ int mcu_write_ir(struct jtag_tap *tap, uint8_t *ir_in, uint8_t *ir_out, int ir_l
{
struct scan_field field[1];
field[0].tap = tap;
field[0].num_bits = tap->ir_length;
field[0].out_value = ir_out;
field[0].in_value = ir_in;
@@ -213,7 +212,6 @@ int mcu_write_dr(struct jtag_tap *tap, uint8_t *dr_in, uint8_t *dr_out, int dr_l
{
struct scan_field field[1];
field[0].tap = tap;
field[0].num_bits = dr_len;
field[0].out_value = dr_out;
field[0].in_value = dr_in;

2
src/target/dsp563xx.c
View File

@@ -865,7 +865,6 @@ int dsp563xx_write_ir(struct jtag_tap *tap, uint8_t * ir_in, uint8_t * ir_out,
{
struct scan_field field[1];
field[0].tap = tap;
field[0].num_bits = tap->ir_length;
field[0].out_value = ir_out;
field[0].in_value = ir_in;
@@ -888,7 +887,6 @@ int dsp563xx_write_dr(struct jtag_tap *tap, uint8_t * dr_in, uint8_t * dr_out,
{
struct scan_field field[1];
field[0].tap = tap;
field[0].num_bits = dr_len;
field[0].out_value = dr_out;
field[0].in_value = dr_in;

26
src/target/embeddedice.c
View File

@@ -349,7 +349,6 @@ int embeddedice_read_reg_w_check(struct reg *reg,
arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
/* bits 31:0 -- data (ignored here) */
fields[0].tap = ice_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
@@ -357,7 +356,6 @@ int embeddedice_read_reg_w_check(struct reg *reg,
fields[0].check_mask = NULL;
/* bits 36:32 -- register */
fields[1].tap = ice_reg->jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
fields[1].out_value[0] = reg_addr;
@@ -366,7 +364,6 @@ int embeddedice_read_reg_w_check(struct reg *reg,
fields[1].check_mask = NULL;
/* bit 37 -- 0/read */
fields[2].tap = ice_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
fields[2].out_value[0] = 0;
@@ -375,7 +372,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
fields[2].check_mask = NULL;
/* traverse Update-DR, setting address for the next read */
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
/* bits 31:0 -- the data we're reading (and maybe checking) */
fields[0].in_value = reg->value;
@@ -389,7 +386,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
/* traverse Update-DR, reading but with no other side effects */
jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
return ERROR_OK;
}
@@ -412,24 +409,21 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
fields[2].out_value[0] = 0;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
while (size > 0)
{
@@ -440,7 +434,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
fields[0].in_value = (uint8_t *)data;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)data);
data++;
@@ -533,18 +527,15 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = field0_out;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
fields[2].out_value[0] = 1;
@@ -554,7 +545,7 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
while (size > 0)
{
buf_set_u32(fields[0].out_value, 0, 32, *data);
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
data++;
size--;
@@ -589,27 +580,24 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = field0_in;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
fields[2].out_value[0] = 0;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
gettimeofday(&lap, NULL);
do {
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;

23
src/target/etb.c
View File

@@ -54,14 +54,13 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr)
{
struct scan_field field;
field.tap = tap;
field.num_bits = tap->ir_length;
field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.in_value = NULL;
jtag_add_ir_scan(1, &field, jtag_get_end_state());
jtag_add_ir_scan(tap, 1, &field, jtag_get_end_state());
free(field.out_value);
}
@@ -75,7 +74,6 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
{
struct scan_field field;
field.tap = etb->tap;
field.num_bits = 5;
field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
@@ -84,7 +82,7 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
/* select INTEST instruction */
etb_set_instr(etb, 0x2);
jtag_add_dr_scan(1, &field, jtag_get_end_state());
jtag_add_dr_scan(etb->tap, 1, &field, jtag_get_end_state());
etb->cur_scan_chain = new_scan_chain;
@@ -179,24 +177,21 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
etb_scann(etb, 0x0);
etb_set_instr(etb, 0xc);
fields[0].tap = etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].in_value = NULL;
fields[1].tap = etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, 4);
fields[1].in_value = NULL;
fields[2].tap = etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(etb->tap, 3, fields, jtag_get_end_state());
for (i = 0; i < num_frames; i++)
{
@@ -210,7 +205,7 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
buf_set_u32(fields[1].out_value, 0, 7, 0);
fields[0].in_value = (uint8_t *)(data + i);
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(etb->tap, 3, fields, jtag_get_end_state());
jtag_add_callback(etb_getbuf, (jtag_callback_data_t)(data + i));
}
@@ -236,14 +231,12 @@ static int etb_read_reg_w_check(struct reg *reg,
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
fields[0].check_value = NULL;
fields[0].check_mask = NULL;
fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -251,7 +244,6 @@ static int etb_read_reg_w_check(struct reg *reg,
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -259,7 +251,7 @@ static int etb_read_reg_w_check(struct reg *reg,
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(etb_reg->etb->tap, 3, fields, jtag_get_end_state());
/* read the identification register in the second run, to make sure we
* don't read the ETB data register twice, skipping every second entry
@@ -269,7 +261,7 @@ static int etb_read_reg_w_check(struct reg *reg,
fields[0].check_value = check_value;
fields[0].check_mask = check_mask;
jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, jtag_get_end_state());
free(fields[1].out_value);
free(fields[2].out_value);
@@ -322,19 +314,16 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
fields[0].tap = etb_reg->etb->tap;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
buf_set_u32(fields[0].out_value, 0, 32, value);
fields[0].in_value = NULL;
fields[1].tap = etb_reg->etb->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].tap = etb_reg->etb->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 1);

12
src/target/etm.c
View File

@@ -508,14 +508,12 @@ static int etm_read_reg_w_check(struct reg *reg,
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = reg->value;
fields[0].in_value = NULL;
fields[0].check_value = NULL;
fields[0].check_mask = NULL;
fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
@@ -523,7 +521,6 @@ static int etm_read_reg_w_check(struct reg *reg,
fields[1].check_value = NULL;
fields[1].check_mask = NULL;
fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
@@ -531,13 +528,13 @@ static int etm_read_reg_w_check(struct reg *reg,
fields[2].check_value = NULL;
fields[2].check_mask = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
fields[0].in_value = reg->value;
fields[0].check_value = check_value;
fields[0].check_mask = check_mask;
jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
free(fields[1].out_value);
free(fields[2].out_value);
@@ -594,28 +591,25 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
arm_jtag_scann(etm_reg->jtag_info, 0x6);
arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
fields[0].tap = etm_reg->jtag_info->tap;
fields[0].num_bits = 32;
uint8_t tmp1[4];
fields[0].out_value = tmp1;
buf_set_u32(fields[0].out_value, 0, 32, value);
fields[0].in_value = NULL;
fields[1].tap = etm_reg->jtag_info->tap;
fields[1].num_bits = 7;
uint8_t tmp2;
fields[1].out_value = &tmp2;
buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].tap = etm_reg->jtag_info->tap;
fields[2].num_bits = 1;
uint8_t tmp3;
fields[2].out_value = &tmp3;
buf_set_u32(fields[2].out_value, 0, 1, 1);
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, jtag_get_end_state());
return ERROR_OK;
}

5
src/target/feroceon.c
View File

@@ -89,22 +89,19 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].tap = jtag_info->tap;
fields[0].num_bits = 32;
fields[0].out_value = out_buf;
fields[0].in_value = NULL;
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 3;
fields[1].out_value = &sysspeed_buf;
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
fields[2].num_bits = 32;
fields[2].out_value = instr_buf;
fields[2].in_value = NULL;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
/* no jtag_add_runtest(0, jtag_get_end_state()) here */

16
src/target/mips_ejtag.c
View File

@@ -41,13 +41,12 @@ int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *del
struct scan_field field;
uint8_t t[4];
field.tap = tap;
field.num_bits = tap->ir_length;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
field.in_value = NULL;
jtag_add_ir_scan(1, &field, jtag_get_end_state());
jtag_add_ir_scan(tap, 1, &field, jtag_get_end_state());
}
return ERROR_OK;
@@ -61,12 +60,11 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
field.tap = ejtag_info->tap;
field.num_bits = 32;
field.out_value = NULL;
field.in_value = (void*)idcode;
jtag_add_dr_scan(1, &field, jtag_get_end_state());
jtag_add_dr_scan(ejtag_info->tap, 1, &field, jtag_get_end_state());
if (jtag_execute_queue() != ERROR_OK)
{
@@ -84,12 +82,11 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
field.tap = ejtag_info->tap;
field.num_bits = 32;
field.out_value = NULL;
field.in_value = (void*)impcode;
jtag_add_dr_scan(1, &field, jtag_get_end_state());
jtag_add_dr_scan(ejtag_info->tap, 1, &field, jtag_get_end_state());
if (jtag_execute_queue() != ERROR_OK)
{
@@ -110,13 +107,12 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
uint8_t t[4], r[4];
int retval;
field.tap = tap;
field.num_bits = 32;
field.out_value = t;
buf_set_u32(field.out_value, 0, field.num_bits, *data);
field.in_value = r;
jtag_add_dr_scan(1, &field, jtag_get_end_state());
jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@@ -294,13 +290,11 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t
uint8_t t[4] = {0, 0, 0, 0};
/* fastdata 1-bit register */
fields[0].tap = tap;
fields[0].num_bits = 1;
fields[0].out_value = &spracc;
fields[0].in_value = NULL;
/* processor access data register 32 bit */
fields[1].tap = tap;
fields[1].num_bits = 32;
fields[1].out_value = t;
@@ -314,7 +308,7 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t
fields[1].in_value = (uint8_t *) data;
}
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(tap, 2, fields, jtag_get_end_state());
keep_alive();
return ERROR_OK;

42
src/target/xscale.c
View File

@@ -169,12 +169,11 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
uint8_t scratch[4];
memset(&field, 0, sizeof field);
field.tap = tap;
field.num_bits = tap->ir_length;
field.out_value = scratch;
buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
jtag_add_ir_scan(1, &field, jtag_get_end_state());
jtag_add_ir_scan(tap, 1, &field, jtag_get_end_state());
}
return ERROR_OK;
@@ -201,23 +200,20 @@ static int xscale_read_dcsr(struct target *target)
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(target->tap, 3, fields, jtag_get_end_state());
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -240,7 +236,7 @@ static int xscale_read_dcsr(struct target *target)
jtag_set_end_state(TAP_IDLE);
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(target->tap, 3, fields, jtag_get_end_state());
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
@@ -279,15 +275,12 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].check_value = &field0_check_value;
fields[0].check_mask = &field0_check_mask;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].check_value = &field2_check_value;
fields[2].check_mask = &field2_check_mask;
@@ -311,7 +304,7 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
fields[1].in_value = (uint8_t *)(field1 + i);
jtag_add_dr_scan_check(3, fields, jtag_set_end_state(TAP_IDLE));
jtag_add_dr_scan_check(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
jtag_add_callback(xscale_getbuf, (jtag_callback_data_t)(field1 + i));
@@ -392,15 +385,12 @@ static int xscale_read_tx(struct target *target, int consume)
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].in_value = &field0_in;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
uint8_t tmp;
fields[2].in_value = &tmp;
@@ -421,7 +411,7 @@ static int xscale_read_tx(struct target *target, int consume)
jtag_add_pathmove(ARRAY_SIZE(noconsume_path), noconsume_path);
}
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
jtag_add_dr_scan(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -480,16 +470,13 @@ static int xscale_write_rx(struct target *target)
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0_out;
fields[0].in_value = &field0_in;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp;
@@ -502,7 +489,7 @@ static int xscale_write_rx(struct target *target)
LOG_DEBUG("polling RX");
for (;;)
{
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
jtag_add_dr_scan(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -534,7 +521,7 @@ static int xscale_write_rx(struct target *target)
/* set rx_valid */
field2 = 0x1;
jtag_add_dr_scan(3, fields, jtag_set_end_state(TAP_IDLE));
jtag_add_dr_scan(target->tap, 3, fields, jtag_set_end_state(TAP_IDLE));
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
@@ -646,23 +633,20 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 3;
fields[0].out_value = &field0;
uint8_t tmp;
fields[0].in_value = &tmp;
fields[1].tap = target->tap;
fields[1].num_bits = 32;
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[2].tap = target->tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
uint8_t tmp2;
fields[2].in_value = &tmp2;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
jtag_add_dr_scan(target->tap, 3, fields, jtag_get_end_state());
jtag_check_value_mask(fields + 0, &field0_check_value, &field0_check_mask);
jtag_check_value_mask(fields + 2, &field2_check_value, &field2_check_mask);
@@ -717,15 +701,13 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(target->tap, 2, fields, jtag_get_end_state());
/* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
@@ -742,7 +724,7 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
memcpy(&value, packet, sizeof(uint32_t));
cmd = parity(value);
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(target->tap, 2, fields, jtag_get_end_state());
}
return jtag_execute_queue();
@@ -767,15 +749,13 @@ static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
memset(&fields, 0, sizeof fields);
fields[0].tap = target->tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
fields[1].tap = target->tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
jtag_add_dr_scan(2, fields, jtag_get_end_state());
jtag_add_dr_scan(target->tap, 2, fields, jtag_get_end_state());
return ERROR_OK;
}