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jtag ftdi: sample TDO on falling edge of TCK

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Due to signal propagation delays, sampling TDO on rising TCK can become
quite peculiar at fast TCK rates. However, FTDI chips offer a possiblity
to sample TDO on falling edge. With this change, stable operation can be
achieved at 30MHz clock even over 10cm ribbon cable.

Change-Id: Icaf240535dae15512e3c60a944e22a5fbc1b0b06
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3180
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Matthias Welwarsky
2016-01-19 22:36:54 +01:00
committed by Andreas Fritiofson
parent de23931162
commit e026d3ff1b
2 changed files with 60 additions and 9 deletions
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14
doc/openocd.texi
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@@ -2610,8 +2610,22 @@ Set a previously defined signal to the specified level.
@end itemize
@end deffn
@deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
Configure TCK edge at which the adapter samples the value of the TDO signal
Due to signal propagation delays, sampling TDO on rising TCK can become quite
peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
TDO on falling edge of TCK. With some board/adapter configurations, this may increase
stability at higher JTAG clocks.
@itemize @minus
@item @option{rising}, sample TDO on rising edge of TCK - this is the default
@item @option{falling}, sample TDO on falling edge of TCK
@end itemize
@end deffn
For example adapter definitions, see the configuration files shipped in the
@file{interface/ftdi} directory.
@end deffn
@deffn {Interface Driver} {remote_bitbang}