target: cortex_a: support read and write watchpoints
The current code for cortex_a watchpoint sets the field DBGWCR:LSC to '3', that corresponds to 'access' watchpoint. Thus, any 'r' or 'w' watchpoint is considered to 'a'. Convert the enum watchpoint_rw to the corresponding values for the field DBGWCR:LSC. Change-Id: Iccfddb3e34f3f26927983f3b00d9d5f81b06eb21 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/9291 Tested-by: jenkins
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@@ -1769,7 +1769,6 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
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uint32_t address;
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uint32_t address;
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uint8_t address_mask;
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uint8_t address_mask;
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uint8_t byte_address_select;
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uint8_t byte_address_select;
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uint8_t load_store_access_control = 0x3;
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struct cortex_a_common *cortex_a = target_to_cortex_a(target);
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struct cortex_a_common *cortex_a = target_to_cortex_a(target);
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struct armv7a_common *armv7a = &cortex_a->armv7a_common;
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struct armv7a_common *armv7a = &cortex_a->armv7a_common;
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struct cortex_a_wrp *wrp_list = cortex_a->wrp_list;
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struct cortex_a_wrp *wrp_list = cortex_a->wrp_list;
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@@ -1827,6 +1826,22 @@ static int cortex_a_set_watchpoint(struct target *target, struct watchpoint *wat
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break;
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break;
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}
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}
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uint8_t load_store_access_control;
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switch (watchpoint->rw) {
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case WPT_READ:
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load_store_access_control = 1;
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break;
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case WPT_WRITE:
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load_store_access_control = 2;
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break;
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case WPT_ACCESS:
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load_store_access_control = 3;
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break;
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default:
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LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
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return ERROR_FAIL;
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};
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watchpoint_set(watchpoint, wrp_i);
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watchpoint_set(watchpoint, wrp_i);
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control = (address_mask << 24) |
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control = (address_mask << 24) |
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(byte_address_select << 5) |
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(byte_address_select << 5) |
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