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Flash, FRAM and EEPROM driver for STM32 QUAD-/OCTOSPI interface

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- write speed up to 150 kByte/s on STM32F469I-disco (due to
  SWD clock and USB connection), up to 1 MByte/s on Nucleo-F767ZI
  with external STLink-V3 or Nucleo-G474RE with two W25Q256FV in
  dual 4-line mode or STM32H73BI-Disco in octal mode
- tested with STM32L476G-disco (64MBit flash, 3-byte addr),
  STM32F412G-Disco, STM32F469I-Disco, STM32F746G-Disco, and
  STM32L476G-Disco (all 128Mbit flash, 3-byte addr),
  STM32F723E-Disco, STM32F769I-Disco (512Mbit flash, 4-byte addr)
  STM32L4R9I-Disco, STM32L4P5G-Disco (512MBit octo-flash, DTR, 4-byte addr)
  STM32H745I-Disco, STM32H747I-Disco (two 512MBit flash, 4-byte addr)
  STM32H73BI-Disco, STM32H735G-Disco (512MBit octo-flash, DTR, 4-byte addr)
- suitable cfg for Discovery boards included
- limited parsing of SFDP data if flash device not hardcoded
  (tested only in single/quad mode as most devices either don't
  support SFDP at all or have empty(!) SFDP memory)
- 'set' command for auto detection override (e. g. for EEPROMs)
- 'cmd' command for arbitrary SPI commands (reconfiguration, testing etc.)
- makefile for creation of binary loader files
- tcl/board/stm32f469discovery.cfg superseded by stm32f469i-disco.cfg
- tcl/board/stm32f7discovery.cfg removed as name is ambiguous
  (superseded by stm32f746g-disco.cfg vs. stm32f769i-disco.cfg)
- dual 4-line mode tested on Nucleo-F767ZI, Nucleo-H743ZI and Nucleo-H7A3ZI-Q
  with two W25Q256FV, and on Nucleo-L496ZP-P and Nucleo-L4R5ZI
  with two W25Q128FV, sample cfg files included and on STM32H745I-Disco,
  STM32H747I-Disco, STM32H750B-Disco
- read/verify/erase_check uses indirect read mode to work around silicon bug in
  H7, L4+ and MP1 memory mapped mode (last bytes not readable, accessing last
  bytes causes debug interface to hang)
- octospi supported only in single/dual 1-line, 2-line, 4-line
  and single 8-line modes, (not in hyper flash mode)

Requirements:
GPIOs must be initialized appropriately, and SPI flash chip be configured
appropriately (1-line ..., QPI, 4-byte addresses ...). This is board/chip
specific, cf. included cfg files. The driver infers most parameters from
current setting in CR, CCR, ... registers.

Change-Id: I54858fbbe8758c3a5fe58812e93f5f39514704f8
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4321
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
This commit is contained in:
Andreas Bolsch
2016-12-21 10:35:58 +01:00
committed by Tomas Vanek
parent 475f42051e
commit e44539d66c
57 changed files with 6709 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

158
src/target/target.c
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@@ -1031,11 +1031,11 @@ int target_run_flash_async_algorithm(struct target *target,
* programming. The exact delay shouldn't matter as long as it's
* less than buffer size / flash speed. This is very unlikely to
* run when using high latency connections such as USB. */
alive_sleep(10);
alive_sleep(2);
/* to stop an infinite loop on some targets check and increment a timeout
* this issue was observed on a stellaris using the new ICDI interface */
if (timeout++ >= 500) {
if (timeout++ >= 2500) {
LOG_ERROR("timeout waiting for algorithm, a target reset is recommended");
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -1049,6 +1049,10 @@ int target_run_flash_async_algorithm(struct target *target,
if (thisrun_bytes > count * block_size)
thisrun_bytes = count * block_size;
/* Force end of large blocks to be word aligned */
if (thisrun_bytes >= 16)
thisrun_bytes -= (rp + thisrun_bytes) & 0x03;
/* Write data to fifo */
retval = target_write_buffer(target, wp, thisrun_bytes, buffer);
if (retval != ERROR_OK)
@@ -1098,6 +1102,156 @@ int target_run_flash_async_algorithm(struct target *target,
return retval;
}
int target_run_read_async_algorithm(struct target *target,
uint8_t *buffer, uint32_t count, int block_size,
int num_mem_params, struct mem_param *mem_params,
int num_reg_params, struct reg_param *reg_params,
uint32_t buffer_start, uint32_t buffer_size,
uint32_t entry_point, uint32_t exit_point, void *arch_info)
{
int retval;
int timeout = 0;
const uint8_t *buffer_orig = buffer;
/* Set up working area. First word is write pointer, second word is read pointer,
* rest is fifo data area. */
uint32_t wp_addr = buffer_start;
uint32_t rp_addr = buffer_start + 4;
uint32_t fifo_start_addr = buffer_start + 8;
uint32_t fifo_end_addr = buffer_start + buffer_size;
uint32_t wp = fifo_start_addr;
uint32_t rp = fifo_start_addr;
/* validate block_size is 2^n */
assert(!block_size || !(block_size & (block_size - 1)));
retval = target_write_u32(target, wp_addr, wp);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, rp_addr, rp);
if (retval != ERROR_OK)
return retval;
/* Start up algorithm on target */
retval = target_start_algorithm(target, num_mem_params, mem_params,
num_reg_params, reg_params,
entry_point,
exit_point,
arch_info);
if (retval != ERROR_OK) {
LOG_ERROR("error starting target flash read algorithm");
return retval;
}
while (count > 0) {
retval = target_read_u32(target, wp_addr, &wp);
if (retval != ERROR_OK) {
LOG_ERROR("failed to get write pointer");
break;
}
LOG_DEBUG("offs 0x%zx count 0x%" PRIx32 " wp 0x%" PRIx32 " rp 0x%" PRIx32,
(size_t) (buffer - buffer_orig), count, wp, rp);
if (wp == 0) {
LOG_ERROR("flash read algorithm aborted by target");
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
if (((wp - fifo_start_addr) & (block_size - 1)) || wp < fifo_start_addr || wp >= fifo_end_addr) {
LOG_ERROR("corrupted fifo write pointer 0x%" PRIx32, wp);
break;
}
/* Count the number of bytes available in the fifo without
* crossing the wrap around. */
uint32_t thisrun_bytes;
if (wp >= rp)
thisrun_bytes = wp - rp;
else
thisrun_bytes = fifo_end_addr - rp;
if (thisrun_bytes == 0) {
/* Throttle polling a bit if transfer is (much) faster than flash
* reading. The exact delay shouldn't matter as long as it's
* less than buffer size / flash speed. This is very unlikely to
* run when using high latency connections such as USB. */
alive_sleep(2);
/* to stop an infinite loop on some targets check and increment a timeout
* this issue was observed on a stellaris using the new ICDI interface */
if (timeout++ >= 2500) {
LOG_ERROR("timeout waiting for algorithm, a target reset is recommended");
return ERROR_FLASH_OPERATION_FAILED;
}
continue;
}
/* Reset our timeout */
timeout = 0;
/* Limit to the amount of data we actually want to read */
if (thisrun_bytes > count * block_size)
thisrun_bytes = count * block_size;
/* Force end of large blocks to be word aligned */
if (thisrun_bytes >= 16)
thisrun_bytes -= (rp + thisrun_bytes) & 0x03;
/* Read data from fifo */
retval = target_read_buffer(target, rp, thisrun_bytes, buffer);
if (retval != ERROR_OK)
break;
/* Update counters and wrap write pointer */
buffer += thisrun_bytes;
count -= thisrun_bytes / block_size;
rp += thisrun_bytes;
if (rp >= fifo_end_addr)
rp = fifo_start_addr;
/* Store updated write pointer to target */
retval = target_write_u32(target, rp_addr, rp);
if (retval != ERROR_OK)
break;
/* Avoid GDB timeouts */
keep_alive();
}
if (retval != ERROR_OK) {
/* abort flash write algorithm on target */
target_write_u32(target, rp_addr, 0);
}
int retval2 = target_wait_algorithm(target, num_mem_params, mem_params,
num_reg_params, reg_params,
exit_point,
10000,
arch_info);
if (retval2 != ERROR_OK) {
LOG_ERROR("error waiting for target flash write algorithm");
retval = retval2;
}
if (retval == ERROR_OK) {
/* check if algorithm set wp = 0 after fifo writer loop finished */
retval = target_read_u32(target, wp_addr, &wp);
if (retval == ERROR_OK && wp == 0) {
LOG_ERROR("flash read algorithm aborted by target");
retval = ERROR_FLASH_OPERATION_FAILED;
}
}
return retval;
}
int target_read_memory(struct target *target,
target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{