auracaster/openocd
3
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

target: convert 'unsigned' to 'unsigned int'

Browse Source 
Conversion done with
	checkpatch --fix-inplace -types UNSPECIFIED_INT

Ignore the cast as they could be better addressed.
Fix only minor additional checkpatch issue (spacing and line
length).

Use Checkpatch-ignore below for the function pointers in the file
'armv7a_cache_l2x.h' that do not assign the identifier names to
the function arguments.
Most of these struct are unused and should be fixed or dropped.

Checkpatch-ignore: FUNCTION_ARGUMENTS

Change-Id: I8f27e68eb3502e431c1ba801b362358105f9f2dc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8480
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
This commit is contained in:
Antonio Borneo
2024-09-08 21:20:48 +02:00
parent 2ad48b78d4
commit e72733d590
45 changed files with 248 additions and 246 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
src/target/armv4_5.c
View File

@@ -168,9 +168,9 @@ static const struct {
};
/** Map PSR mode bits to the name of an ARM processor operating mode. */
const char *arm_mode_name(unsigned psr_mode)
const char *arm_mode_name(unsigned int psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return arm_mode_data[i].name;
}
@@ -179,9 +179,9 @@ const char *arm_mode_name(unsigned psr_mode)
}
/** Return true iff the parameter denotes a valid ARM processor mode. */
bool is_arm_mode(unsigned psr_mode)
bool is_arm_mode(unsigned int psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return true;
}
@@ -272,8 +272,8 @@ static const struct {
* CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
* (Exception modes have both CPSR and SPSR registers ...)
*/
unsigned cookie;
unsigned gdb_index;
unsigned int cookie;
unsigned int gdb_index;
enum arm_mode mode;
} arm_core_regs[] = {
/* IMPORTANT: we guarantee that the first eight cached registers
@@ -499,7 +499,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
* However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
* CPSR (arm->cpsr) is also not mapped.
*/
struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
{
struct reg *r;
@@ -840,7 +840,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
regs = arm->core_cache->reg_list;
for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
for (unsigned int mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
const char *name;
char *sep = "\n";
char *shadow = "";
@@ -875,11 +875,11 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
sep, name, shadow);
/* display N rows of up to 4 registers each */
for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
for (unsigned int i = 0; i < arm_mode_data[mode].n_indices; ) {
char output[80];
int output_len = 0;
for (unsigned j = 0; j < 4; j++, i++) {
for (unsigned int j = 0; j < 4; j++, i++) {
uint32_t value;
struct reg *reg = regs;
@@ -1750,7 +1750,7 @@ cleanup:
static int arm_full_context(struct target *target)
{
struct arm *arm = target_to_arm(target);
unsigned num_regs = arm->core_cache->num_regs;
unsigned int num_regs = arm->core_cache->num_regs;
struct reg *reg = arm->core_cache->reg_list;
int retval = ERROR_OK;