aarch64: use correct A64 instructions for cache handling

Replace A32 MCR with proper A64 MSR opcodes

Change-Id: I64a60b17a58a26b199d2d1b2d5d91098e0c8cbd0
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>

src/target/armv8.c

@@ -34,7 +34,6 @@
 #include <unistd.h>
 
 #include "armv8_opcodes.h"
-#include "arm_opcodes.h"
 #include "target.h"
 #include "target_type.h"
 
@@ -465,7 +464,7 @@ static int _armv8_flush_all_data(struct target *target)
 			/*  DCCISW */
 			/* LOG_INFO ("%d %d %x",c_way,c_index,value); */
 			retval = dpm->instr_write_data_r0(dpm,
-					ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
+					ARMV8_MSR_GP(SYSTEM_DCCISW, 0),
 					value);
 			if (retval != ERROR_OK)
 				goto done;