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- added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. configuration

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- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes


git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2006-11-22 13:03:10 +00:00
parent 03e8f264f4
commit e9297b40b9
16 changed files with 1641 additions and 76 deletions
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8
src/jtag/Makefile.am
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@@ -55,6 +55,12 @@ else
AT91RM9200FILES =
endif
libjtag_a_SOURCES = jtag.c $(BITBANGFILES) $(PARPORTFILES) $(FT2232FILES) $(AMTJTAGACCELFILES) $(EP93XXFILES) $(AT91RM9200FILES)
if GW16012
GW16012FILES = gw16012.c
else
GW16012FILES =
endif
libjtag_a_SOURCES = jtag.c $(BITBANGFILES) $(PARPORTFILES) $(FT2232FILES) $(AMTJTAGACCELFILES) $(EP93XXFILES) $(AT91RM9200FILES) $(GW16012FILES)
noinst_HEADERS = bitbang.h jtag.h