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- added a PLD (programmable logic device) subsystem for FPGA, CPLD etc. configuration

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- added support for loading .bit files into Xilinx Virtex-II devices
- added support for the Gateworks GW16012 JTAG dongle
- merged CFI fixes from XScale branch
- a few minor fixes


git-svn-id: svn://svn.berlios.de/openocd/trunk@116 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2006-11-22 13:03:10 +00:00
parent 03e8f264f4
commit e9297b40b9
16 changed files with 1641 additions and 76 deletions
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5
src/pld/Makefile.am Normal file
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INCLUDES = -I$(top_srcdir)/src/server -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag $(all_includes)
METASOURCES = AUTO
noinst_LIBRARIES = libpld.a
noinst_HEADERS = pld.h xilinx_bit.h virtex2.h
libpld_a_SOURCES = pld.c xilinx_bit.c virtex2.c