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ARM DPM: share debug reason logic

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No point in both ARM11 and Cortex-A8 having private copies
of the logic sorting out e.g. DBG_REASON_WATCHPOINT.

Add and use a shared routine for this ... there's actually
a bunch more debug entry logic that could be shared, this
is just a start on that.  Note that this routine fixes a
bug observed in the ARM11 code, where some abort mode quirks
were displayed as being an unknown debug reason; and also
silences needless ARM11 chatter.

Likewise with private copies of DSCR ... add one to the DPM
struct.  Save it as part of setting DBG_REASON_* so later
patches can switch over to using that copy.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2009-12-03 16:08:04 -08:00
parent 6eee0729d7
commit ea7a49cb9b
7 changed files with 59 additions and 99 deletions
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36
src/target/arm_dpm.c
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@@ -755,6 +755,42 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr)
/*----------------------------------------------------------------------*/
/*
* Other debug and support utilities
*/
void arm_dpm_report_dscr(struct arm_dpm *dpm, uint32_t dscr)
{
struct target *target = dpm->arm->target;
dpm->dscr = dscr;
/* Examine debug reason */
switch (DSCR_ENTRY(dscr)) {
case 6: /* Data abort (v6 only) */
case 7: /* Prefetch abort (v6 only) */
/* FALL THROUGH -- assume a v6 core in abort mode */
case 0: /* HALT request from debugger */
case 4: /* EDBGRQ */
target->debug_reason = DBG_REASON_DBGRQ;
break;
case 1: /* HW breakpoint */
case 3: /* SW BKPT */
case 5: /* vector catch */
target->debug_reason = DBG_REASON_BREAKPOINT;
break;
case 2: /* asynch watchpoint */
case 10: /* precise watchpoint */
target->debug_reason = DBG_REASON_WATCHPOINT;
break;
default:
target->debug_reason = DBG_REASON_UNDEFINED;
break;
}
}
/*----------------------------------------------------------------------*/
/*
* Setup and management support.
*/