flash/nor: add DesignWare SPI controller driver

Driver for DesignWare SPI controller, found on many SoCs (see compatible
list in Linux device tree bindings
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml). This
implementation only supports MIPS as it was the only one available for the
tests, however, adding support for other architectures should require only
few adjustments. Driver relies on flash/nor/spi.h to find Flash chip info.
Driver internal functions support 24bit addressing mode, but due to
limitations of flash/nor/spi.h, it is not used. The reported writing speed
is about 60kb/s.
Lint, sanitizer and valgrind reported warnings were not related to the
driver.

Change-Id: Id3df5626ab88055f034f74f274823051dedefeb1
Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8400
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Sergey Matsievskiy
2024-09-18 20:12:48 +03:00
committed by Tomas Vanek
parent ce38758e3d
commit eb6f2745b7
14 changed files with 2560 additions and 0 deletions

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# SPDX-License-Identifier: GPL-2.0-or-later
TOOLCHAIN:=mipsel-linux-gnu-
CC:=$(TOOLCHAIN)gcc
OBJCOPY:=$(TOOLCHAIN)objcopy
CFLAGS:=-O2 -Wall -Wextra -fpic -Wno-int-to-pointer-cast
SRC=dw-spi.c
OBJ=$(patsubst %.c, %.o,$(SRC))
# sparx-iv
ifeq ($(TOOLCHAIN),mipsel-linux-gnu-)
CFLAGS+= -march=24kec
endif
all: \
$(TOOLCHAIN)transaction.inc \
$(TOOLCHAIN)erase.inc \
$(TOOLCHAIN)check_fill.inc \
$(TOOLCHAIN)program.inc \
$(TOOLCHAIN)read.inc
$(TOOLCHAIN)%.bin: $(OBJ)
$(OBJCOPY) --dump-section .$*=$@ $<
%.inc: %.bin
xxd -i > $@ < $<
.PHONY: clean
clean:
rm -rf .ccls-cache
find . \( \
-iname "*.o" \
-o -iname "*.bin" \
-o -iname "*.inc" \
\) -delete

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@@ -0,0 +1,246 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/**
* @file
* Helper functions for DesignWare SPI Core driver.
* These helpers are loaded into CPU and execute Flash manipulation algorithms
* at full CPU speed. Due to inability to control nCS pin, this is the only way
* to communicate with Flash chips connected via DW SPI serial interface.
*
* In order to avoid using stack, all functions used in helpers are inlined.
* Software breakpoints are used to terminate helpers.
*
* Pushing byte to TX FIFO does not make byte immediately available in RX FIFO
* and nCS is only asserted when TX FIFO is not empty. General approach is to
* fill TX FIFO with as many bytes as possible, at the same time reading
* available bytes from RX FIFO.
*
* This file contains helper functions.
*/
#include "dw-spi.h"
#include "../../../../src/flash/nor/dw-spi-helper.h"
/**
* @brief Generic flash transaction.
*
* @param[in] arg: Function arguments.
*/
__attribute__((section(".transaction"))) void
transaction(struct dw_spi_transaction *arg)
{
register uint8_t *buffer_tx = (uint8_t *)arg->buffer;
register uint8_t *buffer_rx = buffer_tx;
register uint32_t size = arg->size;
register volatile uint8_t *status = (uint8_t *)arg->status_reg;
register volatile uint8_t *data = (uint8_t *)arg->data_reg;
wait_tx_finish(status);
flush_rx(status, data);
for (; size > 0; size--) {
send_u8(status, data, *buffer_tx++);
if (arg->read_flag && rx_available(status))
*buffer_rx++ = rcv_byte(data);
}
// Pushed all data to TX FIFO. Read bytes left in RX FIFO.
if (arg->read_flag) {
while (buffer_rx < buffer_tx) {
wait_rx_available(status);
*buffer_rx++ = rcv_byte(data);
}
}
RETURN;
}
/**
* @brief Check flash sectors are filled with pattern. Primary use for
* checking sector erase state.
*
* @param[in] arg: Function arguments.
*/
__attribute__((section(".check_fill"))) void
check_fill(struct dw_spi_check_fill *arg)
{
register uint32_t tx_size;
register uint32_t rx_size;
register uint32_t dummy_count;
register uint8_t filled;
register uint8_t *fill_status_array = (uint8_t *)arg->fill_status_array;
register volatile uint8_t *status = (uint8_t *)arg->status_reg;
register volatile uint8_t *data = (uint8_t *)arg->data_reg;
for (; arg->sector_count > 0; arg->sector_count--,
arg->address += arg->sector_size,
fill_status_array++) {
wait_tx_finish(status);
flush_rx(status, data);
/*
* Command byte and address bytes make up for dummy_count number of
* bytes, that must be skipped in RX FIFO before actual data arrives.
*/
send_u8(status, data, arg->read_cmd);
if (arg->four_byte_mode) {
dummy_count = 1 + 4; // Command byte + 4 address bytes
send_u32(status, data, arg->address);
} else {
dummy_count = 1 + 3; // Command byte + 3 address bytes
send_u24(status, data, arg->address);
}
for (tx_size = arg->sector_size, rx_size = arg->sector_size, filled = 1;
tx_size > 0; tx_size--) {
send_u8(status, data, 0); // Dummy write to push out read data.
if (rx_available(status)) {
if (dummy_count > 0) {
// Read data not arrived yet.
rcv_byte(data);
dummy_count--;
} else {
if (rcv_byte(data) != arg->pattern) {
filled = 0;
break;
}
rx_size--;
}
}
}
if (filled) {
for (; rx_size > 0; rx_size--) {
wait_rx_available(status);
if (rcv_byte(data) != arg->pattern) {
filled = 0;
break;
}
}
}
*fill_status_array = filled;
}
RETURN;
}
/**
* @brief Erase flash sectors.
*
* @param[in] arg: Function arguments.
*/
__attribute__((section(".erase"))) void
erase(struct dw_spi_erase *arg)
{
register uint32_t address = arg->address;
register uint32_t count = arg->sector_count;
register volatile uint8_t *status = (uint8_t *)arg->status_reg;
register volatile uint8_t *data = (uint8_t *)arg->data_reg;
for (; count > 0; count--, address += arg->sector_size) {
write_enable(status, data, arg->write_enable_cmd);
wait_write_enable(status, data, arg->read_status_cmd,
arg->write_enable_mask);
erase_sector(status, data, arg->erase_sector_cmd, address,
arg->four_byte_mode);
wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
}
RETURN;
}
/**
* @brief Flash program.
*
* @param[in] arg: Function arguments.
*/
__attribute__((section(".program"))) void
program(struct dw_spi_program *arg)
{
register uint8_t *buffer = (uint8_t *)arg->buffer;
register uint32_t buffer_size = arg->buffer_size;
register volatile uint8_t *status = (uint8_t *)arg->status_reg;
register volatile uint8_t *data = (uint8_t *)arg->data_reg;
register uint32_t page_size;
while (buffer_size > 0) {
write_enable(status, data, arg->write_enable_cmd);
wait_write_enable(status, data, arg->read_status_cmd,
arg->write_enable_mask);
wait_tx_finish(status);
send_u8(status, data, arg->program_cmd);
if (arg->four_byte_mode)
send_u32(status, data, arg->address);
else
send_u24(status, data, arg->address);
for (page_size = MIN(arg->page_size, buffer_size); page_size > 0;
page_size--, buffer_size--) {
send_u8(status, data, *buffer++);
}
arg->address += arg->page_size;
wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
}
RETURN;
}
/**
* @brief Read data from flash.
*
* @param[in] arg: Function arguments.
*/
__attribute__((section(".read"))) void
read(struct dw_spi_read *arg)
{
register uint32_t tx_size = arg->buffer_size;
register uint32_t rx_size = arg->buffer_size;
register uint32_t dummy_count;
register uint8_t *buffer = (uint8_t *)arg->buffer;
register volatile uint8_t *status = (uint8_t *)arg->status_reg;
register volatile uint8_t *data = (uint8_t *)arg->data_reg;
wait_tx_finish(status);
flush_rx(status, data);
/*
* Command byte and address bytes make up for dummy_count number of
* bytes, that must be skipped in RX FIFO before actual data arrives.
*/
send_u8(status, data, arg->read_cmd);
if (arg->four_byte_mode) {
dummy_count = 1 + 4; // Command byte + 4 address bytes
send_u32(status, data, arg->address);
} else {
dummy_count = 1 + 3; // Command byte + 3 address bytes
send_u24(status, data, arg->address);
}
for (; tx_size > 0; tx_size--) {
send_u8(status, data, 0); // Dummy write to push out read data.
if (rx_available(status)) {
if (dummy_count > 0) {
rcv_byte(data);
dummy_count--;
} else {
*buffer++ = rcv_byte(data);
rx_size--;
}
}
}
while (rx_size > 0) {
wait_rx_available(status);
if (dummy_count > 0) {
// Read data not arrived yet.
rcv_byte(data);
dummy_count--;
} else {
*buffer++ = rcv_byte(data);
rx_size--;
}
}
RETURN;
}

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/* SPDX-License-Identifier: GPL-2.0-or-later */
/**
* @file
* Helper functions for DesignWare SPI Core driver.
* These helpers are loaded into CPU and execute Flash manipulation algorithms
* at full CPU speed. Due to inability to control nCS pin, this is the only way
* to communicate with Flash chips connected via DW SPI serial interface.
*
* In order to avoid using stack, all functions used in helpers are inlined.
* Software breakpoints are used to terminate helpers.
*
* This file contains functions, common to helpers.
*/
#ifndef _DW_SPI_H_
#define _DW_SPI_H_
#include <stdint.h>
#include <sys/param.h>
#include "../../../../src/helper/types.h"
/**
* @brief SI busy status bit.
*
* Set when serial transfer is in progress, cleared when master is idle or
* disabled.
*/
#define DW_SPI_STATUS_BUSY 0x01
/**
* @brief SI TX FIFO not full status bit.
*
* Set when TX FIFO has room for one or more data-word.
*/
#define DW_SPI_STATUS_TFNF 0x02
/**
* @brief SI TX FIFO empty status bit.
*/
#define DW_SPI_STATUS_TFE 0x04
/**
* @brief SI RX FIFO not empty status bit.
*/
#define DW_SPI_STATUS_RFNE 0x08
/**
* @brief Return from helper function.
*/
#define RETURN \
do { \
asm("sdbbp\n\t"); \
return; \
} while (0)
/**
* @brief Append byte to TX FIFO.
*
* For each transferred byte, DW SPI controller receives a byte into RX FIFO.
* Slave data are read by pushing dummy bytes to TX FIFO.
*
* @param[in] dr: Pointer to DR register.
* @param[in] byte: Data to push.
*/
__attribute__((always_inline)) static inline void
_send_byte(volatile uint8_t *dr, uint8_t byte)
{
*dr = byte;
}
/**
* @brief Get byte from RX FIFO.
*
* Reading RX byte removes it from RX FIFO.
*
* @param[in] dr: Pointer to DR register.
* @return RX FIFO byte.
*/
__attribute__((always_inline)) static inline uint8_t
rcv_byte(volatile uint8_t *dr)
{
return *dr;
}
/**
* @brief Check transmission is currently in progress.
*
* @param[in] sr: Pointer to SR register.
* @retval 1: Transmission is in progress.
* @retval 0: Controller is idle or off.
*/
__attribute__((always_inline)) static inline int
tx_in_progress(volatile uint8_t *sr)
{
return (*sr ^ DW_SPI_STATUS_TFE) & (DW_SPI_STATUS_BUSY | DW_SPI_STATUS_TFE);
}
/**
* @brief Wait for controller to finish previous transaction.
*
* @param[in] sr: Pointer to SR register.
*/
__attribute__((always_inline)) static inline void
wait_tx_finish(volatile uint8_t *sr)
{
while (tx_in_progress(sr))
;
}
/**
* @brief Wait for room in TX FIFO.
*
* @param[in] sr: Pointer to SR register.
*/
__attribute__((always_inline)) static inline void
wait_tx_available(volatile uint8_t *sr)
{
while (!(*sr & DW_SPI_STATUS_TFNF))
;
}
/**
* @brief Check for data available in RX FIFO.
*
* @param[in] sr: Pointer to SR register.
* @retval 1: Data available.
* @retval 0: No data available.
*/
__attribute__((always_inline)) static inline int
rx_available(volatile uint8_t *sr)
{
return *sr & DW_SPI_STATUS_RFNE;
}
/**
* @brief Wait for data in RX FIFO.
*
* @param[in] sr: Pointer to SR register.
*/
__attribute__((always_inline)) static inline void
wait_rx_available(volatile uint8_t *sr)
{
while (!rx_available(sr))
;
}
/**
* @brief Flush RX FIFO.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
*/
__attribute__((always_inline)) static inline void
flush_rx(volatile uint8_t *sr, volatile uint8_t *dr)
{
while (*sr & DW_SPI_STATUS_RFNE)
*dr;
}
/**
* @brief Append variable number of bytes to TX FIFO.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] word: Data to append.
* @param[in] bytes: Number of bytes to append.
*/
__attribute__((always_inline)) static inline void
_send_bytes(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word,
int bytes)
{
for (register int i = bytes - 1; i >= 0; i--) {
wait_tx_available(sr);
_send_byte(dr, (word >> (i * 8)) & 0xff);
}
}
/**
* @brief Append 8 bit value to TX FIFO.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] word: Data to push.
*/
__attribute__((always_inline)) static inline void
send_u8(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t byte)
{
wait_tx_available(sr);
_send_byte(dr, byte);
}
/**
* @brief Append 24 bit value to TX FIFO.
*
* Used to send Flash addresses in 24 bit mode.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] word: Data to push.
*/
__attribute__((always_inline)) static inline void
send_u24(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
{
_send_bytes(sr, dr, word, 3);
}
/**
* @brief Append 32 bit value to TX FIFO.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] word: Data to push.
*/
__attribute__((always_inline)) static inline void
send_u32(volatile uint8_t *sr, volatile uint8_t *dr, uint32_t word)
{
_send_bytes(sr, dr, word, 4);
}
/**
* @brief Read chip status register.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] stat_cmd: Read status command.
* @return Chip status.
*/
__attribute__((always_inline)) static inline uint8_t
read_status(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd)
{
wait_tx_finish(sr);
flush_rx(sr, dr);
/*
* Don't bother with wait_tx_available() as TX FIFO is empty
* and we only send two bytes.
*/
_send_byte(dr, stat_cmd);
_send_byte(dr, 0); // Dummy write to push out read data.
wait_rx_available(sr);
rcv_byte(dr); // Dummy read to skip command byte.
wait_rx_available(sr);
return rcv_byte(dr);
}
/**
* @brief Enable Flash chip write.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] we_cmd: Write enable command.
*/
__attribute__((always_inline)) static inline void
write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t we_cmd)
{
wait_tx_finish(sr);
_send_byte(dr, we_cmd);
}
/**
* @brief Erase Flash sector.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] erase_cmd: Erase sector cmd.
* @param[in] address: Sector address.
* @param[in] four_byte_mode: Device is in 32 bit mode flag.
*/
__attribute__((always_inline)) static inline void
erase_sector(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t erase_cmd,
uint32_t address, uint8_t four_byte_mode)
{
wait_tx_finish(sr);
_send_byte(dr, erase_cmd);
if (four_byte_mode)
send_u32(sr, dr, address);
else
send_u24(sr, dr, address);
}
/**
* @brief Wait for write enable flag.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] stat_cmd: Read status command.
* @param[in] we_mask: Write enable status mask.
*/
__attribute__((always_inline)) static inline void
wait_write_enable(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
uint8_t we_mask)
{
while (!(read_status(sr, dr, stat_cmd) & we_mask))
;
}
/**
* @brief Wait while flash is busy.
*
* @param[in] sr: Pointer to SR register.
* @param[in] dr: Pointer to DR register.
* @param[in] stat_cmd: Read status command.
* @param[in] busy_mask: Flash busy mask.
*/
__attribute__((always_inline)) static inline void
wait_busy(volatile uint8_t *sr, volatile uint8_t *dr, uint8_t stat_cmd,
uint8_t busy_mask)
{
while (read_status(sr, dr, stat_cmd) & busy_mask)
;
}
#endif // _DW_SPI_H_

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