flash/nor: add DesignWare SPI controller driver
Driver for DesignWare SPI controller, found on many SoCs (see compatible list in Linux device tree bindings Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml). This implementation only supports MIPS as it was the only one available for the tests, however, adding support for other architectures should require only few adjustments. Driver relies on flash/nor/spi.h to find Flash chip info. Driver internal functions support 24bit addressing mode, but due to limitations of flash/nor/spi.h, it is not used. The reported writing speed is about 60kb/s. Lint, sanitizer and valgrind reported warnings were not related to the driver. Change-Id: Id3df5626ab88055f034f74f274823051dedefeb1 Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8400 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Sergey Matsievskiy
committed by
Tomas Vanek
Tomas Vanek
parent
ce38758e3d
commit
eb6f2745b7
246
contrib/loaders/flash/dw-spi/dw-spi.c
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246
contrib/loaders/flash/dw-spi/dw-spi.c
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// SPDX-License-Identifier: GPL-2.0-or-later
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/**
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* @file
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* Helper functions for DesignWare SPI Core driver.
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* These helpers are loaded into CPU and execute Flash manipulation algorithms
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* at full CPU speed. Due to inability to control nCS pin, this is the only way
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* to communicate with Flash chips connected via DW SPI serial interface.
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*
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* In order to avoid using stack, all functions used in helpers are inlined.
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* Software breakpoints are used to terminate helpers.
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*
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* Pushing byte to TX FIFO does not make byte immediately available in RX FIFO
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* and nCS is only asserted when TX FIFO is not empty. General approach is to
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* fill TX FIFO with as many bytes as possible, at the same time reading
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* available bytes from RX FIFO.
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*
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* This file contains helper functions.
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*/
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#include "dw-spi.h"
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#include "../../../../src/flash/nor/dw-spi-helper.h"
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/**
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* @brief Generic flash transaction.
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*
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* @param[in] arg: Function arguments.
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*/
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__attribute__((section(".transaction"))) void
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transaction(struct dw_spi_transaction *arg)
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{
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register uint8_t *buffer_tx = (uint8_t *)arg->buffer;
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register uint8_t *buffer_rx = buffer_tx;
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register uint32_t size = arg->size;
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register volatile uint8_t *status = (uint8_t *)arg->status_reg;
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register volatile uint8_t *data = (uint8_t *)arg->data_reg;
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wait_tx_finish(status);
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flush_rx(status, data);
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for (; size > 0; size--) {
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send_u8(status, data, *buffer_tx++);
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if (arg->read_flag && rx_available(status))
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*buffer_rx++ = rcv_byte(data);
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}
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// Pushed all data to TX FIFO. Read bytes left in RX FIFO.
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if (arg->read_flag) {
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while (buffer_rx < buffer_tx) {
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wait_rx_available(status);
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*buffer_rx++ = rcv_byte(data);
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}
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}
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RETURN;
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}
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/**
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* @brief Check flash sectors are filled with pattern. Primary use for
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* checking sector erase state.
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*
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* @param[in] arg: Function arguments.
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*/
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__attribute__((section(".check_fill"))) void
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check_fill(struct dw_spi_check_fill *arg)
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{
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register uint32_t tx_size;
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register uint32_t rx_size;
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register uint32_t dummy_count;
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register uint8_t filled;
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register uint8_t *fill_status_array = (uint8_t *)arg->fill_status_array;
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register volatile uint8_t *status = (uint8_t *)arg->status_reg;
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register volatile uint8_t *data = (uint8_t *)arg->data_reg;
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for (; arg->sector_count > 0; arg->sector_count--,
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arg->address += arg->sector_size,
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fill_status_array++) {
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wait_tx_finish(status);
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flush_rx(status, data);
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/*
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* Command byte and address bytes make up for dummy_count number of
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* bytes, that must be skipped in RX FIFO before actual data arrives.
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*/
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send_u8(status, data, arg->read_cmd);
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if (arg->four_byte_mode) {
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dummy_count = 1 + 4; // Command byte + 4 address bytes
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send_u32(status, data, arg->address);
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} else {
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dummy_count = 1 + 3; // Command byte + 3 address bytes
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send_u24(status, data, arg->address);
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}
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for (tx_size = arg->sector_size, rx_size = arg->sector_size, filled = 1;
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tx_size > 0; tx_size--) {
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send_u8(status, data, 0); // Dummy write to push out read data.
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if (rx_available(status)) {
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if (dummy_count > 0) {
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// Read data not arrived yet.
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rcv_byte(data);
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dummy_count--;
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} else {
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if (rcv_byte(data) != arg->pattern) {
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filled = 0;
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break;
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}
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rx_size--;
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}
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}
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}
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if (filled) {
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for (; rx_size > 0; rx_size--) {
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wait_rx_available(status);
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if (rcv_byte(data) != arg->pattern) {
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filled = 0;
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break;
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}
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}
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}
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*fill_status_array = filled;
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}
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RETURN;
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}
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/**
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* @brief Erase flash sectors.
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*
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* @param[in] arg: Function arguments.
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*/
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__attribute__((section(".erase"))) void
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erase(struct dw_spi_erase *arg)
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{
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register uint32_t address = arg->address;
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register uint32_t count = arg->sector_count;
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register volatile uint8_t *status = (uint8_t *)arg->status_reg;
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register volatile uint8_t *data = (uint8_t *)arg->data_reg;
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for (; count > 0; count--, address += arg->sector_size) {
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write_enable(status, data, arg->write_enable_cmd);
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wait_write_enable(status, data, arg->read_status_cmd,
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arg->write_enable_mask);
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erase_sector(status, data, arg->erase_sector_cmd, address,
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arg->four_byte_mode);
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wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
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}
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RETURN;
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}
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/**
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* @brief Flash program.
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*
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* @param[in] arg: Function arguments.
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*/
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__attribute__((section(".program"))) void
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program(struct dw_spi_program *arg)
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{
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register uint8_t *buffer = (uint8_t *)arg->buffer;
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register uint32_t buffer_size = arg->buffer_size;
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register volatile uint8_t *status = (uint8_t *)arg->status_reg;
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register volatile uint8_t *data = (uint8_t *)arg->data_reg;
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register uint32_t page_size;
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while (buffer_size > 0) {
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write_enable(status, data, arg->write_enable_cmd);
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wait_write_enable(status, data, arg->read_status_cmd,
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arg->write_enable_mask);
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wait_tx_finish(status);
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send_u8(status, data, arg->program_cmd);
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if (arg->four_byte_mode)
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send_u32(status, data, arg->address);
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else
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send_u24(status, data, arg->address);
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for (page_size = MIN(arg->page_size, buffer_size); page_size > 0;
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page_size--, buffer_size--) {
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send_u8(status, data, *buffer++);
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}
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arg->address += arg->page_size;
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wait_busy(status, data, arg->read_status_cmd, arg->busy_mask);
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}
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RETURN;
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}
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/**
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* @brief Read data from flash.
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*
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* @param[in] arg: Function arguments.
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*/
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__attribute__((section(".read"))) void
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read(struct dw_spi_read *arg)
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{
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register uint32_t tx_size = arg->buffer_size;
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register uint32_t rx_size = arg->buffer_size;
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register uint32_t dummy_count;
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register uint8_t *buffer = (uint8_t *)arg->buffer;
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register volatile uint8_t *status = (uint8_t *)arg->status_reg;
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register volatile uint8_t *data = (uint8_t *)arg->data_reg;
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wait_tx_finish(status);
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flush_rx(status, data);
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/*
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* Command byte and address bytes make up for dummy_count number of
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* bytes, that must be skipped in RX FIFO before actual data arrives.
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*/
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send_u8(status, data, arg->read_cmd);
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if (arg->four_byte_mode) {
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dummy_count = 1 + 4; // Command byte + 4 address bytes
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send_u32(status, data, arg->address);
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} else {
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dummy_count = 1 + 3; // Command byte + 3 address bytes
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send_u24(status, data, arg->address);
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}
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for (; tx_size > 0; tx_size--) {
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send_u8(status, data, 0); // Dummy write to push out read data.
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if (rx_available(status)) {
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if (dummy_count > 0) {
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rcv_byte(data);
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dummy_count--;
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} else {
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*buffer++ = rcv_byte(data);
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rx_size--;
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}
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}
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}
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while (rx_size > 0) {
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wait_rx_available(status);
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if (dummy_count > 0) {
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// Read data not arrived yet.
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rcv_byte(data);
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dummy_count--;
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} else {
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*buffer++ = rcv_byte(data);
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rx_size--;
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}
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}
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RETURN;
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}
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