Submitted by Dean Glazeski <dnglaze@gmail.com>:
Add doxygen comments in arm7_9_common source and header files. git-svn-id: svn://svn.berlios.de/openocd/trunk@1880 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@@ -32,52 +32,55 @@
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#include "breakpoints.h"
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#include "etm.h"
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#define ARM7_9_COMMON_MAGIC 0x0a790a79
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#define ARM7_9_COMMON_MAGIC 0x0a790a79 /**< */
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/**
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* Structure for items that are common between both ARM7 and ARM9 targets.
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*/
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typedef struct arm7_9_common_s
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{
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u32 common_magic;
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arm_jtag_t jtag_info;
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reg_cache_t *eice_cache;
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arm_jtag_t jtag_info; /**< JTAG information for target */
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reg_cache_t *eice_cache; /**< Embedded ICE register cache */
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u32 arm_bkpt;
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u16 thumb_bkpt;
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int sw_breakpoints_added;
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int breakpoint_count;
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int wp_available;
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int wp_available_max;
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int wp0_used;
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int wp1_used;
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int wp1_used_default;
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u32 arm_bkpt; /**< ARM breakpoint instruction */
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u16 thumb_bkpt; /**< Thumb breakpoint instruction */
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int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
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int breakpoint_count; /**< Current number of set breakpoints */
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int wp_available; /**< Current number of available watchpoint units */
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int wp_available_max; /**< Maximum number of available watchpoint units */
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int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
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int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
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int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
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int force_hw_bkpts;
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int dbgreq_adjust_pc;
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int use_dbgrq;
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int need_bypass_before_restart;
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int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
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int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
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int need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
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etm_context_t *etm_ctx;
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int has_single_step;
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int has_monitor_mode;
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int has_vector_catch;
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int has_vector_catch; /**< Specifies if the target has a reset vector catch */
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int debug_entry_from_reset;
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int debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
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struct working_area_s *dcc_working_area;
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int fast_memory_access;
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int dcc_downloads;
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int (*examine_debug_reason)(target_t *target);
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int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
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void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
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void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc); /**< Function for changing from Thumb to ARM mode */
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void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
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void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]); /**< Function for reading the core registers */
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void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
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void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr);
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void (*read_xpsr)(target_t *target, u32 *xpsr, int spsr); /**< Function for reading CPSR or SPSR */
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void (*write_xpsr)(target_t *target, u32 xpsr, int spsr);
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void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
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void (*write_xpsr)(target_t *target, u32 xpsr, int spsr); /**< Function for writing to CPSR or SPSR */
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void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr); /**< Function for writing an immediate value to CPSR or SPSR */
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void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
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void (*load_word_regs)(target_t *target, u32 mask);
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@@ -88,20 +91,20 @@ typedef struct arm7_9_common_s
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void (*store_hword_reg)(target_t *target, int num);
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void (*store_byte_reg)(target_t *target, int num);
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void (*write_pc)(target_t *target, u32 pc);
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void (*write_pc)(target_t *target, u32 pc); /**< Function for writing to the program counter */
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void (*branch_resume)(target_t *target);
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void (*branch_resume_thumb)(target_t *target);
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void (*enable_single_step)(target_t *target, u32 next_pc);
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void (*disable_single_step)(target_t *target);
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void (*set_special_dbgrq)(target_t *target);
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void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
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void (*pre_debug_entry)(target_t *target);
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void (*post_debug_entry)(target_t *target);
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void (*pre_debug_entry)(target_t *target); /**< Callback function called before entering debug mode */
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void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
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void (*pre_restore_context)(target_t *target);
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void (*post_restore_context)(target_t *target);
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void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
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void (*post_restore_context)(target_t *target); /**< Callback function called after restoring the processor context */
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armv4_5_common_t armv4_5_common;
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void *arch_info;
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